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شيت دمحمددسوقى


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  • 1. SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT1Q1-What are the three basic Binary Logic operatios , their truthtables , and their logic diagramesthree basic logical operations called AND, OR, and NOT:when (X,Y,Z are binary variables equal 1 or 0)AND Z = X • Y is called Z equal X AND YOR. Z = X + Y is called Z equal X OR Y −NOT. Z= X is called Z equal NOT XThe truth tables for the operations are shown in following TableLogic Gat diagrames:Q2- what is the Boolean algebra with example 1
  • 2. The Boolean algebra is an algebra dealing with binary variables and logicoperations as example the function F is afunction in logic variablesX,Y,Z. F ( X ,Y , Z ) = X + YZA Boolean function can be represented by a truth table.The truth table for the logic operation is number of rows in a truth table is2n, where n is the number of variables in the function. The binarycombinations for the truth table are the n-bit binary numbers thatcorrespond to counting in decimal from 0 through 2n – 1, the logicdiagrame for the function as following. SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT2Q3- what are Basic Identities of Boolean algebra 2
  • 3. Basic Identities of Boolean algebra are:Examples:1. X+XY=X(1+Y)=X2. XY + XY = X (Y + Y ) = X3. X + XY = ( X + X )( X + Y ) = X + Ymore examples:4. X ( X + Y ) = X + XY = X5. ( X + Y )( X + Y ) = X + YY = X6. X ( X + Y ) = XX + XY = XYQ4- what are meant by Dual, and its dual Boolean expressions?The dual expression is change the OR to AND and AND to ORXY to X+YX+Y to XYThe consensus theoremXY + XZ + YZ = XY + XZ 3
  • 4. The theorem shows that the third terrm, YZ, is redundant and can beeliminated. Note that Y and Z are associated with X and X in the firsttwo terms and appear together in the term that is eliminated.The dual of the consensus theorem is( X + Y )( X + Z )(Y + Z ) = ( X + Y )( X + Z )Q5- draw the logic diagram for the following function , and using theBoolean algebra to simplify it , then draw the simplified logicdiagram for the simplified function with truth table check fortwo function F = XYZ + XYZ + XZThe three terms in the expression are implemented with three AND gates,,one OR, and two NOT.Now consider a simplification of the expression for F byapplying Boolean algebra: F = XYZ + XYZ + XZ F = XY ( Z + Z ) + XZ by identity 14 F = XY .1 + XZ by identity7Truth table for function check a, and b: 4
  • 5. Q6- what is the Demorgan’s theorem, using it to complementthe Functions:The the Demorgan’s theorem for complement the expressions are:X + Y = X ⋅YX .Y = X + YX =XQ7- Find the complements of thru function in example 1-1 bytaking the duals of the equations and complementing eachliteral. 5
  • 6. SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT3Q8- what are the Minterms and Maxtermsa- Minterms: A product term in which all the variables appear exactly once,either complemented or uncomplemented, is called a minterm.b- Maxterms: A sum term that contains all the variables incomplemented or uncomplemented form is called a maxterm. 6
  • 7. Note from Tables a minterm and maxterm with the same subscript are thecomplements of each other; that is, Mi = mi .Q9- represents the following logic function with minterm and maxterm froma given truth table:By examining the truth tables for these minterms it is evident that the function Fcan be expressed algebraically as the logical sum of the stated minterms:F = XY Z + XYZ + XY Z + XYZBoolean Function of Three Variables can be further abbreviated by listing onlythe decimal subscripts of the minterms:F ( X , Y , Z ) = ∑ m(0,2,5,7) 7
  • 8. Note that if the function contains all minterms, it is equal to 1.F by maxterm:This shows the procedure for expressing a Boolean function as aproduct of maxterms. The abbreviated form for this product is F ( X , Y , Z ) = Π M (1,3,4,6)Q10- draw the logic diagram for the following functionsusing Sum of Products, and Product of sum:a-Sum of Products An example of logical a Boolean function expressed as a sum ofproducts is F = Y + XYZ + XYThe AND gates followed by the OR gate form a circuit configurationreferred to as a two-level implementation .If the expression not in the standard form of sum of product, theexpression can be converted to a sum of products by applying theappropriate distributive law as follows:F = AB + C(D + E) = AB + CD +CEThe function F is implemented in a nonstandard form in Figure 1-6(a).This requires two AND gates and two OR gates. There are three levels ofgating in the circuit. F is implemented in sum-of-products form in Figure1-6(b). 8
  • 9. b- Product of Sums F = X (Y + Z )( X + Y + Z )This expression has sum terms of one, two, and three literals. The sum termsperform an OR operation, and the product is an AND operation. SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT4,5Q11-draw the Karnaug map (K-map) for two, three, and fourvariables for Simplifying a Boolean Function :a-Two-Variable MapThere are four minterms 9
  • 10. Figure 1-9(b) shows the map for the logical sum of three minterms: m1 + m2 + m3 = XY + XY + XY = X + YThe optimized expression X + Y is determined from the two-square areafor the variable X in the second row and the two-square area for Y in thesecond column.b- Three-Variable MapThe characteristic of the listed sequence is that only one bit changes invalue from one adjacent column to the next, which corresponds to theGray code. In general, Three-variable maps exhibit the following characteristics:One square represents a minterm of three literals.A rectangle of two squares represents a product term of two literals.A rectangle of four squares represents a product term of one literal. 10
  • 11. A rectangle of eight squares produces a function that is always equal to logic 1 as in the following figures: c- Four-Variable Map There are 16 minterms for four binary variables, and therefore, a four- variable map consists of 16 squares, as shown :The combinations of squares that can be chosen during the optimizationprocess in the four-variable map are as follows:One square represents a minterm of four literals.A rectangle of 2 squares represents a product term of three literals.A rectangle of 4 squares represents a product term of two literals.A rectangle of 8 squares represents a product term of one literal.A rectangle of 16 squares produces a function that is always equal to logic 1. Q12- Simplifying a Boolean Function Using a K-Map F ( X , Y , Z ) = ∑ m(2,3,4,5) 1-Fill K- map with minterms 11
  • 12. 2- The optimized expression for F: F = XY + XYQ13- Simplifying a Boolean Function Using a K-Map F1(X,Y.Z) = Sm(3.4,6,7) F2 (X,Y,Z) = Sw(0,2,4,5.6)The map for F1 is shown in Figure 1-13(a). There are four squares markedwith 1s, one for each minterm of the function. Two adjacent squares arecombined in the third column to give a two-literal term YZ. Theremaining two squares with 1s are also adjacent by the cylinder-baseddefinition and are shown in the diagram with their values enclosed in halfrectangles. When combined, these two squares give the two-literal termXZ .The optimized function thus becomes F 1= YZ + XZ 12
  • 13. And with the same procedures F2 = Z + XYQ14- Simplify the following two Boolean functions F1(X,Y.Z) = ∑ m(1,3.4,5,6)F2 (X,Y,Z) = ∑ m(1,2,3,5.7)As in the fig1.14a the minterms 1, and 3 give the term XZ ,minterms 4, and 6 give term XZ . The minterm 5 can becombined with the minterm 4 to give XY or minterm 1 to giveY Z so :F1(X,Y.Z) = ∑ m(1,3.4,5,6) = XZ + XZ + Y ZFor the F2 as in fig.2.14b the minterms 1,3,4,7 combined and give theterm Z, the minterm 2 combined with minterm 3 to give the term XY so :F2 (X,Y,Z) = ∑ m(1,2,3,5.7) = Z + XYQ15- Simplifying a 4-Variable Function with a MapF(W,X,Y,Z) = ∑ m(0,l,2,4,5,6,8,9,10,12,13) 13
  • 14. As in the fig. minterms 0, 1,4, 5, 8, 9, 12, 13 the eight mintermscombined to give the term Y .The remaining term 2,6,14. The 6, 14,combined with 4, 12 to give X Z , and 2,6 combined with 0,4 to give termW Z so F simplified as: F= Y + X Z + W ZQ16- Simplifying a 4- Variable Function with a Map F = ∑ m(0,1,2,6,12,13,14)As in the fig. minterms 0, 1,8,9 the four minterms combined to give theterm B C .The remaining term 2,6,10. The 2,10 combined with 0,8 to give B D , and 6 combined with 2 to give term A CD so F simplified as: F= B C + B D + A CDQ17- Simplifying a 4- Variable Function with a Map usingdon’t care condition: 14
  • 15. Consider the following incompletely specified function F that has threedont-care minterms d:F(A,B,C,D) = ∑ m(l,3,7,11,15)d(A,B,C,D) = ∑ m(0,2,5)As in the next fig.a the dont care is signed by x sign. The minterms 3, 7,11, 15 are combined to give term CD the remaining minterm 1, 2 iscombined with dont care minterm 0,3 to give term A BSo the simplified F function is as:F= CD+ A BAs in fig.b minterms 3, 7, 11, 15 combine to give CD, minterms 1,3,7combined with dont care minterm 5 to give A DQ18- explain exclusive-or, and exclusive-NOR with gatesThe exclusive-OR (XOR), denoted by ⊕ , is a logical operation thatperforms the function X ⊕ Y = XY + XYIt is equal to 1 if exactly one input variable is equal to l.The exclusive-NOR, also known as the equivalence, is the complement ofthe exclusive-OR and is expressed by the function 15
  • 16. X ⊕ Y = XY + XYIt is equal to 1 if both X and Y are equal to 1 or if both are equal to 0.for more than two variablesThe exclusive-OR is replaced by the odd function; there is no symbol forexclusive-OR for more than two inputs.By duality, the exclusive-NOR is replaced by the even function and hasno symbol for more than two inputs.Q18- explain Odd Function, and even functionOdd FunctionThe exclusive-OR operation with three or more variables can beconverted into an ordinary Boolean function by replacing the ⊕ symbolwith its equivalent Boolean expression as follows:X ⊕ Y ⊕ Z = ( X ⊕ Y ) Z + Z ( X ⊕ Y ) = ( XY + XY ) Z + Z ( XY + XY ) = XY Z + XYZ + XY Z + XYZThe Boolean expression clearly indicates that the three-variableexclusive-OR is equal to 1 if only one variable is equal to 1 or if all threevariables are equal to 1. Hence, whereas in the two-variable functiononly one variable need be equal to 1, with three or more variables an oddnumber of variables must be equal to 1. 16
  • 17. Next Figure(a) shows the map for the three-variable odd function. Thefour-variable case is shown in Figure (b).The odd function is implemented by means of two-input exclusive-ORgates, as shown in the next fig.b-even functionIt should be mentioned that the minterms not marked with 1s in the maphave an even number of 1s and constitute the complement of the oddfunction, called the even function.The even function is obtained by replacing the output gate with anexclusive-NOR gate. 17
  • 18. Q19-draw The symbols, truth tables, and function for different types ofgates First year computer science Introduction to Computer Organization CHAPTER TWO 18
  • 19. ARITHMETIC FUNCTIONS AND CIRCUITS LEC. 6,72-1 Binary addersAn arithmetic circuit is a combinational circuit that performs arithmeticoperation? Such as addition, subtraction, multiplication, and division withbinary numbers or with decimal numbers in a binary code. We willdevelop arithmetic circuits by means of hierarchical, iterative design. Webegin at the lowest level by finding a circuit that performs the addition oftwo binary digits. This simple addition consists of four possibleelementary 0 +0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10. The first threeoperations produce a sum requiring only one bit to represent it, butwhen both the augend and addend are equal to 1, the binary sumrequires two bits. Because of this case, the result is alwaysrepresented by two bits, the carry and the sum. The carryobtained from the addition of two bits is added to the nexthigher order pair of significant bits.A combinational circuit that performs the addition of two bits iscalled a half adder.One that performs the addition of three bits (two significant bitsand a previous carry) is called a full adder.The names of the circuits stem from the fact that two halfadders can be employed to implement a full adder. The halfadder and the full adder are basic arithmetic blocks with whichother arithmetic circuits are designed.Half Adder 19
  • 20. A half adder is an arithmetic circuit that generates the sum of twobinary digits. The circuit has two inputs and two outputs. The inputvariables are the augend and addend bits to be added, and theoutput variables produce the sum and carry. We assign the symbolsX and Y to the two inputs and S(for "sum") and C (for "carry") tothe outputs. The truth table for the half adder is listed in Table 3-1.The C output is 1 only when both inputs are l. The S outputrepresents the least significant bit of the sum. table 2.1The Boolean functions for the two outputs, easily obtained fromthe truth table, are:S = XY + XY = X ⊕ YC = XY 20
  • 21. The half adder can be implemented with one exclusive-OR gateand one AND gate, as shown in fig.2.1Figure 2-1 Logic Diagram of Half AdderFull AdderA full adder is a combinational circuit that forms arithmetic sumoff three input bits. Besides the three inputs it has two ouputs.Two of the inputs are denoted by X and Y, represent the twosignificant bits to be added . the third input Z represents thecarry from the previous lower significant position.the twooutput are designated by symbols S for sum, and C for carry asin table 3.2.the S is equal to 1 when only one input equal to oneor when all three inputs are equal to one.the carry is 1 if twoinput equal 1 or three inputs equal 1. Truth table 2.2 21
  • 22. The simplified sum of of product functions for the two output are:The Boolean function for full adder in terms of exlusive ORoperation can be expressed as:The maps as in fig.2.2 , and the logic diagram as in fig.2.3. 22
  • 23. Fig. 2.2 maps for full adder Fig. 2.3 logic diagram full adderBinary Ripple Carry AdderA parallel binary adder is a digital circuit that produces the arithmeticsum of two binary numbers using only combinational logic. The paralleladder uses n full adders in parallel, with all input bits appliedsimultaneously to produce the sum. The full adders are connected incascade, with the carry output from one full adder connected to the carryinput of the next full adder Since a 1 carry may appear near the leastsignificant bit of the adder and yet propagate through many full adders tothe most significant bit, just as a wave ripples outward from a pebbledropped in a pond, the parallel adder is referred to as a ripple carry adder 23
  • 24. Figure 2-4 shows the interconnection of four full-adder blocks to form a4-bit ripple carry adder. The augend bits of A and the addend bits of B aredesignated by subscripts in increasing order from right to left, withsubscript 0 denoting the least significant bit. The carries are connected ina chain through the full adders. The input carry to the parallel adder is C0,and the output carry is C4. An n-bit ripple carry adder requires n fulladders, with each output carry connected to the input carry of the next-higher-order full adder.FIGURF 2-4 4bit Ripple carry AdderFor example, consider the two binary numbers A = 1011 and B = 0011.Their sum, S = 1110, is formed with a 4-bit ripple carry adder as follows: 24
  • 25. 2-2 Binary subtraction2-2-1 binary adder-subtractorsThe circuit for subtracting A - B consists of a parallel adder asshown in Figure 2-4, with inverters placed between each Bterminal and the corresponding full-adder input. The input carryC0 must be equal to l.The operation that is performed becomes Aplus the 1s complement of B plus 1. This is equal to A plus the2s complement of B. For unsigned numbers, it gives A - B if A>B or the 2s complement of (B – A) if A< B.The addition and subtraction operations can be combined intoone circuit with one common binary adder. This is done byincluding an exclusive-OR gate with each full adder. A 4-bitadder-subtractor circuit is shown in Figure 2-5. Input S controlsthe operation. When S=0 the circuit is an adder, and when S = 1the circuit becomes a subtracter. Each exclusive-OR gatereceives input S and one of the inputs of B, Bi . When S = 0, wehave Bi ⊕ 0. If the full adders receive the value of B. and the 25
  • 26. input carry is 0, the circuit performs A plus B. When S = 1, wehave Bi ⊕ 1 = Bi and C0 = 1. In this case, the circuit performs theoperation A plus the 2s complement of B. Fig.2.5 adder subtractor circuitSigned Binary NumbersThe convention is to make the sign bit 0 for positive numbers, 1for negative numbers. If the binary number is signed, then theleftmost represents the sign and the rest of the bits represent thenumber. If the binary number is assumed to be unsigned, thenthe leftmost bit is the most significant bit of number. Table 2.3show the signed binary numbers 26
  • 27. Table 2-3Signed Binary Addition and SubtractionIf tne number is negative we replaced by the 2s complement,and then add, if the most significant bit is zero the result value ispositive valu. If the most significant bit is 1 the result is negativeant is in the 2s complement form, to get the exact value we getits complement.Example:Note that in the case of unsigned number the negative number replacedby its complement, and then add, if there is carry its ignored and the 27
  • 28. result is positive. if there is no carry the result is negative , and the resultis in complemt value , if we need the exact value replace the result by itscomplement valus.OverflowTo obtain a correct answer when adding and subtracting, we must ensurethat the result has a sufficient number of bits to accommodate the sum. Ifwe start with two n-bit numbers, and the sum occupies n + 1 bits, we saythat an overflow occurs.Example:Note that the 8-bit result that should have been positive has anegative sign bit and that the 8-bit result that should have beennegative has a positive sign bit. If, however, the carry out of thesign bit position is taken as the sign bit of the result, then the 9-bit answer so obtained will be correct. But since there is noposition in ilic result for the 9th bit, we say that an overflow hasoccurred.2-3 BINARY MULTIPLICATIONMultiplication of binary numbers is performed in the same wayas with decimal numbers. The multiplicand is multiplied by eachbit of the multiplier, starting from the least significant bit. Each 28
  • 29. such multiplication forms a partial product. Successive partialproducts are shifted one bit to the left. The final product isobtained from the sum of the partial products.To see how a binary multiplier can be implemented with acombinational circuit, consider the multiplication of two 2-bitnumbers, as shown in Figure 2-6. The multiplicand bits are B0and B1, the multiplier bits are A1 and A0, and the product isC3C2C1C0 as in figure 2-6. Fig.2.6 2 bit binary multiplierExampleMultiply binary number 1 0 1, and 010 01 x 10 00 01 00 0010 29
  • 30. CHAPTER Three SEQUENTIAL CIRCUITS LEC. 8,93.1 sequential circuits To this point, we have studied only combinational logic. In order toperform useful or flexible sequences of operations, we need to be able toconstruct circuits that can store information between the operations.Such circuits are called sequential circuits. A block diagram of a sequential circuit is shown in Figure 3-1. Acombinational circuit and storage elements are interconnected to formthe sequential circuit. The sequential circuit receives binary informationfrom its environment via the inputs. These inputs, together with thepresent state of the storage elements to determine the binary value ofthe outputs and the storage element next state. Figure 3.1 block diagram of a sequential circuit The storage elements used in clocked sequential circuits that calledflip –flops. A flip –flop is a binary storage device capable of storing onebit of information and having timing characteristics. The block diagramof a synchronous clocked sequential circuit is shown in Figure 3-2. 30
  • 31. The flip – flops receive their inputs from the combinational circuit andalso from a clock signal with pulses that occur at fixed intervals of time. Figure 3.2 synchronous clocked circuit3.2 LatchesA storage element can maintain a binary state indefinitely until.directed by an input signal to switch statesSR Latches 3.2.1The latch has two inputs, labeled S for set and R for reset, and twouseful states When output Q=1 =1and Q =0, the latch is said to be in _the set state. When Q =0 and Q=1, it is in the reset state. Outputs Q _and Q are normally the complements of each other. When bothinputs are equal to 1 at the same time, an undefined state with bothoutputs equal to 0 occurs as in figure 3.3. 31
  • 32. Figure 3.3 SR Latch with NOR gatesIn normal operation these problems area avoided by making sure that1s are not applied to both inputs simultaneously. The behavior of theSR latch described in the preceding paragraph is illustrated by thelogic simulator waveforms shown in Figure 3.4 Initially. Figure 3-4 logic simulation of SR latch behaviourThe SR latch with two cross –coupled NAND gates is shown in Figure3.5. It operates with both inputs normally at 1, unless the state of the latchhas to be changed. The application of a 0 to the S input causes output Qto go to1.putting the latch in the set state. When the S input goes back to1, the circuit remains in the set state with both inputs at 1. The state if the 32
  • 33. latch is changed by placing a 0 on the R input. This causes the circuit to go to the reset state and stay there even after both inputs return to 1. The condition that is undefined for this NAND latch is when both inputs are equal to 0 at the same time, an input combination that should be avoided.Figure 3.5 Latch with nand gates The operation of the basic NOR and NAND latches can be modified by providing an additional control input that determines when the state of the latch can be changed. An SR latch with a control input is shown in Figure 3.6. It consists of the Figure 3.6 SR Latch with control The D latch in VLSI circuits is often constructed with transmission gates (TGs). As shown in Figure -3.8. The C input controls two TGs. When C=1, the TG connected to input D conducts, and the TG connected to output Q disconnects .this produces a path from input D through two 33
  • 34. Figure ١.٨D latch with transmition gatesFigure 3.8D latch with transmition gatesInverters to output Q, thus, the output follows the data input as long as cremains active (1). When C changes to 0, the first TG disconnects input Dfrom the circuit and the second TG connects the two inverters at theoutput into a loop. Hence, the value that was present at input D at thetime that C went from 1 to 0 is retained at the Q output by the loop. Flip –Flops 3-3Any changes in the data input will change the state of the latch. Inthis sense the latch is transparent, since its input value can be seenfrom the outputs. The key to the proper operation is to prevent themfrom being transparent. In a flip-flop, before an output can change, thepath from its inputs to its outputs is broken. There are two ways that latches are combined to form a flip-flop.One way is to combine two latches such that (1) the inputs presentedto the flip-flop when a clock pulse is present control its state and (2)the state of the flip-flop changes only when a clock pulse is not present.Such a circuit is called a master-slave flip-flop. Another way is to 34
  • 35. produce a flip-flop that triggers only during a signal transition from 0to 1 (or from 1 to 0) on the clock pulse. Such a circuit is said to be anedge triggered flip-flop.3.3.1 Master-slave Flip-FlopsThe master-slave SR flip-flop, consisting of two latches and aninverter, is shown in Figure 3.9. When the clock input C is 0, theoutput of the inverter is 1. The slave latch is then enabled, and itsoutput Q is equal to the master output Y. the master latch is disabled,because C is 0. When logic 1 clock pulse is applied, the values on S andR control the value stored in the master latch Y. The slave, however, isdisabled as long as the pulse remains at the 1 level, because its C input isequal to 0. Any changes in the external S and R inputs change the master output Y, Figure 3.9 SR master slaves Flip-Flopbut cannot affect the slave output 0. When the pulse returns to 0, themaster is disabled and is isolated from the S and R inputs. At the sametime, the slave is enabled, and the current value of Y is transferred to theoutput of the flip-flop at Q. 35
  • 36. 3.3.2D flip-flop A master-slave D flip-flop can be constructed from the SR master-slave flip-flop by simply replacing the master SR latch with a master D latch. The resulting circuit is shown in Figure 3.10. The resulting circuit changes its value on the negative edge of the clock Figure 3.10 Negative edge-triggered D Flip-Flop For the clock input equal to 0, the master latch is enabled and transparent andFigure 3.11 positive edge-triggered D Flip-Flop follows the D input value. The slave latch is disabled and holds the state of the flip-flop fixed. When the positive edge occurs, the clock input changes to 1. This disables the master latch so that its value is fixed and enables the slave latch so that it copies the state of the master latch. The state of the master latch to be copied is the state that is present at the positive edge of the clock. Thus .the behavior appears to be edge triggered with the clock input equal to 1.the master latch is disabled and cannot change so the state of both the master and the slave remain unchanged finally. When the clock input changes from 1 to O. the master is enabled before any change 36
  • 37. in the master can reach it. Thus the value stored in the slave remainsunchanged during this transition.3.3.3 JK and T filp-flopThe JK flip-flop was a modified version of the master-slave SR. when SRproduces undefined output for S=1, R=1, the JK cause the output tocomplement its current value. _ _Q(t + 1) = J (t ) Q(t ) + k (t )Q(t ) The T (toggle) flip-flop is equivalent to JK with J and K tied together sothat J=K=1are applied. If we take the characteristic equation for the JKand make this connection the equation becomes: _ _ T exclusive-ORQQ(t + 1) =T Q + TQ = T ⊕Q Standard graphics symbolsThe stander graphics symbols for the different types of latches and flip-flops are shown in Figure 3-12.Aflip –flop or latch is designated by arectangular block with inputs on the left and outputs on the right. Oneoutput designates the normal state of the flip-flop, and the other, with abubble, designates the complement output. 37
  • 38. Figure 3.13 flip-flop logic characteristic tables , Characteristic equations, and excitation table See fig.11Figure 3.12 standard graphics symbols for latches and flip-flops See fig.9 38
  • 39. Characteristic table: the table defines the next state Q(t+1) as a functionof the present state Q(t) , and inputs of D, or S,R, or J,K, or T. note thatthe pulse at C is not listed, it is assumed to occur between time t, and t+1.Characteristic equation: it defines the next state after the clock pulse asa function of present state, and Flip-flop inputs.Excitation table: these tables define the Flip-flops input value as afunction of next state value after the clock pulse, given the present statevalues.Sequential circuit analysis: we are given the flip-flop inputs, and askedto give the corresponding output. To do that we must knew thecharacteristic table of the given flip-flop. 39
  • 40. Sequential circuit design: the inverse of analysis, given present state,and next state, required designing the input of the flip-flop; we mustknow the excitation table of the given flip-flop.e.g for D type analysis Q(t), Q(t+1) design D 40