Fan-Out Wafer Level Packaging 2016 Patent Landscape report published by Yole Developpement

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With Apple and TSMC changing the game, 2016 is a turning point for the Fan-Out market. The number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position.

FAN-OUT IP LANDSCAPE IS THE MOST DYNAMIC IN ADVANCED PACKAGING
With Apple and its A10 processor employing TSMC’s InFO-PoP technology, the fan-out market has exploded. Apple’s involvement will undoubtedly generate increased interest in the fan-out platform, and market revenue is forecast to reach around US$2.5B in 2021, with 80% growth between 2015 - 2017 (See Yole Développement’s August 2016 report, Fan-out: Technology & Market Trends 2016). Moreover, following the high-volume adoption of InFO and the further development of fan-out wafer level packaging technologies, a wave of new players may enter the market. The supply chain is also expected to evolve, with a considerable amount of investment in Fan-Out packaging capabilities.

In such a fast-growing Fan-Out market, it is essential to deeply understand the global patent landscape in order to anticipate changes, harvest business opportunities, mitigate risks, and make strategic decisions in order to strengthen one’s market position and maximize return on one’s IP portfolio.

Knowmade has thoroughly investigated the Fan-Out packaging patent landscape (chip-first, chip-last, face-down, face-up, single-die, multi-chip module, package-on-package, system-in-package, etc.), and this report contains detailed patent analyses including countries of filing, patents’ legal status, and patented technologies, as well as patent owners, their IP position, and IP strategies.
More than 3,100 patents relating to over 1,200 inventions on Fan-Out packaging have been published worldwide through September 2016, coming from 100+ patent applicants. A first wave of patent applications occurred from 1999-2006, induced by Infineon. Patent applications have increased since then, with Freescale (NXP), STATS ChipPAC (JCET), SPIL, Amkor, and TSMC entering the Fan-Out IP arena. Today the number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position.
All of major players involved has filed patents on Fan-Out packaging, except for Nanium, which does not file any patents at all but instead has adopted a different IP strategy that we discuss in this report. Another special case is the presence of patent licensing companies like Polaris Innovations (WiLAN), which in 2015 acquired key patents from Infineon/Qimonda. The visibility of such companies in the patent landscape is a tangible sign of the market explodes. In the next few years Polaris Innovations could assert its patents to make money, and in this report we present its most critical patents. We have also noted Samsung’s conspicuous presence IP presence in the FOWLP patent landscape, de

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Fan-Out Wafer Level Packaging 2016 Patent Landscape report published by Yole Developpement

  1. 1. © 2016 | www.knowmade.com KnowMadePatent & Technology Intelligence Source: TSMC Source: STATS ChipPAC Source: Nepes Source: Deca Technologies Source: Infineon Source: ASE Fan-Out Wafer Level Packaging Patent Landscape Analysis November 2016
  2. 2. 2 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TABLE OF CONTENT INTRODUCTION 5 • Definitions • Scope of the report • Key features of the report • Objectives of the reports • Methodology MARKET TRENDS 21 NOTEWORTHY NEWS 24 EXECUTIVE SUMMARY 27 PATENT LANDSCAPE OVERVIEW 42 • Time evolution of patent applications • Major offices of patent applications • Time evolution of patent applications by country • Main patent assignees • Industry supply-chain • Technology history • Time evolution of main patent assignees • Acceleration of main patent assignees • Countries of priority patents for patent assignees • Countries of patent filings for patent assignees • Legal status of patents for main patent assignees • Remaining lifetime of granted patents • Geographic map of granted patents and pending patent applications • Countries of granted patents and pending patent applications for main patent assignees • IP collaboration network • Main patent transactions • Licensing agreements • IP competitors dependency by patent citations • Most cited patents • Granted patents near expiration date IP POSITION OF MAIN PATENT ASSIGNEES 71 • IP specialization degree • Prior art strength index • IP leadership • IP blocking potential • IP enforcement potential • The best IP positions • Summary of patent portfolios • Comparison of patent portfolios of the main IDMs, Foundries and OSATs PATENT LITIGATIONS 83 PATENT SEGMENTATION 85 For each segment: Number of patents, Time evolution of patent publications and main patent assignees, Matrix of patent assignees vs. technical segments, Matrix of technology vs. process steps/technical challenges/architecture, Matrix of main patent applicants vs. technical segments TECHNICAL CHALLENGES 94 • Solutions found in patents to solve warpage and die shift issues IP PROFILE OF KEY PLAYERS 132 Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple. Each IP profile includes: time evolution of patent applications, world map of granted patents and pending patent applications, key features and strength of patent portfolio. CONCLUSION 218
  3. 3. 3 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 INTRODUCTION Scope of the report (1/2) Die embedded in epoxy mold compound RDL Foundry BEOL Die embedded in organic laminate Lamination around the chip Cavity dig in substrate Coreless substrate Chip-first / Chip-last Face-down / Face-up Chip-first / Chip-last Face-down / Face-up Chip-last Face-down / Face-up Embedded packaging technologies with interconnections fanned out of IC surface Dies embedded in laminated materials This type of package, also known as «embedded die» package is based on PCB manufacturing capability and therefore is not in the same category as Fan-Out technologies using molding compound: Resolution is lower (L/S of 10um or higher), type of tools used are different, most of actors are different (more substrate makers than OSATs or IDMs) and end-markets are different with more simple applications targeted. Mold compound embedding on top of advanced-substrate (PCB type) solution (standard or coreless) This type of package can also be considered as a Flip-Chip CSP. In the same way as dies embedded in laminated materials, Knowmade is not focusing this report on this type of technology because the resolution achieved and the end-markets targeted are different. Scope of this report Fan-Out Wafer Level Packaging (FOWLP)
  4. 4. 4 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 INTRODUCTION Scope of the report (2/2) • This report provides a detailed picture of the patent landscape for Fan-Out wafer level packaging (FOWLP). All patents related to Fan-Out packaging were considered: chip-first, chip-last, face-down, face-up, single chip, multi-chip module, system-in-package (SiP), package-on-package (PoP), face-to-face package (F2F), stacked dies … • This report covers patents published worldwide up to September 2016. We have selected and analyzed more than 3,160 patents and patent applications grouped in more than 1,260 patent families relevant to the scope of this report. Included in the report Not included in the report • Patents related to “Fan-Out” solutions that are embedding dies in laminated materials. • Patents related to “Fan-Out” solutions where the mold compound embedding is on the top of advanced-substrate (PCB type), standard or coreless. • Patent related to “Fan-Out” solutions that are using other design of package. • Patents related to “Fan-Out” solutions that are embedding dies in a mold compound and are not using laminated advanced substrate for the redistribution layers (RDL). eWLB (Infineon, Nanium, STATS ChipPAC, ASE …), RCP (Freescale/NXP, Nepes …), InFO (TSMC), SWIFT & SLIM (Amkore), NTI/SLIT (SPIL/Xilinx), M-Series (Deca, ASE), CHIEFS & CLIP (PTI), WDoD (3D PLUS), etc… Fan-In WLP Leadframe (QFN,QFP ) WB BGA FC CSP / FC BGA 3D IC TSV interconnect Interposer based Embedded die Coreless FC
  5. 5. 5 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 INTRODUCTION Key features of the report (1/2) • The report provides essential patent data for Fan-Out wafer level packaging (chip-first, chip-last, face-down, face-up, single chip, multi- chip module, SiP, PoP, etc…). • It provides in-depth patent analyses of key technologies and key players including: – IP trends including time evolutions and countries of patent filings. – Current legal status of patents. – Ranking of main patent applicants. – IP collaborations, joint developments and licensing agreements. – IP position of key players and relative strength of their patent portfolios. – Segmentation of patents by technology solution (chip-first/face-down, chip-first/face-up, chip-last), process steps (die placement, molding, planarization, RDL …), architecture (multi-chip module, PoP, SiP, face-to-face package …), technical challenge (warpage, die shift). – Matrix showing patent applicants and their patented technologies. – Technical solutions found in patents for warpage and die-shift issues. • The “Fan-Out” IP profiles of 18 key companies is presented, including countries of filings, legal status of patents, patented technologies, prior-art strength index, IP blocking potential, partnerships and IP strategy: Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple
  6. 6. 6 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 INTRODUCTION Key features of the report (2/2) • The report also provides an extensive Excel database with all patents analyzed in the report (3,100+ patents), including technology segmentation. • This useful patent database allows multi-criteria searches, including: - Patent publication number - Hyperlinks to the original documents - Priority date - Title - Abstract - Patent assignees - Technical segmentation (chip-first/face-down, chip-first/face-up, chip-last, die placement, molding, planarization, RDL … multi-chip module, PoP, SiP, face-to-face package … warpage, die shift). - Legal status for each member of the patent family • Disclaimer: This report does not provide any insight analyses or counsel regarding legal aspects or the validity of any individual patent. KNOWMADE is a research firm that provides technical analysis and technical opinions. KNOWMADE is not a law firm. The research, technical analysis and/or work proposed or provided by KNOWMADE and contained herein is not a legal opinion and should not be construed as such.
  7. 7. 7 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 INTRODUCTION Objectives of the report Understand the competitive environment from technology and patent perspective Understand technology & market from a patent perspective. Understand the patent landscape. Identify risks & opportunities. Comprehend key trends in IP and technology development. List the major players and the relative strength of their patent portfolio. Name new players. Identify IP collaboration networks between key players (industrial and academic). Position key players within the value chain and understand their strategic decisions. Understand the competitive landscape, your current and future competitors. Understand your competitors’ strategic direction and future product offerings. Determine your competitors’ strengths and weaknesses. Identify current legal status of patented technologies. Identify key patents by assignees and technology. Identify blocking and valuable patents. Overview of past and current litigations and licensing agreements. Avoid patent infringement. Appreciate the link between the patent landscape and market evolutions. Discover new markets & technology directions. Identify untapped areas and opportunities to direct R&D and patenting activity.
  8. 8. 8 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 MARKET TRENDS (1/2) Fan-Out wafer level packaging (FOWLP) began volume commercialization in 2009/2010 with initial push by Intel Mobile. Start was promising but limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – and few customers. Later on, in 2012, big fab-less wireless/mobile players started slowly to require volume production after qualifying the technology for larger scope of applications including RF, Audio Codec, PMIC/PMU and more … And this growth was confirmed among time with a market size of around US$244 million in 2015 (“Fan-out: Technology & Market Trends 2016” report, Yole Développement, August 2016). 2016 is a turning point for the Fan-Out market since Apple and TSMC changed the game and may create a trend of acceptance of Fan-Out packages. Today, with Apple and its A10 processor using the InFO-PoP technology of TSMC, the market explodes. According to Yole Développement, the fan-out activity revenues forecast should reach about US$2.5billion in 2021, with 80% growth between 2015 and 2017. The Apple getting involved will clearly bring more and more interest to the fan- out platform. Following high volume adoption of InFO and further development of eWLB technology, a wave of new players and FOWLP technologies may enter the market. Source: Yole Développement (“Fan-out: Technology & Market Trends 2016” report, August 2016)
  9. 9. 9 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Time evolution of patent applications for FOWLP Patent activity in the field of fan-out wafer level packaging 3,160+ patents (1,260+ patent families*), including 1,600+ granted patents and 1,200+ pending patent applications Note: Due to the delay between the filing of patents and the publications by patent offices, usually 18 months, the data corresponding to the year 2015 and 2016 may not be complete since most patents filed during these years are not published yet. * A patent family is a set of patents filed in multiple countries by a common inventor(s) to protect a single invention.
  10. 10. 10 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Time evolution of patent applications split by countries Time evolution of countries of patent filings in the field of fan-out wafer level packaging • The USA is the first country of patent filings since the beginning of patenting activity in FOWLP field. • Decrease of the share of European filings since mid-2000s. • Increase of patent filings in Asia since 2010, especially in China. Note: Europe includes patents filed in European countries and patents for which the European procedure was the filed document (EP patents). The European applications (EP patents) may hide countries that are not yet published.
  11. 11. 11 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Main patent applicants for FOWLP
  12. 12. 12 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Time evolution of main patent assignees involved in FOWLP * A patent family is a set of patents filed in multiple countries by a common inventor(s) to protect a single invention. Note: Due to the delay between the filing of patents and the publications by patent offices, usually 18 months, the data corresponding to the year 2015 and 2016 may not be complete since most patents filed during these years are not published yet.
  13. 13. 13 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Number of patents and corresponding legal status for main patent assignees in FOWLP field
  14. 14. 14 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Remaining lifetime of granted patents for main patent assignees in FOWLP field
  15. 15. 15 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Geographic map of granted patents and pending patent applications in FOWLP field
  16. 16. 16 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Countries of granted patents and pending patent applications for main patent assignees in FOWLP field
  17. 17. 17 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW IP collaboration network in FOWLP field • Number in black on each link between patent assignees is the number of co-assigned patent families in the data set of the study. • Number up right to each bubble is the number of patent families for this applicant in the data set of the study. Bubble size is proportional to the number of patent families selected for the study.
  18. 18. 18 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Licensing agreements
  19. 19. 19 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LANDSCAPE OVERVIEW Most cited patents in FOWLP field
  20. 20. 20 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Degree of IP specialization in FOWLP field
  21. 21. 21 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Prior art strength index (*) Internal citations refer to citations coming from the corpus of patents selected for the study. External citations refer to citations coming from patents not selected for the study. (**) A relative impact factor (R.I.F) of 2 indicates that the patent portfolio is cited by two times more different patent families than the average of the corpus selected for the study. In other terms, the patent portfolio has two times more impact than the average. (***) Prior Art Strength Index = Relative Impact Factor multiplied by the number of patent families. The prior art strength index is based on the number of different patent families citing the patent portfolio. It indicates the impact of the patents on the prior art compared to other patents.
  22. 22. 22 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Prior art strength index (citations from all technology fields)
  23. 23. 23 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS IP leadership in FOWLP field
  24. 24. 24 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS IP blocking potential in FOWLP field
  25. 25. 25 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Potential future plaintiffs in FOWLP field
  26. 26. 26 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS The best IP positions in FOWLP patent landscape
  27. 27. 27 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Summary of patent portfolios
  28. 28. 28 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 IP POSITION OF KEY PLAYERS Comparison of FOWLP patent portfolios held by the main IDMs, Foundries and OSATs OSAT: Outsource Semiconductor Assembly and Test IDMs: Integrated Device Manufacturers
  29. 29. 29 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT LITIGATIONS The situation could rapidly change due to the market adoption
  30. 30. 30 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT SEGMENTATION Number of patents, time evolution of patent publications and main patent assignees
  31. 31. 31 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT SEGMENTATION Matrix of patent assignees vs. technical segments
  32. 32. 32 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT SEGMENTATION Matrix of technology vs. process steps/technical challenges/architecture
  33. 33. 33 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT SEGMENTATION Matrix of main patent applicants vs. technical segments
  34. 34. 34 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 PATENT SEGMENTATION Matrix of main patent applicants vs. technical segments
  35. 35. 35 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 WARPAGE Warpage issue for Fan-Out packaging Warpage remains a major challenge for Fan-Out, and it will be even more critical with panels. In the case of FOWLP, wafer can bend and bow due to mechanical stress during mold curing and debonding of the reconstituted wafer. Warpage leads to complications or the impossibility of following process steps once the wafer is bent due non-uniformity of the substrate (alignment issues, non-uniformity of depositions, etc…) which can result in yield loss. It creates stress on dies, which can damage them, and also can damage adhesive after RDL. The encapsulation layer has a thermal expansion coefficient (CTE) higher than those of other constituents is formed on both lateral sides and upper sides of the dies, thus the die package warps, thereby deteriorating the reliability of the die package. Warpage is a big challenge. The epoxy mold wafers can be warped after curing, and the size and shape of the warpage can change for different shapes and density of the embedded die. In an effort to reduce cost and package height, the thickness of the substrate reduces too, although this tends to make the wafer less stiff and therefore flatten under gravity.
  36. 36. 36 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 WARPAGE Technical solutions found in patent to solve warpage issue for Fan-Out packaging
  37. 37. 37 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 WARPAGE Technical solutions found in patent to solve warpage issue for Fan-Out packaging
  38. 38. 38 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 WARPAGE Technical solutions found in patent to solve warpage issue for Fan-Out packaging
  39. 39. 39 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 WARPAGE Technical solutions found in patent to solve warpage issue for Fan-Out packaging
  40. 40. 40 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 DIE SHIFT Die shift issue for chip-first Fan-Out packaging Die shift during molding and mold curing is one of the major processing hurdles in chip-first FOWLP processes. It limits pitch capability and yield. Die shift is an unwanted movement of the chip after placing it on the carrier and depositing the molding. It results from shrinkage of the mold during curing. It can go up to several tens of microns. The consequence of die shift is an inaccurate alignments of die pads of reconfigured wafers which can cause yield losses. In case of multi-components FOWLP there can be die shifts in different directions within the same package. This is a critical issue which limits integration capability. Source: Yole Développement The thermal release tape is flexible. During a molding process, the coefficient of thermal expansion (CTE) of the thermal release tape and lateral forces from the encapsulant can likely cause positional deviation of the semiconductor chips (that is, positions of the semiconductor chips are deviated from a chip areas), thereby adversely affecting the positional accuracy of the semiconductor chips. The larger the size of the carrier is, the more severe the positional deviation of the semiconductor chips becomes. As such, the electrical connection between the redistribution structure (RDL) and the semiconductor chips is adversely affected, and consequently the product yield is reduced.
  41. 41. 41 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 DIE SHIFT Technical solutions found in patent to solve die shift issue for chip-first Fan-Out packaging
  42. 42. 42 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 DIE SHIFT Technical solutions found in patent to solve die shift issue for chip-first Fan-Out packaging
  43. 43. 43 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 DIE SHIFT Technical solutions found in patent to solve die shift issue for chip-first Fan-Out packaging
  44. 44. © 2016 All rights reserved | www.knowmade.com IP PROFILE OF KEY PLAYERS
  45. 45. 45 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC (Taiwan Semiconductor Manufacturing Company) InFO technology
  46. 46. 46 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC (Taiwan Semiconductor Manufacturing Company) InFO technology
  47. 47. 47 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC (Taiwan Semiconductor Manufacturing Company) IP profile in Fan-Out wafer level packaging
  48. 48. 48 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC’s InFO-PoP Teardown analysis of the Apple’s A10 APE
  49. 49. 49 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC’s InFO-PoP from Apple’s A10 APE XXXXXXXXXXXXX
  50. 50. 50 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 TSMC’s InFO-PoP from Apple’s A10 APE XXXXXXXXXXXXXXX
  51. 51. 51 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 APPLE Fan-Out technology Apple chose the TSMC’s InFO-PoP technology for its A10 APE in 2016. According to Yole Développement, the entrance of TSMC as a supplier of Fan-Out packaging for Apple’s APE made a big change, with the market expected to jump from $244M in 2015 to $821M in 2017 (“Fan-out: Technology & Market Trends 2016” report, Yole Développement, August 2016). Apple has filed some patents on Fan-Out wafer level packaging in 2014-2015, including chip-last/chip-first solutions, Package-on-Package and System-in- Package. This recent patenting activity reflect a real interest for the FOWLP platform.
  52. 52. 52 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 POLARIS INNOVATIONS (WILAN) Patents on fan-out wafer level packaging Polaris Innovations
  53. 53. 53 © 2016 All rights reserved | www.knowmade.com Fan-Out Wafer Level Packaging – Patent Landscape Analysis | November 2016 CONTACT o Consulting and Specific Analysis – North America: Steve LaFerriere, Director of Northern America Business Development, Yole Inc. Email: laferriere@yole.fr – Europe: Lizzie Levenez, Europe Middle East and Africa Business Development Manager, Yole Développement Email: levenez@yole.fr – Japan: Takashi Onozawa, General Manager, Yole Japan & President, Yole K.K. Email: onozawa@yole.fr – RoW: Jean-Christophe Eloy, President & CEO, Yole Développement Email: eloy@yole.fr o Report business – North America: Steve LaFerriere, Director of Northern America Business Development, Yole Inc. Email: laferriere@yole.fr – Europe: Fayçal El Khamassi, Headquarter Sales Coordination & Customer Service Email: khamassi@yole.fr – Japan & Asia: Takashi Onozawa, Sales Asia & General Manager, Yole K.K. Email: onozawa@yole.fr o Financial services – Jean-Christophe Eloy, CEO & President Email: eloy@yole.fr o General: Email: info@yole.fr
  54. 54. More than 3,100 patents relating to over 1,200 inventions on Fan-Out packaging have been published worldwide through September 2016, coming from 100+ patent applicants. A first wave of patent applications occurred from 1999-2006, induced by Infineon. Patent applications have increased since then, with Freescale (NXP), STATS ChipPAC (JCET), SPIL, Amkor, and TSMC entering the Fan-Out IP arena. Today the number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position. All of major players involved has filed patents on Fan-Out packaging, except for Nanium, which does not file any patents at all but instead has adopted a different IP strategy that we discuss in this report. Another special case is the presence of patent licensing companies like Polaris Innovations (WiLAN), which in 2015 acquired key patents from Infineon/Qimonda. The visibility of such companies in the patent landscape is a tangible sign of the market explodes. In the next few years Polaris Innovations could assert its patents to make money, and in this report we present its most critical patents. We have also noted Samsung’s conspicuous presence PATENT LANDSCAPE ANALYSIS Fan-Out Wafer Level Packaging Patent Landscape Analysis – November 2016 With Apple and TSMC changing the game, 2016 is a turning point for the Fan-Out market. The number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position. REPORT OUTLINE • Fan-Out Wafer Level Packaging Patent Landscape Analysis • November 2016 • PDF (200+ pages) • Excel file (3,100+ patents) • €5,990 (Multi-user license) KEY FEATURES OF THE REPORT • IP trends, including time evolutions and countries of patent filings • Patents’ current legal status • Ranking of main patent applicants • IP collaboration, joint development, and licensing agreements • Key players’ IP position, and relative strength of their patent portfolios • Patent segmentation by technology solution (chip-first, chip-last, face- down, face-up), process steps (die placement, molding, planarization, RDL), architecture (multi-chip, PoP, SiP, face-to-face package), and technical challenge (warpage, die shift) • Matrix showing patent applicants and their patented technologies • Technical solutions found in patents for warpage and die-shift issues. • FOWLP IP profiles for 18 key companies, including countries of filing, patents’ legal status, patented technologies, prior art strength index, IP blocking potential, partnerships, and IP strategy • Excel database with all patents (3,100+) analyzed in this report, including technology segmentation RELATED REPORTS • Fan-out: Technology & Market Trends 2016, Yole Développement, August 2016 • TSMC Integrated Fan-Out (inFO) Package in Apple’s A10 Application Processor, System Plus Consulting, October 2016 • Samsung’s Galaxy S7 Processor Packages: Qualcomm/Shinko’s MCeP vs. Samsung’s PoP, System Plus Consulting, June 2016 FAN-OUT IP LANDSCAPE IS THE MOST DYNAMIC IN ADVANCED PACKAGING With Apple and its A10 processor employing TSMC’s InFO-PoP technology, the fan-out market has exploded. Apple’s involvement will undoubtedly generate increased interest in the fan- out platform, and market revenue is forecast to reach around US$2.5B in 2021, with 80% growth between 2015 - 2017 (See Yole Développement’s August 2016 report, Fan-out: Technology & Market Trends 2016). Moreover, following the high-volume adoption of InFO and the further development of fan-out wafer level packaging technologies, a wave of new players may enter the market. The supply chain is also expected to evolve, with a considerable amount of investment in Fan-Out packaging capabilities. In such a fast-growing Fan-Out market, it is essential to deeply understand the global patent landscape in order to anticipate changes, harvest business opportunities, mitigate risks, and make strategic decisions in order to strengthen one’s market position and maximize return on one’s IP portfolio. Knowmade has thoroughly investigated the Fan-Out packaging patent landscape (chip-first, chip-last, face-down, face-up, single-die, multi-chip module, package-on-package, system-in- package, etc.), and this report contains detailed patent analyses including countries of filing, patents’ legal status, and patented technologies, as well as patent owners, their IP position, and IP strategies. Knowmade © 2016 Patent activity in the field of fan-out wafer level packaging Distributed by
  55. 55. The 1,200+ inventions selected for this study are categorized by technology solution (chip-first/face-down, chip-first/face-up, chip- last), process steps (die placement, molding, planarization, RDL), architecture (multi-chip module, PoP, SiP, face-to-face package, etc.) and technical challenges (warpage, die shift). In this report we also reveal the IP strategy and technical choices of the main patent assignees. A special focus is placed on technical solutions found in patents for solving warpage and die shift issues. This report also provides an IP profile for 18 key players: Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, and Apple. Each company’s IP profile includes the time evolution of their patent applications, a world map of granted patents and pending patent applications, and key features and strength of their patent portfolio. KNOW THE KEY PLAYERS’ IP POSITION PATENTED TECHNOLOGY AND IP STRATEGY USEFUL PATENT DATABASE (3,100+ patents) This report also includes an Excel database containing the 3,100+ patents analyzed in our study. This useful patent database allows for multi-criteria searches and includes patent publication number, hyperlinks to the original documents, priority date, title, abstract, patent assignees, technological segments, and legal status for each patent family member. IP blocking potential of main patent assignees involved in fan-out wafer level packaging Knowmade © 2016 Fan-Out Wafer Level Packaging: Patent Landscape Analysis - November 2016 IP presence in the FOWLP patent landscape, despite the company’s unclear market position. R&D labs are also present (i.e. Fraunhofer, A*STAR, CEA), but to a lesser extent. Most new entrants in the FOWLP patent landscape are Chinese players (HuaTian Technology, NCAP, SMIC), and more recently we have observed Apple’s appearance. Apple, which this year chose TSMC’s InFO-PoP technology for its A10 APE, has recently filed some patents on Fan-Out wafer level packaging (chip-last, chip-first, PoP, and SiP), reflecting a genuine interest in the FOWLP platform. This report analyzes in detail the IP status and IP strategies of key players and provides an understanding of their patented technologies. This report also provides a ranking and analysis of the top patent holders’ relative strength, derived from their portfolio size, patent citation networks, countries of patent filing, and patents’ current legal status. Furthermore, we reveal the IP strength of the key IP players involved in FOWLP technologies, and we depict their competitive IP position. JCET/STATS ChipPAC and TSMC lead the FOWLP patent landscape. From a quantitative point of view, TSMC is the most prolific patent applicant of the last few years, but according to our analyses, JCET/STATS ChipPAC has by far the strongest IP position. The company has formidable Patented technologies of main patent assignees involved in fan-out wafer level packaging Knowmade © 2016 formidable “IP blocking potential” that empowers it to deter other players to patent inventions that are similar to its own IP portfolio. TSMC is the most serious IP challenger, and it may reshape the patent landscape in the near future upon the approval of its numerous pending patent applications. Both companies feature a large enforceable patent portfolio and a long remaining lifetime of their patents.
  56. 56. TABLE OF CONTENT Dr Nicolas Baron is CEO and co-founder of Knowmade. He leads the Physics Department. He holds a PhD in Physics from the University of Nice Sophia- Antipolis, and a Master of Intellectual Property Strategies and Innovation from the European Institute for Enterprise and Intellectual Property (IEEPI Strasbourg), France. nicolas.baron@knwowmade.fr AUTHOR COMPANIES MENTIONED IN THE REPORT 3D Plus, A*STAR, ACE Technology, ADL Engineering, Altera, Amkor, Apple, ASE, Avago Technologies, Bridge Semiconductor, Bridgelux, Broadcom, Camtek, CEA, Cheng Ming, ChipMOS, Cirrus Logic, Conexant Systems, Cypress Semiconductor, Dainippon Screen Manufacturing, Deca Technologies, EPIC Technologies, EV Group, Flipchip International, Fraunhofer, Fujitsu, GE Embedded Electronics, General Electric, Gerad Technologies, GlobalFoundries, Hana Micron, Hitachi Chemical, HuaTian Technology, Infineon, Intel, ITRI (Industrial Technology Research Institute), JCAP, JCET/STATS ChipPAC, J-Devices, Jiangsu University of Science & Technology, LSI Logic, Macrotech Technology, Maxim Integrated Products, MediaTek, Medtronic, Micron Technology, Murata Electronics, NCAP, Nepes, Niko Semiconductor, Nippon Electric Glass, Nitto Denko, North Star Innovations (WiLAN), NXP/Freescale, Nytell Software, Oerlikon, PacTech Packaging Technologies, Philips, Polaris Innovations (WiLAN), Powertech Technology, Princo Middle East FZE, Qimonda, Qualcomm, Renesas Electronics, Samsung Electronics, Samsung Electro Mechanics, Semiconductor Components Industries, Seoul National University (SNU), Sharp, Shinko Electric Industries, SK Hynix, SMIC, Sony, Sound Technology, SPIL, STMicroelectronics, Technische Universitat Berlin, Tera Probe, Tessera, Texas Instruments, Toray Advanced Mat Korea, Toshiba, TSMC, Ultratech, Unimicron Technology, United Microelectronics, United Test & Assembly Center, X-Celeprint, Xenogenic Development (Intellectual Ventures), Xilinx, Xintec, Zhongxin Changdian Semiconductor … INTRODUCTION 5 - Definitions - Scope of the report - Key features of the report - Objectives of the reports - Methodology MARKET TRENDS 21 NOTEWORTHY NEWS 24 EXECUTIVE SUMMARY 27 PATENT LANDSCAPE OVERVIEW 42 - Time evolution of patent applications - Major offices of patent applications - Time evolution of patent applications by country - Main patent assignees - Industry supply-chain - Technology history - Time evolution of main patent assignees - Acceleration of main patent assignees - Countries of priority patents for patent assignees - Countries of patent filings for patent assignees - Legal status of patents for main patent assignees - Remaining lifetime of granted patents - Geographic map of granted patents and pending patent applications - Countries of granted patents and pending patent Applications for main patent assignees - IP collaboration network - Main patent transactions - Licensing agreements - IP competitors dependency by patent citations - Most cited patents - Granted patents near expiration date IP POSITION OF MAIN PATENT ASSIGNEES 71 - IP specialization degree - Prior art strength index - IP leadership - IP blocking potential - IP enforcement potential - The best IP positions - Summary of patent portfolios - Comparison of patent portfolios of the main IDMs, Foundries and OSATs PATENT LITIGATIONS 83 PATENT SEGMENTATION 85 For each segment: number of patents, time evolution of patent publications and main patent assignees, Matrix of patent assignees vs. technical segments, Matrix of technology vs. process steps & technical challenges/architecture, Matrix of main patent applicants vs. technical segments TECHNICAL CHALLENGES 94 - Solutions found in patents to solve warpage and die shift issues IP PROFILE OF KEY PLAYERS 132 Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple. Each IP profile includes: time evolution of patent applications, world map of granted patents and pending patent applications, key features and strength of patent portfolio. CONCLUSION 218 Fan-Out Wafer Level Packaging: Patent Landscape Analysis - November 2016 Knowmade is a Technology Intelligence and IP Strategy consulting company specialized in analysis of patents and scientific information. The company supports R&D organizations, industrial companies and investors in their business development by helping them to understand their IP environment and follow technology trends. Knowmade is involved in Microelectronics & Optoelectronics, Compound Semiconductors, IC Manufacturing & Advanced Packaging, Power & RF Devices, MEMS & Sensors, Photonics, Micro & Nanotechnology, Biotech/Pharma, MedTech and Agri- Food. Knowmade provides Prior art search, Patent Landscape Analysis, Patent Valuation, Freedom-to-Operate Analysis, Litigation/Licensing support, Scientific Literature Landscape, Technology Scouting and Technology Tracking. Knowmade combines information search services, technology expertise, powerful analytics tools and proprietary methodologies for analyzing patents and scientific information. Knowmade’s analysts have an in-depth knowledge of scientific & patent databases and Intellectual Property. We Know Technology, We Know Patents ABOUT KNOWMADE
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  59. 59. More than 3,100 patents relating to over 1,200 inventions on Fan-Out packaging have been published worldwide through September 2016, coming from 100+ patent applicants. A first wave of patent applications occurred from 1999-2006, induced by Infineon. Patent applications have increased since then, with Freescale (NXP), STATS ChipPAC (JCET), SPIL, Amkor, and TSMC entering the Fan-Out IP arena. Today the number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position. All of major players involved has filed patents on Fan-Out packaging, except for Nanium, which does not file any patents at all but instead has adopted a different IP strategy that we discuss in this report. Another special case is the presence of patent licensing companies like Polaris Innovations (WiLAN), which in 2015 acquired key patents from Infineon/Qimonda. The visibility of such companies in the patent landscape is a tangible sign of the market explodes. In the next few years Polaris Innovations could assert its patents to make money, and in this report we present its most critical patents. We have also noted Samsung’s conspicuous presence PATENT LANDSCAPE ANALYSIS Fan-Out Wafer Level Packaging Patent Landscape Analysis – November 2016 With Apple and TSMC changing the game, 2016 is a turning point for the Fan-Out market. The number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position. REPORT OUTLINE • Fan-Out Wafer Level Packaging Patent Landscape Analysis • November 2016 • PDF (200+ pages) • Excel file (3,100+ patents) • €5,990 (Multi-user license) KEY FEATURES OF THE REPORT • IP trends, including time evolutions and countries of patent filings • Patents’ current legal status • Ranking of main patent applicants • IP collaboration, joint development, and licensing agreements • Key players’ IP position, and relative strength of their patent portfolios • Patent segmentation by technology solution (chip-first, chip-last, face- down, face-up), process steps (die placement, molding, planarization, RDL), architecture (multi-chip, PoP, SiP, face-to-face package), and technical challenge (warpage, die shift) • Matrix showing patent applicants and their patented technologies • Technical solutions found in patents for warpage and die-shift issues. • FOWLP IP profiles for 18 key companies, including countries of filing, patents’ legal status, patented technologies, prior art strength index, IP blocking potential, partnerships, and IP strategy • Excel database with all patents (3,100+) analyzed in this report, including technology segmentation RELATED REPORTS • Fan-out: Technology & Market Trends 2016, Yole Développement, August 2016 • TSMC Integrated Fan-Out (inFO) Package in Apple’s A10 Application Processor, System Plus Consulting, October 2016 • Samsung’s Galaxy S7 Processor Packages: Qualcomm/Shinko’s MCeP vs. Samsung’s PoP, System Plus Consulting, June 2016 FAN-OUT IP LANDSCAPE IS THE MOST DYNAMIC IN ADVANCED PACKAGING With Apple and its A10 processor employing TSMC’s InFO-PoP technology, the fan-out market has exploded. Apple’s involvement will undoubtedly generate increased interest in the fan- out platform, and market revenue is forecast to reach around US$2.5B in 2021, with 80% growth between 2015 - 2017 (See Yole Développement’s August 2016 report, Fan-out: Technology & Market Trends 2016). Moreover, following the high-volume adoption of InFO and the further development of fan-out wafer level packaging technologies, a wave of new players may enter the market. The supply chain is also expected to evolve, with a considerable amount of investment in Fan-Out packaging capabilities. In such a fast-growing Fan-Out market, it is essential to deeply understand the global patent landscape in order to anticipate changes, harvest business opportunities, mitigate risks, and make strategic decisions in order to strengthen one’s market position and maximize return on one’s IP portfolio. Knowmade has thoroughly investigated the Fan-Out packaging patent landscape (chip-first, chip-last, face-down, face-up, single-die, multi-chip module, package-on-package, system-in- package, etc.), and this report contains detailed patent analyses including countries of filing, patents’ legal status, and patented technologies, as well as patent owners, their IP position, and IP strategies. Knowmade © 2016 Patent activity in the field of fan-out wafer level packaging Distributed by
  60. 60. The 1,200+ inventions selected for this study are categorized by technology solution (chip-first/face-down, chip-first/face-up, chip- last), process steps (die placement, molding, planarization, RDL), architecture (multi-chip module, PoP, SiP, face-to-face package, etc.) and technical challenges (warpage, die shift). In this report we also reveal the IP strategy and technical choices of the main patent assignees. A special focus is placed on technical solutions found in patents for solving warpage and die shift issues. This report also provides an IP profile for 18 key players: Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, and Apple. Each company’s IP profile includes the time evolution of their patent applications, a world map of granted patents and pending patent applications, and key features and strength of their patent portfolio. KNOW THE KEY PLAYERS’ IP POSITION PATENTED TECHNOLOGY AND IP STRATEGY USEFUL PATENT DATABASE (3,100+ patents) This report also includes an Excel database containing the 3,100+ patents analyzed in our study. This useful patent database allows for multi-criteria searches and includes patent publication number, hyperlinks to the original documents, priority date, title, abstract, patent assignees, technological segments, and legal status for each patent family member. IP blocking potential of main patent assignees involved in fan-out wafer level packaging Knowmade © 2016 Fan-Out Wafer Level Packaging: Patent Landscape Analysis - November 2016 IP presence in the FOWLP patent landscape, despite the company’s unclear market position. R&D labs are also present (i.e. Fraunhofer, A*STAR, CEA), but to a lesser extent. Most new entrants in the FOWLP patent landscape are Chinese players (HuaTian Technology, NCAP, SMIC), and more recently we have observed Apple’s appearance. Apple, which this year chose TSMC’s InFO-PoP technology for its A10 APE, has recently filed some patents on Fan-Out wafer level packaging (chip-last, chip-first, PoP, and SiP), reflecting a genuine interest in the FOWLP platform. This report analyzes in detail the IP status and IP strategies of key players and provides an understanding of their patented technologies. This report also provides a ranking and analysis of the top patent holders’ relative strength, derived from their portfolio size, patent citation networks, countries of patent filing, and patents’ current legal status. Furthermore, we reveal the IP strength of the key IP players involved in FOWLP technologies, and we depict their competitive IP position. JCET/STATS ChipPAC and TSMC lead the FOWLP patent landscape. From a quantitative point of view, TSMC is the most prolific patent applicant of the last few years, but according to our analyses, JCET/STATS ChipPAC has by far the strongest IP position. The company has formidable Patented technologies of main patent assignees involved in fan-out wafer level packaging Knowmade © 2016 formidable “IP blocking potential” that empowers it to deter other players to patent inventions that are similar to its own IP portfolio. TSMC is the most serious IP challenger, and it may reshape the patent landscape in the near future upon the approval of its numerous pending patent applications. Both companies feature a large enforceable patent portfolio and a long remaining lifetime of their patents.
  61. 61. TABLE OF CONTENT Dr Nicolas Baron is CEO and co-founder of Knowmade. He leads the Physics Department. He holds a PhD in Physics from the University of Nice Sophia- Antipolis, and a Master of Intellectual Property Strategies and Innovation from the European Institute for Enterprise and Intellectual Property (IEEPI Strasbourg), France. nicolas.baron@knwowmade.fr AUTHOR COMPANIES MENTIONED IN THE REPORT 3D Plus, A*STAR, ACE Technology, ADL Engineering, Altera, Amkor, Apple, ASE, Avago Technologies, Bridge Semiconductor, Bridgelux, Broadcom, Camtek, CEA, Cheng Ming, ChipMOS, Cirrus Logic, Conexant Systems, Cypress Semiconductor, Dainippon Screen Manufacturing, Deca Technologies, EPIC Technologies, EV Group, Flipchip International, Fraunhofer, Fujitsu, GE Embedded Electronics, General Electric, Gerad Technologies, GlobalFoundries, Hana Micron, Hitachi Chemical, HuaTian Technology, Infineon, Intel, ITRI (Industrial Technology Research Institute), JCAP, JCET/STATS ChipPAC, J-Devices, Jiangsu University of Science & Technology, LSI Logic, Macrotech Technology, Maxim Integrated Products, MediaTek, Medtronic, Micron Technology, Murata Electronics, NCAP, Nepes, Niko Semiconductor, Nippon Electric Glass, Nitto Denko, North Star Innovations (WiLAN), NXP/Freescale, Nytell Software, Oerlikon, PacTech Packaging Technologies, Philips, Polaris Innovations (WiLAN), Powertech Technology, Princo Middle East FZE, Qimonda, Qualcomm, Renesas Electronics, Samsung Electronics, Samsung Electro Mechanics, Semiconductor Components Industries, Seoul National University (SNU), Sharp, Shinko Electric Industries, SK Hynix, SMIC, Sony, Sound Technology, SPIL, STMicroelectronics, Technische Universitat Berlin, Tera Probe, Tessera, Texas Instruments, Toray Advanced Mat Korea, Toshiba, TSMC, Ultratech, Unimicron Technology, United Microelectronics, United Test & Assembly Center, X-Celeprint, Xenogenic Development (Intellectual Ventures), Xilinx, Xintec, Zhongxin Changdian Semiconductor … INTRODUCTION 5 - Definitions - Scope of the report - Key features of the report - Objectives of the reports - Methodology MARKET TRENDS 21 NOTEWORTHY NEWS 24 EXECUTIVE SUMMARY 27 PATENT LANDSCAPE OVERVIEW 42 - Time evolution of patent applications - Major offices of patent applications - Time evolution of patent applications by country - Main patent assignees - Industry supply-chain - Technology history - Time evolution of main patent assignees - Acceleration of main patent assignees - Countries of priority patents for patent assignees - Countries of patent filings for patent assignees - Legal status of patents for main patent assignees - Remaining lifetime of granted patents - Geographic map of granted patents and pending patent applications - Countries of granted patents and pending patent Applications for main patent assignees - IP collaboration network - Main patent transactions - Licensing agreements - IP competitors dependency by patent citations - Most cited patents - Granted patents near expiration date IP POSITION OF MAIN PATENT ASSIGNEES 71 - IP specialization degree - Prior art strength index - IP leadership - IP blocking potential - IP enforcement potential - The best IP positions - Summary of patent portfolios - Comparison of patent portfolios of the main IDMs, Foundries and OSATs PATENT LITIGATIONS 83 PATENT SEGMENTATION 85 For each segment: number of patents, time evolution of patent publications and main patent assignees, Matrix of patent assignees vs. technical segments, Matrix of technology vs. process steps & technical challenges/architecture, Matrix of main patent applicants vs. technical segments TECHNICAL CHALLENGES 94 - Solutions found in patents to solve warpage and die shift issues IP PROFILE OF KEY PLAYERS 132 Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple. Each IP profile includes: time evolution of patent applications, world map of granted patents and pending patent applications, key features and strength of patent portfolio. CONCLUSION 218 Fan-Out Wafer Level Packaging: Patent Landscape Analysis - November 2016 Knowmade is a Technology Intelligence and IP Strategy consulting company specialized in analysis of patents and scientific information. The company supports R&D organizations, industrial companies and investors in their business development by helping them to understand their IP environment and follow technology trends. Knowmade is involved in Microelectronics & Optoelectronics, Compound Semiconductors, IC Manufacturing & Advanced Packaging, Power & RF Devices, MEMS & Sensors, Photonics, Micro & Nanotechnology, Biotech/Pharma, MedTech and Agri- Food. Knowmade provides Prior art search, Patent Landscape Analysis, Patent Valuation, Freedom-to-Operate Analysis, Litigation/Licensing support, Scientific Literature Landscape, Technology Scouting and Technology Tracking. Knowmade combines information search services, technology expertise, powerful analytics tools and proprietary methodologies for analyzing patents and scientific information. Knowmade’s analysts have an in-depth knowledge of scientific & patent databases and Intellectual Property. We Know Technology, We Know Patents ABOUT KNOWMADE
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