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2.5d 3dic tsv interconnects patent analysis 2013 Report by Yole Developpement

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2.5D, 3DIC and TSV Interconnect Patent Investigation Report …

2.5D, 3DIC and TSV Interconnect Patent Investigation Report

3DIC technology is seen today as a new paradigm for the future of the semiconductor industry: understanding the status of the patent situation is key to understanding the business situation.

A very young patent landscape dominated by 10 companies...
For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened. 52% of the families have been classified as relevant and further studied. The indepth analysis quickly revealed that the overall patent landscape was pretty young with 82% of patents filed since 2006. Actually about 260 players are involved in 3DIC technology while the top 10 assignees represents 48% of patents filed in the 3DIC domain! We selected 5 companies from these 10 most active players to focus on and lead an accurate analysis of their patent portfolios.
The report also provides a database of all the relevant patents we have analyzed in an Excel file which allows multi-criteria searching. The criteria are basically those we used for the technological segmentation:
• Patent information ◦Patent publication number
◦ Link to the PDF document
◦ Oldest priority date
◦ Title
◦ Assignee
◦ Patent potential ranking
◦ Nb of citing patent families

• Technological segmentation ◦Design
◦ Process: lithography, etching, metallization, passivation, filling, repassivation, UBM, bonding, thinning
◦ Test
◦ Architecture

• End Application mentioned ◦Memory
◦ Interposer
◦ Logic Sip / SoC

We found 4 main types of business models among the top 10 assignees involved in this mutating middleend area:
• Foundries and IDM: IBM, Samsung, Intel
• OSATs: STATS ChipPAC, Amkor
• Memory IDM/Foundries: Micron, SK Hynix, Elpida
• Research centers: ITRI

It is also interesting to notice that the USA is the early player increasingly involved in 3DIC since 1969. China and Korea are new players since 2005.
This complete description of the patent landscape is included in the first part of the report and provides all the background materials for the 3DIC patent landscape analysis. The report provides a complete analysis of the patent landscape including geographical origins of the patents, companies or R&D organizations that have been granted the patents, historical data on when the companies that have applied for patents in the last 20 years, inventors of the patents, expiration status, R&D collaborations…


Understanding the patent portfolio of the top 10 3DIC asignees
The report provides a deep dive into each of the patent portfolios of assignees selected by Yole Développement, including Intel, Samsung, Micron, IBM and TSMC.
For each of these companies, the report provides an in-depth analysis of its patent portfolio, highlighting the following points:
• Company patent portfolio evolution
• Countries of deposition and origin of the patents
• Top inventors

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  • 1. © 2013Copyrights © Yole Developpement SA. All rights reserved.2.5D, 3DIC and TSV InterconnectPatent Investigation ReportInfineonMicronSynopsysVTICEA LETIXilinx
  • 2. © 2013 • 2Copyrights © Yole Developpement SA. All rights reserved.Table of Contents• Why This Report?• Companies Cited in the Report• Introduction to 3DIC Technology• Methodology for Patent Screening, Analysis and Ranking• IP Landscape Overview• Global Patent Ranking and Patent Potential Analysis• Key Player Patent Portfolio Analysis– Focus on Intel Corporation– Focus on Samsung– Focus on Micron– Focus on IBM– Focus on TSMC• Conclusions and Perspectives• Introduction & Presentation of Yole’s Activity31112273654596086113136162187190
  • 3. © 2013 • 3Copyrights © Yole Développement SA. All rights reserved.Why This Report ?• After several years of specific analysis for customers, YOLE Développement lastyear started publishing reports on the analysis of the technical contents ofpatents• This new IP report is focused on the youngest advanced packaging technologicalplatform: 2.5D, 3DIC and TSV Interconnects• YOLE has developed a specific methodology in order to make such analysis,combining YOLE technical and business knowledge and classical access topatent databases
  • 4. © 2013 • 4Copyrights © Yole Développement SA. All rights reserved.What This Report Does and Does Not Include ?• It includes…– This IP report provides an overview of « who is owning what » in terms of patents for the 3DIC& 2.5D Interposer technologies, plus a dedicated focus on 5 players we consider as the mostactive in this area– The main report objectives are: To present the industrial and business status of the 3DIC today To define and provide a database of all the relevant patents with technological segmentation To detail architecture to be implemented To identify the key patents and the owners of such patents• It does not include…– Juridic analysis of patent portfolio– Deep link analysis (legal, juridic…) between assignees• To summarize, our work in the frame of the new kind of reports is toanalyze key patents to identify structuring concepts from a technologicalor an industrial point of view, leading to business and strategicconclusions
  • 5. © 2013 • 5Copyrights © Yole Développement SA. All rights reserved.Yole’s standardreports• Market analysis• Technology analysisA New Type of Report Providing a Clear Linkbetween IP Situation and Market Evolutions• More than a report describing a state of the art of an IP situation, this reportprovides a missing link between patented technological solutions and market,technological and business trends– YOLE has developed a unique methodology to define a technical segmentation of patent landscape,as well as define which patents are the most innovative, either for future use or already in production– By combining its technical knowledge, business understanding and patent search, this Yole report isable to provide unique analysis and added value.– In-depth technological analysis of patents provided in this report will lead to the understanding ofstrategic decisions and positioning of key players within the value chain3DIC Technological evolutions& Market evolutions3DIC IP landscapeYole’s new IP report• Relevant patents analysis• Technological segmentation• Detailed architecture to be implemented• Key patent identification• Links with the patents and available products
  • 6. © 2013 • 6Copyrights © Yole Développement SA. All rights reserved.Assumptions and Methodology (2/4)Phase II depends on Phase I results.
  • 7. © 2013 • 7Copyrights © Yole Développement SA. All rights reserved.Companies Cited in This ReportA*STAR, Altera, AMD, Amkor, Apple, ASTRI, Avago, ChinaWLCSP, CISCO, Cypress, DNP, Elpida, Epson, GMEMS,HITACHI, Hoya, IBM, IMEC, IMT MEMS, Infineon, Intel, IPDIA,Irvine sensor, ITRI, JCET, KAIST, LG inotek, Lsi, Maxim,Mediatek, Micron, Motorola, nVidia, NXP, OKI, Plan optik, PTI,Qualcomm, Samsung, Sibdi, Silex, SK-Hynix, Sony,StatsChipPAC, STMicroelectronics, Tecnisco, Teledyne Dalsa,Tessera, Tezzaron, TI, tMt, Toshiba, TSMC, Visera, VTI Murata,Xilinx, Xintec, and more !
  • 8. © 2013 • 8Copyrights © Yole Développement SA. All rights reserved.3D Integration: Halfway between SoC and SiP“All-in-One chip systemintegration Euphoria”3DIC technology is seentoday as a new paradigmfor the future of thesemiconductor industry,as it will enable severalmore decades of chipevolution at ever lowercost, higher performanceand smaller-sizefeatures.
  • 9. © 2013 • 9Copyrights © Yole Développement SA. All rights reserved.Why, When and How 3D?The rapid evolution of 3D thinking in the IC community is astonishing– Two years ago, the big question was “Why 3D?”– Today’s questions are “When 3D?” and “How 3D?”– In less than a decade from now, we will wonder “Why 2D?”Evolutionor Revolution?3DIC / 3D SoC“De-integrated & Re-integrated SOC”2D SOC“All-in-One chip system integration”All functions on 28nm lithography Chip area ↑, Cost ↑MEMS 130 nm 200 mmMemory 45 nm 300 mmLogic 22 nm ? 450 mm ?Analog 90 nm 300 mmThanks to 3D, heterogeneousfunctions are integrated:• On different lithography nodes• On different wafer sizes• In different wafer fabs• By different players Cost ↓, Performance ↑, Size ↓
  • 10. © 2013 • 10Copyrights © Yole Developpement SA. All rights reserved.Focus of the report !Targeted Platforms for the IP ReportAdvanced Packaging PlatformsRDLBumpingBallingWafer BondingTSVWL-OpticsWL-Capping2.5DInterposer3DICBallingWLCSPFOWLPEmbeddedICFlipChipMEMS ICCappingICSensorMemoryLogic3DWLCSPDie 1 Die 2 Die 3 Die 4Middle-End Process Steps
  • 11. © 2013 • 11Copyrights © Yole Developpement SA. All rights reserved.Definitions for Patent Analysis• Patent family– A patent family is a set of either patent applications or publications taken in multiple countries to protect a single invention by a commoninventor(s) and then patented in more than one country. A first application is made in one country – the priority – and is then extended to otheroffices.• Assignee (or applicant)– An assignee is a person or organization (e.g. company, university, etc.) who/which has filed a patent application. There may be more than oneassignee per application. The assignee may also be the inventor.• Priority date– The priority date is the date on which the patent application was filed. At this date the patent document is not made available to the public.• Priority Number– The priority number is the number of the application with respect to which priority is claimed, i.e. it is the same as the application number of theclaimed priority document. The priority number is made up of a country code (two letters), the year of filing (four digits) and a serial number(variable, maximum seven digits).• Publication date– The publication date is the date on which the patent application was first published. It is the date on which the patent document is made availableto the public, thereby becoming part of the state of the art.• Publication number– The publication number is the number assigned to a patent application on publication. Publication numbers are generally made up of a countrycode (two letters) and a serial number (variable, one to twelve digits) (eg DE202004009768).• International Patent Classification (IPC)– The technical content of patent documents is classified in accordance with the International Patent Classification (IPC). The publishing office assignsan IPC symbol valid at the time of publication of the patent application. The complete IPC can be found on the website of the World IntellectualProperty Organization (WIPO - http://www.wipo.int/ipcpub).
  • 12. © 2013Copyrights © Yole Développement SA. All rights reserved.IP Landscape Overview Distribution of All Analyzed Patents Overall Filing Trend Important Assignees
  • 13. © 2013 • 13Copyrights © Yole Developpement SA. All rights reserved.Trend of Patent Filing for 3DIC TechnologiesPatent Filing Trends for 3DIC Technologies• 1013 patent families were filed from 1969 to 2012• 82% of patents were filed since 2006Yole Developpement © December 20120204060801001201401601802002202402601968 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012No.ofPatentFamiliesPriority years
  • 14. © 2013 • 14Copyrights © Yole Developpement SA. All rights reserved.Evolution of Top 15 Priority Countries for3DIC Patents• Bubble size represent number of published patent families. Note that World (WO) andEurope (EP) codes may hide a significant portion of other countries patent activities• USA is the early player increasingly involved in 3DIC since 1969. China and Korea are newplayers since 2005Evolution of Top 15 Priority Country for 3DIC Patents (related and relevant included)Yole Developpement © December 2012
  • 15. © 2013Copyrights © Yole Développement SA. All rights reserved.Key Player PatentPortfolio Analysis Company profiles Patent distribution and evolution Key patent family ranking, most cited patent identification Patent mapping Qualitative analysis of key patents
  • 16. © 2013 • 16Copyrights © Yole Developpement SA. All rights reserved.Intel Patent Portfolio Analysis• As an Integrated Device Manufacturer (IDM), Intel is involved in bothDesign and Process development. However, almost 80% of the Intel’spatents are dedicated to 3DIC & TSV process optimizationDesign8%Process79%Architecture13%Intel Patent Portfolio AnalysisBreakdown by technological areaYole Developpement © January 2013
  • 17. © 2013 • 17Copyrights © Yole Developpement SA. All rights reserved.Intel Patents Describing TSV and 3DICManufacturing Processes• All the process steps for 3DIC manufacturing are described in Intel’s patents– Bumping is the main area patented by Intel– Followed by barrier/seed, TSV isolation, TSV etching and filling As an IDM, Intel is strongly focused on middle-end activities, epecially oninter/intraconnections for 3D stackingLithography4%Etching14%Isolation17%Barrier / Seed17%Filling14%Bump / Passivation /UBM /21%TB / TDB10%Thinning / Grinding3%Intel Patents Describing ProcessBreakdown by process stepYole Developpement © January 2013
  • 18. © 2013 • 18Copyrights © Yole Developpement SA. All rights reserved.Assignee(s) INTEL (US)Publication Number(representative member)US20060273455No. of citingpatent families48Oldest priority dateof the family2005-06-01 Legal status Alive: US20060273455Title Electronic packaging including die with through silicon viaWhat is claimed:- Die stacking through TSV, included in die, each active die separated withsilicon spacer- Restrictive use of package leadless or not, QFP, SOIC, TSOP- Definition of systems to use for this patentKey words: TSV, Die to die stack, PackageContext: Reduced size of electronics package. Stacked die development.Advantages / Prev.:- Solder joint on TSV, to join 2 die, and also act as a spacer- Shape of TSV with flexibility in the filling, not only metal, and can be filledby dielectric in the middle of the TSV. Improvement can be frommechanical point of view- Flexibility of TSV design, through RDL done in the BEOL of die, to routeTSV not adjacentWeakness:- Cup shape of TSV can consume more area than vertical TSV- Poor explanation on the description in the patentQualitative Analysis of Key Intel 3DIC Patents
  • 19. © 2013 • 19Copyrights © Yole Developpement SA. All rights reserved.Assignee(s) INTEL (US)Publication Number(representative member)US6229216No. of citingpatent families17Oldest priority dateof the family1999-01-11 Legal statusAlive: US6562653Dead: US6229216Title Silicon interposer and multi-chip-module (MCM) with through substrate viasWhat is claimed:- Die stacking package as shown in figure 3- Electronic cartridge use the previous die stacking package, including heatspreaderKey words: TSV, Interposer, PackageContext: IC package and thermal & mechanical aspects of package, with quality improvement.Advantages / Prev.:- Use of silicon interposer to connect plurality of IC, through solder bump(silicon is matching CTE of IC, reducing the stress on solder bump)- Interposer is built with TSV- Use of small interposer, to act as a fan out, in order that the maininterposer is not limited with pad pitchWeakness:- Final package integration not easy to industrialize- To bump top and bottom surface of interposer- Poor claimQualitative Analysis of Key Intel 3DIC Patents
  • 20. © 2013 • 20Copyrights © Yole Developpement SA. All rights reserved.Samsung Strategic Position in 3DIC PlatformsGlobal wafer forecast - breakdown by segment (12’’eq. wafers)• Samsung already owns IP and has 3D devices in production in 3D WLCSP and 3DICplatforms for CMOS image sensors (respectively FSI and BSI).• It is also involved in the hybrid memory cube consortium with SK-Hynix, Micron and IBM.This HMC is expected to be a key turning point in 2013 for 3DIC HVM manufacturing.• Finally, Samsung has strong 3D SiP/SoC activity and is expected to ship the first 3D APE in2015.-1 000 0002 000 0003 000 0004 000 0005 000 0006 000 0002 010 2 011 2 012 2 013 2 014 2 015 2 016 2 0173D Stacked NAND Flash - - - - - 8 877 20 130 288 1503D Wide IO Memory - - - - 110 215 252 005 896 565 1 429 417Logic 3D SiP / SoC - - - 8 694 55 694 235 157 565 294 1 043 0153D Stacked DRAM - 15 954 50 563 146 200 324 563 593 361 878 729 1 596 526MEMS / Sensors 92 18 664 49 431 62 119 104 941 158 674 228 727 305 883RF, Power, Analog & Mixed signal 10 723 16 027 23 006 39 654 61 102 84 445 110 921 146 403Imaging & Optoelectronics 42 578 85 874 132 977 174 210 244 701 338 943 449 618 603 606Wafercount(12eqwafers)3DIC Platform Wafer ForecastBreakdown by Segment (12eq wafers)Yole Developpement © July 2012TOTAL 53 394 136 519 255 977 430 877 791 001 1 419 457 2 253 420 5 413 001
  • 21. © 2013 • 21Copyrights © Yole Developpement SA. All rights reserved.About the Author of This ReportLionel Cadix– Lionel joined Yole after completing several projects linked to thecharacterization and modeling of high-density TSV and 3DIC chip stacking incollaboration with CEA-Leti and STMicroelectronics for his PhD. He is theauthor of several publications and holds eight patents in the field of 3DIntegrationContact: cadix@yole.fr
  • 22. © 2013 • 22Copyrights © Yole Developpement SA. All rights reserved.© 2012 • 22Media businessNews feed / Magazines /Webcastswww.yole.frMarket ResearchReportsMarket research,Technology & StrategyConsulting servicesYole activities in Advanced Packaging© 2010Copyrights© YoleDéveloppementSA.All rightsreserved.MEMS PackagingMarket & Technology Trends1995Sidebraze DIP1996-2002PlasticPDIP1999 - todaySMT SOIC& Die Down2006Stacked DieQFN~125 sqmm~100 sqmm ~25 sqmm6 & 6 mm1995Sidebraze DIP1996-2002PlasticPDIP1999 - todaySMT SOIC& Die Down2006Stacked DieQFN~125 sqmm~100 sqmm ~25 sqmm6 & 6 mm
  • 23. © 2013 • 23Copyrights © Yole Developpement SA. All rights reserved.© 2012 • 23Our latest market reports…TSV +Cost Analysis Tool foryour 3D IC manufacturingFlip-chip2013 ReportIPD - Thin-filmIntegrated Passive DevicesWL CSP2011 Report updateNokia3D Glass & Siliconinterposers - 2010 Report© 2010Copyrights © Yole Développement SARL. All rights reserved.Advanced PackagingEquipment & MaterialsNEC-SchottSUSS Brewer ScienceSTSEVGDuPontEquipment & Materialsfor Wafer-Level-Packaging© 2010Copyrights © Yole Développement SA. All rights reserved.MEMS PackagingMarket & Technology Trends1995Sidebraze DIP1996-2002Plastic PDIP1999 - todaySMT SOIC& Die Down2006Stacked DieQFN~125 sq mm ~100 sq mm ~25 sq mm6 & 6 mm1995Sidebraze DIP1996-2002Plastic PDIP1999 - todaySMT SOIC& Die Down2006Stacked DQFN~125 sq mm ~100 sq mm ~25 sq m6New!New!New!New!EmbeddedWafer Level PackagesNew!
  • 24. © 2013 • 24Copyrights © Yole Developpement SA. All rights reserved.For More Information …Take a look at our websiteswww.yole.frYole Développement corporate websitewww.i-micronews.comNews Portal - online free registration to our publicationswww.systemplus.frSister company expert in teardown & reverse costing analysiswww.yolefinance.comSeparate business unit of Yole dedicated to financial services

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