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### Prese000

1. 1. WAED Ibrahim Al- Islam IbrahimNAME: AL-faraheed shaqareen. ADC
2. 2. Analog to digital converter (ADC) circuit1- What is the Analog and digital signal?2- What is the ADC?3- Type s of ADC
3. 3. Objective of this experiment:To understand the concept and the principle of analog to digital conversions
4. 4. Analog and digital signalsAnalog signals are continuous in value and in - timeDigital signals are discrete in value and in time -
5. 5. Digital-to-Analog ConversionIn order to control analog outputs, digital outputs must first be converted toanalog form using a digital-to-analog converter (also referred to as a DAC orD/A converter). digital Analog D/A Converter Output Analog Output from digital (Digital Input to D/A Converter)Analog-to-Digital ConversionIn order to read analog inputs, the analog inputs must first be converted to digitalform using a an analog-to-digital converter (also referred to as a ADC or A/Dconverter). Analog A/D Converter DIGITAL Input Digital Output from A/D Converter
6. 6. -How we Convert analog signal into digital signal?we used ADC which is opposite of DAC in last experiment device forconverting analogue signals into digital signals or circuit that has single inputand multibit binary outputsThe number of output bits will determine the ADC resolution the number ofoutput bit is from 4 to 20 bit ADC with higher number of output bit will havehigher resolution
7. 7. To convert analog signal into digital signal using ADC the signal through three stage :1- sampling 2-quantizing
8. 8. 3- coding
9. 9. *Four circuits have been devised to perform A/D conversion:1- counter-ramp feedback ADC2- dual slope ADC3- sucessive approximation converter4- flash comparator ADC
11. 11. This circuit is contain DAC,COUNTER,COMPERATOR1-Vin : applied input analog signal is one input of comparator2-Vout : is the output of DAC which is the second input of comparator3- count(control line):if it is low the counter turn on and stop thecounter if it high4- output of comparator is connected to (count)and end puls5-start pulls connect to /clr that is initiate the counter (reset) itdetermine to start convert analog signal into digital value input signal6-clock (increment the counter) test signal7-D0-DN output that is digital value DAC b7 b0 counter
12. 12. Operation:1- analog signal input is applied on (vin)of the comparator2-start pulse is applied to counter and reset the 8-bit binary counter so it begincount from “0”3- counter generate signal from (b0-b7) which is input of DAC that convert itinto analog signal with vout4- if the voltage of input signal is higher than voltage on test signal (output ofDAC) then the output of the comparator is high so the clock will increment thecounter5- if the voltage of input signal is less than voltage on test signal (output ofDAC) then the output of the comparator is low so the enable the end pulse tostop the conversion of analog signal input signal test signal DAC b b0 7 counter
13. 13. -To find the maximum conversion time can be calculated as :2^n-1*clock period ( for example 8-bit counter with 100khz)so the max=1.28ms (n=number of bit in the counter)-advantages :It has simple structure-disadvantages :Very slow require 2^n-1 clock cycle to convert each sample
14. 14. 2- Dual slope ADC:It convert an unknown analog input to time interval that can be measured bycounterIt consists of integrator,comparator,control circuit ,BCD countar with 7-segmentlCD,lED
15. 15. Operation:1- when the analog input is applied on (vin )2- the control circuit will reset the counter and connect the analog input toinput of the integrator3- the integrator capacitor will start charging by integrating the analog inputfor afixed time period (t1) at the end of t1 output of the integrator is a functionof the analog input and the input of the integrator is switched to arefrencevoltage (vref)4- at this point the integrator capacitor will start discharching and the counterstart counting the discharge time t2 until the capacitor is completelydischarged5- when t2 is reached the comparator change its logic state and the counterstop counting the output of the counter is proportional to analog input6- when the capacitor is charging vout has negative slope ,when dischargingvref ,vin, vout have positive slope
16. 16. *T1,the vout=vin/rc*t1 So the vout have negative slope (charging time) *T2,the vout =vref*t2/rc So the vout have positive slope SO the unknown input voltage is expressed as t2/t1 vref
17. 17. Advantages of dual slope ADC :1- high accuracy2- inherent noise immunity
18. 18. Flash Comparator converter YOU can observe from the circuit that It consists from comparators and special type of encoder called priority encoder
19. 19. OBSERVATION ON CIRCUIT There are 7 ranges for each comparator starting from v/8,2v/8,........,v. Triggering comparator by voltage large than V/8 Binary output can be obtained if output of parallel comparators encoded using priority encoder. Now...................what is priorityencoder?
20. 20. Priority encoder :encoder circuit that includes priority function . It used when we have more than two outputs active "high (1)” at the same time so output will be input that has highest priority. Example suppose we have 4-inputs ,D0 has lowest priority and D1 has highest priority So truth table will be D0 D1 D2 D3 X Y V 0 0 0 0 X X 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
21. 21. Anlogevin W1 W2 W3 W4 W5 W6 W7 Y2 Y1 Y3 0~V/8 0 0 0 0 0 0 0 0 0 0 V/8~2V/8 1 0 0 0 0 0 0 0 0 12V/8~3V/8 1 1 0 0 0 0 0 0 1 03V/8~4V/8 1 1 1 0 0 0 0 0 1 14V/8~5V/8 1 1 1 1 0 0 0 1 0 05V/8~6V/8 1 1 1 1 1 0 0 1 0 16V/8~7V/8 1 1 1 1 1 1 0 1 1 17V/8~V 1 1 1 1 1 1 1 1 1 1
22. 22.  Example: Suppose that 5V/8<Vin<6V/8 so W1~W5 are equal to one & W6,W7 are 0 “1111100” binary output is Y2Y1Y0=101 *Features: Fastest but most expensive This type has fast conversion rate so number of shortcoming less Keep in mind ......if resolution improved this mean increase number of comparators and as result increase cost tremendously.
23. 23. SUCCESSIVE APPROXIMATION This type of ADC is improvement result from Counter ramp DADC. Observe that :  It consists of DAC and comparator Counter replaced by special circuit SAR ‘*successive Approximation Converter * MSB cause DAC output to be half input reference voltage. Next........................successive Circuit
24. 24. OPERATING CYCLE Conversion intiated:SAR=0but immediately MSB=1 but other bits lower still 0 Control circuit Comparator generate final compare DAC output and send to output with anlog Buffer circuit input Vin Final binary output If Vout>Vin so MSB=0 found so this mean and we go to the next “End of Conversion “ MSB=1 Vout compared with If Vin>VoutMSB=1 Vin and it will set or reset continuously. And next MSB=1
25. 25. Operating speed for successive converterOperating speed Number of Clock period bits *This type of converter has high speed operating cycle . *Most application use this type because of its high speed.
27. 27. WR control input when CS=0 and conversion start .  WR=0,Counter reset conversion start .when WR back to “1”. INT pin signals the end of conversionIt is =0 when conversion start and returns to 0when conversion ends. Vin(+),Vin(-) analogy signal inputs[negative and positive voltage] CLK IN clock input .
28. 28. MORE ABOUT........................ CK Clock frequency of converter Limited (100KHz-1460KHz] If CK frequency exceeds 1460KHz frequency divider used to reduce it. Now how ADC generate its own clock signals? Adding RC circuit between CLKIN ,CLK R . Frequency=1/(1.1 *R*C)
29. 29. ( Impedance R range (10-50K• Pin 9 manipulate to get different input voltage ranges.this mean we can control input voltage with out affected by supplied voltage.GND two types:*A GND for analog ground.*D GND for digital ground.Largest analog input into the ADC0804 is the fullscaleWhen input=Vref ,output FFhWhen pin 11 open Vref=Vcc
30. 30. Input impedance "resistor Resolution +capacitors” Accuracy: Conversion degree of Time: time non- required to linearity convert andinterference ADC specification analog input voltage to.[quantizing digital error] and Error output . resources OUT put stability:ADC code :in sensitivity to binary or temperature BCD change. Analog input voltage
31. 31. TafIlla Technical University(TTU)
32. 32. Synthesis of system level bus interfaces1- introduction2- problem formulation3- bus generation algorithm
33. 33. Introduction :In this paper the outhers implement single bus from set of communication channelsAnd we present a bus generation algorithm which determines the width of busImplemented and tradeoffs between the width of the bus and performance of theprocesses communicating over the bus this algorithm give the system level constraintssuch as data Transfer rate ,number of pins and allow several channels that may betransfer different sizes Of data to be implemented as single bus
34. 34. *How we partitioning system level :* A system can be viewed as set of processes which communicate witheach other over communication channels*System level partitioning in two groups:1- groups processes and variables in the system specification intomodules(representing chips and memories)2- groups the channels to be implemented by buses*Interface synthesis:Set of task performed to implement communication between modules in asystem
35. 35. Module 1 Process A Process A Variable IR,PC,ACCUM Variable Procedure receive(…) IR,PC,ACCUM ….. Procedure send(…) IR<=MEM(PC) STATUS<=X”0A” ….. MEM(AR)<=ACCUM Receive(busb ,PC ,IR) Bus generation ……Bus b Send(busb,”0A”) ……. ch1 Ch3 Send(busb ,AR ch2 ,ACCUM) Process A1 Process A2 BUS B Module 2 Variable Variable 8 bit MEM:intarray STATUS Process A2 Process A1 Variable STATUS Variable Procedure receive(…) MEM:intarray ………. Procedure send(….) Procedure receive(…) Loop Variables processes >modules Receive(busb,STATUS) Send(busb ,MEM) …… END LOOP Channels>buses Receive(bus, MEM)
36. 36. Figure 1 :- process A after system partitioning is mapped to two system modules-The variables MEM and STATUS mapped to processes A1 and A2 indifferent module-Process A processes reads and writes data to the variable MEM overchannels ch1 and ch2-STATUS is accessed over channel ch3-ch1,ch2,ch3 have been grouped into bus b-Bus generation is the interface synthesis task that determines the busstructure (number of data and control lines) for implementing group ofcommunication channels-It determines the buswidth bus generation directly affects two criticaldesign metrics:-Performance of the processes comunicating over bus-Interconnect cost of the modules measure number of wire and pin ofmodules
37. 37. After system partitioning we wish to synthesize a bus toimplement communication between different processescommunicating over channel each channel maytransfer data of different sizes Firstly we explain the problem formulation of bus generation and then we explain the algorithm which determine the bus width finaly we take about experiments with bus generation
38. 38. 1- computing bus and channel rates: Bus rate : Maximum rate at which data can be transferred across the busTo find the bus rate assume that-width(B) is the number of data line in bus b-delay (B) total delay used by process to transfer data over thebusSoBus rate(B)=Width(B)/Delay(B)
39. 39. To find the total execution time for any process consists of two components:1- computation time (comptime(p)) : average start to finish execution timerequired by process to perform all its internal computations (these computationsrepresent any statement in the process loop, conditional statements)2- communication time (commtime(p)): time spent by the process accessing dataexternal to process (variables which are in another process/module as result ofsystem partitioning) commTime(p)=Access(p , c)*(bits(C)/Width(b))*Delay(B) Where Access(p , c) represent the number of times process (p) will transfer data over channel (c) ,bit(c ) is inferred from the type of variable being accessed over channel c
40. 40. Channel average rate is defined as the rate at which data is sent over channel cover the lifetime of process communicating over rateChannel average rate (AveRate)=access(p , c)*Bits(c)/compTime(p)+commTime(p)Channel peak Rate: rate at which single data transfer over channel
41. 41. Average data transfer 8 8 rateChannel A A1 A2 (2*8bits)/4s=4b/s 16 16 16Channel B B1 B3 (3*16bits)/4s=12b/s B2 8 16 16 16 Bus AB A1 B1 B2 A2 B3 (4+12)=16 b/s t=0s t=1s t=2s t=3s t=4s Channel A sends 8 bits of data twice over the 4s ,channel B sends 16 bit of data (3)over the 4s,bus AB send different size of data 8BIT AND 16 BIT over 4s The peak rate of a is 8bit/s ,and of b is 16 bit/s
42. 42. 2- relating bus and channel rates:1-bus is more efficient implementation because it never idle and has100%utilization2-consider two channels A and B assume that the 4s time interval shown ofdata transfer over the life times of process communicate over channels Aand B3- channels A and B have average rates 4 and 12bit/s4- if channels A and B are implemented as single bus AB then the bus ABneed to send data at the rate of 16bit/second to be able to satisfy the datatransfer of two channel A and B5- bus AB we attempt to utilize the idle time slots of one channel for datatransfer of other channels by synthesizing a bus over which data transfer atconstant time
43. 43. 3- Constraints for bus generation: For implementation the designer can specify constraints such as: 1- Bus Width : Maximum/minimum bus width (pins, modules) 2- channel Average rate (minimum channel and maximum channel )(constraints for process communicating over the channel 3-channel peak rate: to ensure that transfer of single data item over the bus don’t take long time
44. 44. determine bus width toimplement group of channels.For each one time only one channel canThe data and control bus are disjoint.transfer data.
45. 45. Observation: 1.If bus width is greater than address and data bit width so data and address bits are sent simultaneously over the bus if opposite they sent separately. Note: *In last case address must be latched in the receiving process. *If bus width smaller than data bits so data sent on multiple interfaces.How we use this bus?₩ .Variables mapped to another module .₩. These mapped variables modeled by separate process.₩. Separate process send/receive variable values over channel in response to requests from process.
46. 46.  By using this algorithm we have to extract two cases :*Feasible implementation.*No constraints case .”Bus width corresponds to 1 to serial data transfer” Feasible implementation Each bus width have bus rate &channel average rate must be calculated.  bus rate greater than sum of channel average rate as below Bus Rate=AveRate(channel) CEBSelect one that has least cost.
47. 47. Min BW&MaxBW range of bus width. MinCost representAveRateSum:sum min.cost of the channel computed foraverage rates for all feasible specific value of implementatio variables n of the bus. CurrBW CurrBW:curr MinCostBWRe ent bus width present evaluated by buswidth for algorithm. min.cost
48. 48. Bus algorithm show 5 steps:1.Determine the buswidth to be examined . MinBW=1,MaxBW=max(Bits(channel))2.Compute bus rate corresponding to CurrBW. BusRate(B)=CurrBW/Delay(B)3.Deteminethe channel average rates.
49. 49. Now if BusRate>sum of average rates of all channels then we have a feasible implementation for the bus .so....go to next step.else go to step 24.Determine cost for CurrBW. Cost of bus=(squares of violations of each constraints [weighted by relative weights specified for them])5.Select the buswidth.To determine the least cost from many feasible implementation solutions.
50. 50. Note : Problem.......If there is more than one channel in the implementation these would progressively delay the process communicating over bus this situation when we have more channels have own very high average rate requirements are grouped to gather to have single busSo ........solution is split the group of channels to be implemented by more than one bus and use feasible implementation.
51. 51.  EVAL-R3 &CONV-R2 Processes of FLC access array variables trRu0 & trRu2 over communication channels ch1 & ch2 that merged to be implemented as a single bus. All execution times data transfer rates are expressed in terms of clocks
52. 52. Both channels access array variables which have 128 words (7 address bits)of 16 bits each.MinBW=1 and MaxBW=23CurrBW=18. For handshake rotocol,delay(b)=2 clocks[BusRate(B)=18/( 2)=9 bits/clock.] AveRate(ch1)=(128*23)/(515+(128*[28/18]*2)] =2.86 bits/clockAveRate(ch2)=(128*23)/[129+(128*[23/18]*2) =4.59 bits/clock
53. 53. BusRate(B)>AveRate(ch1)+AveRate(ch2) we have fessible solution for CurrBW=18.Cost =peakRateCost(ch2)^2=(10*(10-9))^2=100 If repeating the algorithm on other range for buswidth from[1-23]. For graph:1.This is the buswidth that is selected for implementing the bus consisting of channels ch1 and ch2.2.We note that the minimum value of the cost function is [0] which occurs at a buswidth of 20
54. 54. Bus generation algorithm implemented by SpecSyn system –level partitioner . Usage of bus generation algorithm for protocol generation*For selected buswidth VHDL receive/send procedures defining the data transfer over bus are generated for each channel*Accesses to variables in the processes are replaced by the appropriate send/receive procedure call .
55. 55. Application of bus generation algorithm Ethernet network processor. Bladder volume controller. Fuzzy logic controller. Now let is disscus fuzzy logic controller
56. 56. *FLC consists of two inputs*FLC sense the temperature and humidity in a room and evaluate four rules to control the operation of an air conditioning system .*system partitioning mapped processes & array variables that store FLC membership functions & fuzzy logic rules to different modules then creating several channels between modules .
57. 57.  1.Each bus width has protocol required for all channels in the bus. Performance estimator used to get execution time of processes. BW ExecutionExample” timeProcess (CONV-R2)has max execution time constraints of 2000 clocks so only bus width over 4 bits needed to implement bus .[back to figure 6]
58. 58.  This by specify suitable constraints and weighting we implement bus generation algorithm to 3 sets of constraints. [3 designs]
59. 59. Design A Min peak rate ch2 =10 bit/clock. Feasible bus implementations are those which have bus rate >sum of individual channel average rates Min cost function for bus width of 20 bits. Design B Min & max Bus width constraints with relative weight half peak rate constraint for ch2 specified. Min cost function occurs at bus width of 18
60. 60. Design C This design for implement both channel A & B using 16 bit bus. Both min & max bus width constraints specified to be 16 bits & very high relatively weights. It has least cost function of all feasible implementations.
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