Data flow super computing   valentina balas
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Data flow super computing   valentina balas Data flow super computing valentina balas Presentation Transcript

  • V. Milutinović, G. Rakocevic, S. Stojanović, and Z. Sustran University of Belgrade Oskar Mencer Imperial College, London Oliver Pell Maxeler Technologies, London and Palo Alto Michael Flynn Stanford University, Palo Alto Valentina E. Balas 1/52 Aurel Vlaicu University of Arad
  • For Big Data algorithms and for the same hardware price as before, achieving: a) speed-up, 20-200 b) monthly electricity bills, reduced 20 times c) size, 20 times smaller 2/52
  • Absolutely all results achieved with: a) all hardware produced in Europe, specifically UK b) all software generated by programmers of EU and WB 3/52
  • ControlFlow (MultiFlow and ManyFlow):  Top500 ranks using Linpack (Japanese K,…)DataFlow:  Coarse Grain (HEP) vs. Fine Grain (Maxeler) 4/52
  • Compiling below the machine code level brings speedups;also a smaller power, size, and cost.The price to pay:The machine is more difficult to program.Consequently:Ideal for WORM applications :)Examples using Maxeler:GeoPhysics (20-40), Banking (200-1000, with JP Morgan 20%), M&C (New York City), Datamining (Google), … 5/52
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  • tCPU = tGPU = tDF = NOPS * CDF * TclkDF +N * NOPS * CCPU*TclkCPU N * NOPS * CGPU*TclkGPU / (N – 1) * TclkDF / NDF/NcoresCPU NcoresGPU Assumptions: 1. Software includes enough parallelism to keep all cores busy 2. The only limiting factor is the number of cores. 11/52
  • Which way are the horsesDualCore? going? 12/52
  • Is it possible to use 2000 chicken instead of two horses? ? ==What is better, real and anecdotic? 13/52
  • 2 x 1000 chickens (CUDA and rCUDA) 14/52
  • D at aHow about 2 000 000ants? 15/52
  • Big Data Input Results Marmalade 16/52
  • Factor: 20 to 200 MultiCore/ManyCore Dataflow Machine Level Code Gate Transfer Level 17/52
  • Factor: 20 MultiCore/ManyCore Dataflow 18/52
  • Factor: 20 MultiCore/ManyCore DataFlow Data Processing Data Processing Process Control Process Control 19/52
  •  MultiCore:  Explain what to do, to the driver  Caches, instruction buffers, and predictors needed ManyCore:  Explain what to do, to many sub-drivers  Reduced caches and instruction buffers needed DataFlow:  Make a field of processing gates: 1C+2nJava+3Java  No caches, etc. (300 students/year: BGD, BCN, LjU, ICL,…) 20/52
  • MultiCore:  Business as usualManyCore:  More difficultDataFlow:  Much more difficult  Debugging both, application and configuration code 21/52
  •  MultiCore/ManyCore:  Several minutes DataFlow:  Several hours for the real hardware  Fortunately, only several minutes for the simulator  The simulator supports both the large JPMorgan machine as well as the smallest “University Support” machine Good news:  Tabula@2GHz 22/52
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  • MultiCore:  Horse stableManyCore:  Chicken houseDataFlow:  Ant hole 24/52
  • MultiCore:  HaystackManyCore:  CornbitsDataFlow:  Crumbs 25/52
  • Small Data: Toy Benchmarks (e.g., Linpack) 26/52
  • Medium Data(benchmarksfavorising NVidia,compared to Intel,…) 27/52
  • Big Data 28/52
  •  Revisiting the Top 500 SuperComputer Benchmarks  Our paper in Communications of the ACM Revisiting all major Big Data DM algorithms  Massive static parallelism at low clock frequencies Concurrency and communication  Concurrency between millions of tiny cores difficult, “jitter” between cores will harm performance at synchronization points Reliability and fault tolerance  10-100x fewer nodes, failures much less often Memory bandwidth and FLOP/byte ratio  Optimize data choreography, data movement, and the algorithmic computation 29/52
  • Maxeler Hardware CPUs plus DFEs DFEs shared over Infiniband Low latency connectivityIntel Xeon CPU cores and up to Up to 8 DFEs with 384GB of Intel Xeon CPUs and 1-2 DFEs 4 DFEs with 192GB of RAM RAM and dynamic allocation with up to six 10Gbit Ethernet of DFEs to CPU servers connections MaxWorkstation MaxCloud Desktop development system On-demand scalable accelerated compute resource, hosted in London30/52
  • Major Classes of Algorithms, from the Computational Perspective 1. Coarse grained, stateful: Business – CPU requires DFE for minutes or hours 1. Fine grained, transactional with shared database: DM – CPU utilizes DFE for ms to s – Many short computations, accessing common database data 1. Fine grained, stateless transactional: Science (FF) – CPU requires DFE for ms to s – Many short computations31/52
  • Coarse Grained: Modeling 80 • Long runtime, but: 70 Timesteps (thousand) Domain points (billion) 60 • Memory requirements 50 Total computed points (trillion) 40 change dramatically based 30 on modelled frequency 20 10 • Number of DFEs allocated 0 0 10 20 30 40 50 60 70 80 Peak Frequency (Hz) to a CPU process can be 2,000 easily varied to increase 1,800 1,600 15Hz peak frequency 30Hz peak frequency available memory 1,400 1,200 45Hz peak frequency 70Hz peak frequency • Streaming compression 1,000 800 600 • Boundary data exchanged 400 U o n u q P C e a E v c s r t l i 200 over chassis MaxRing 0 1 4 Number of MAX2 cards 832/52
  • Fine Grained, Shared Data: Monitoring • DFE DRAM contains the database to be searched • CPUs issue transactions find(x, db) • Complex search function – Text search against documents – Shortest distance to coordinate (multi-dimensional) – Smith Waterman sequence alignment for genomes • Any CPU runs on any DFE that has been loaded with the database – MaxelerOS may add or remove DFEs from the processing group to balance system demands – New DFEs must be loaded with the search DB before use33/52
  • Fine Grained, Stateless: The BSOP Control • Analyse > 1,000,000 scenarios • Many CPU processes run on many DFEs – Each transaction executes on any DFE in the assigned group atomically • ~50x MPC-X vs. multi-core x86 node CPU CPU DFE CPU CPU Market and DFE DFE Loop over instruments Loop over instruments Loop over instruments Loop over instruments CPU instruments DFE DFE Loop over instruments Loop over instruments Loop over instruments Loop over instruments Loop over instruments Loop over instruments Random number Random number data Random number Random number Random number Random number generator and Random numberand generator Random number generator and Random numberand generator Random number generator and generator and sampling of and Tail Tail generator underliers sampling of of underliers sampling underliers generator and Tail Tail sampling of of underliers sampling underliers generator and generator and Tail Tail sampling of of underliers sampling underliers Tail analysis Tail analysis sampling of of underliers sampling underliers sampling of underliers Tail analysis Tail analysis analysis analysis analysis onCPU CPU analysis analysis CPU onCPU onCPU analysis onCPU onCPU on on CPU on Price instruments Price instruments Price instruments Price instruments on CPU on CPU Price instruments Priceusing Black instruments using Black Price instruments Priceusing Black instruments using Black Price instruments Priceusing Scholes instruments Black using Black Scholes using Scholes Black using Black Scholes using Scholes Black using Black Scholes Instrument Scholes Scholes Scholes Scholes values34/52
  • Selected Examples35/52
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  • The CRS Results  Performance of one MAX2 card vs. 1 CPU core  Land case (8 params), speedup of 230x  Marine case (6 params), speedup of 190x CPU Coherency MAX2 Coherency37/52
  • Seismic Imaging • Running on MaxNode servers - 8 parallel compute pipelines per chip - 150MHz => low power consumption! - 30x faster than microprocessors An Implementation of the Acoustic Wave Equation on FPGAs T. Nemeth†, J. Stefani†, W. Liu†, R. Dimond‡, O. Pell‡, R.Ergas§ † Chevron, ‡Maxeler, §Formerly Chevron, SEG 200838/52
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  • P. Marchetti et al, 2010 Trace Stacking: Speed-up 217 • DM for Monitoring and Control in Seismic processing • Velocity independent / data driven method to obtain a stack of traces, based on 8 parameters – Search for every sample of each output trace 2  2 T  2t0 Tt 2 hyp =  t0 + w m  +  v0  v0 ( m H zy K N H T m + h T H zy K NIP H T h zy zy )   2 parameters ( emergence angle & azimuth ) 3 Normal Wave front parameters ( KN,11; KN,12 ; KN22 ) 3 NIP Wave front parameters ( KNip,11; KNip,12 ; KNip22 )41/52
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  • Conclusion: Nota Bene This is about algorithmic changes, to maximize the algorithm to architecture match: Data choreography, process modifications, and decision precision. The winning paradigm of Big Data ExaScale?45/52
  • The TriPeak Siena + BSC + Imperial College + Maxeler + Belgrade 46/52 46/8
  • The TriPeakMontBlanc = A ManyCore (NVidia) + a MultiCore (ARM)Maxeler = A FineGrain DataFlow (FPGA)How about a happy marriage?MontBlanc (ompSS) and Maxeler (an accelerator)In each happy marriage,it is known who does what :)The Big Data DM algorithms:What part goes to MontBlanc and what to Maxeler? 47/52 47/8
  • Core of the Symbiotic SuccessAn intelligent DM algorithmic scheduler,partially implemented for compile time,and partially for run time.At compile time:Checking what part of code fits where(MontBlanc or Maxeler): LoC 1M vs 2K vs 20KAt run time:Rechecking the compile time decision,based on the current data values. 48/52 48/8
  • Maxeler: Teaching (Google: profvm) VLSI, PowerPoints, Maxeler:TEACHING,Maxeler Veljko Explanations, August 2012Maxeler Veljko Anegdotic,Maxeler Oskar Talk, August 2012Maxeler Forbes ArticleFlyer by JP MorganFlyer by Maxeler HPCTutorial Slides by Sasha and Veljko: Practice (Current Update)Paper, unconditionally accepted for Advances in Computers by ElsevierPaper, unconditionally accepted for Communications of the ACMTutorial Slides by Oskar: Theory (7 parts)Slides by Jacob, New YorkSlides by Jacob, AlabamaSlides by Sasha: Practice (Current Update)Maxeler in MeteorologyMaxeler in MathematicsExamples generated in Belgrade and WorldwideTHE COURSE ALSO INCLUDES DARPA METHODOLOGY FOR MICROPROCESSOR DESIGN, with an example 49/52 49/8
  • Maxeler: Research (Google: good method)Structure of a Typical Research Paper: Scenario #1[Comparison of Platforms for One Algorithm]Curve A: MultiCore of approximately the same PurchasePriceCurve B: ManyCore of approximately the same PurchasePriceCurve C: Maxeler after a direct algorithm migrationCurve D: Maxeler after algorithmic improvementsCurve E: Maxeler after data choreographyCurve F: Maxeler after precision modificationsStructure of a Typical Research Paper: Scenario #2[Ranking of Algorithms for One Application]CurveSet A: Comparison of Algorithms on a MultiCoreCurveSet B: Comparison of Algorithms on a ManyCoreCurveSet C: Comparison on Maxeler, after a direct algorithm migrationCurveSet D: Comparison on Maxeler, after algorithmic improvementsCurveSet E: Comparison on Maxeler, after data choreographyCurveSet F: Comparison on Maxeler, after precision modifications 50/52 50/8
  • Maxeler: Topics (Google: HiPeac Berlin) SRB (TR): KG: Blood Flow NS: Combinatorial Math BG1: MiSANU Math BG2: Meteos Meteorology BG3: Physics (Gross Pitaevskii 3D real) BG4: Physics (Gross Pitaevskii 3D imaginary) (reusability with MPI/OpenMP vs effort to accelerate) FP7 (Call 11): University of Siena, Italy, ICL, UK, BSC, Spain, QPLAN, Greece, ETF, Serbia, IJS, Slovenia, … 51/52 51/8
  • Q&Abalas@drbalas.ro 52/52 52/8