Mini Project  ROM-Based Sine Wave Generator   Introductory Lecture   BSc Hon. Multimedia Technology.  Mini Projects. <ul><...
Contents <ul><ul><li>Outline </li></ul></ul><ul><ul><li>Sequential Logic </li></ul></ul><ul><ul><li>D Flip-Flop </li></ul>...
Outline <ul><li>Sequential design using VHDL </li></ul><ul><ul><li>Flip Flops </li></ul></ul><ul><ul><li>Counters </li></u...
Sequential Logic <ul><li>Digital electronics is classified into: </li></ul><ul><ul><li>Combinatorial logic </li></ul></ul>...
Sequential Logic <ul><li>Two types of Sequential circuits: </li></ul><ul><ul><li>Synchronous sequential circuits </li></ul...
D Flip-FLOP Timing diagram Truth table
D Flip-FLOP Detecting Rising Clock Edge: (CLK='1' and CLK 'event )  or  rising_edge (CLK) Detecting Falling Clock Edge?
D Flip-FLOP with Asynchronous RESET Timing diagram
D Flip-FLOP with Asynchronous RESET
D Flip-FLOP with Synchronous RESET Timing diagram Exercise 1
D Flip-FLOP with Synchronous RESET
2-bit Counter with Asynchronous RESET Timing diagram Exercise 2
2-bit Counter with Asynchronous RESET
Memories <ul><li>Array types </li></ul><ul><li>Writing to an array </li></ul><ul><li>Signed and unsigned types </li></ul><...
Array Types <ul><li>An array is a collection of elements of the same type.  The type of the elements can be any kind of ty...
Writing to an array <ul><li>Write a value to a single array location </li></ul><ul><li>Fill the entire array with the same...
SIGNED and UNSIGNED types <ul><li>The package  NUMERIC_STD  exists for the purpose of doing arithmetic on vectors </li></u...
Array type conversion <ul><li>unsigned, signed and std_logic_vector are known as  closely related  types in VHDL </li></ul...
Conversion functions <ul><li>A function can be written to convert a value from any data type to a different data type </li...
Numeric_std and std_logic_vector <ul><li>In order to do arithmetic operations on values of the type std_logic_vector the v...
Conversions- Summary
Resizing <ul><li>Numeric_std package contains resizing functions </li></ul><ul><li>They are used for resizing a signed/uns...
Resizing - Example
Modelling memories - RAM
Modelling memories - RAM
Modelling memories - ROM
Modelling memories - ROM
<ul><li>Wait statement </li></ul><ul><li>After Statement  </li></ul><ul><li>Assertion statement </li></ul><ul><li>Writing ...
WAIT Statement  <ul><li>The wait statement explicitly specifies the conditions under which a process may resume execution ...
WAIT Statement  <ul><li>Causes suspension of the process for a period of time given by the evaluation of  time expression ...
WAIT Statement - Example  <ul><li>A process that generates a clock with a 10 ns period  </li></ul>
Creating Signal Waveforms Using After Clause <ul><li>It is possible to assign multiple values to a signal, each with a dif...
Assertion Statement <ul><li>A statement that checks that a specified condition is true and reports an error if it is not  ...
Assertion Statement Example <ul><li>When the values of the signals S and R are equal to ’1’, the message is displayed and ...
VHDL Test Bench <ul><li>A test bench is a specification in VHDL that plays the role of a complete simulation environment f...
VHDL Test Bench <ul><li>The UUT is instantiated as a component of the test bench </li></ul><ul><li>The architecture of the...
A Test Bench Template
A Test Bench Example Truth table VHDL code to describe the D FF
A Test Bench Example VHDL test bench to simulate the D FF
A Test Bench Example
A Test Bench Example FALSE
A Test Bench Exercise Write the process part of the test bench that generates the following inputs:
Solution
This resource was created by the University of Hertfordshire and released as an open educational resource through the Open...
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Mini Project- ROM Based Sine Wave Generator

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The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.

The objectives of this module are to demonstrate, within an embedded development environment:

• Processor – to – processor communication
• Multiple processors to perform one computation task using parallel processing

This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

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  • In other words, sequential logic has storage ( memory )
  • Std_logic_vector an unconstrained array
  • Std_logic_vector an unconstrained array
  • Use Ieee.numeric_std.all
  • C &lt;= std_logic_vector (B)
  • Integer -2**31 to +2**31 - 1
  • Integer -2**31 to +2**31 - 1
  • Integer -2**31 to +2**31 - 1
  • suspends process/subprogram execution until a signal changes, a condition becomes true, or a defined time period has elapsed. Combinations of these can also be used.
  • See page 77 book
  • See page 77 book
  • All the SAS that we have seen so far, we have always assigned a single value to a signal Any arbitrary waveform can be easily created using a SAS The delay must appear in increasing order
  • When an assertion violation occurs, the report is issued and displayed on the screen. The severity level defines the degree to which the violation of the assertion affects operation of the process Note: provides information about the progress of the simulation
  • The message is displayed when the condition is NOT met
  • A test bench is a specification in VHDL that plays the role of a complete simulation environment for the analysed system (Unit Under Test, UUT). The test bench contains both the UUT as well as stimuli for the simulation. The UUT is instantiated as a component of the test bench and the architecture of the test bench specifies stimuli for the UUT’s ports.
  • Most simulators provide commands to apply stimulus to the input ports of a design entity. By tracing and viewing the resulting values of the signals on the output ports, we can determine whether the model is operating correctly. In VHDL, the model (test bench) generates sequences of inputs and reads the outputs of the module being tested.
  • -- Declare any libraries that will be needed -- Declare the packages that will be use in these libraries
  • Mini Project- ROM Based Sine Wave Generator

    1. 1. Mini Project ROM-Based Sine Wave Generator Introductory Lecture BSc Hon. Multimedia Technology. Mini Projects. <ul><li>Author: University of Hertfordshire </li></ul><ul><li>Date created: </li></ul><ul><li>Date revised: 2009 </li></ul><ul><li>Abstract </li></ul><ul><li>The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. </li></ul><ul><li>The objectives of this module are to demonstrate, within an embedded development environment: </li></ul><ul><ul><li>Processor – to – processor communication </li></ul></ul><ul><ul><li>Multiple processors to perform one computation task using parallel processing </li></ul></ul><ul><li>This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team. </li></ul>© University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License .
    2. 2. Contents <ul><ul><li>Outline </li></ul></ul><ul><ul><li>Sequential Logic </li></ul></ul><ul><ul><li>D Flip-Flop </li></ul></ul><ul><ul><li>D Flip-FLOP with Asynchronous RESET </li></ul></ul><ul><ul><li>D Flip-FLOP with Synchronous RESET </li></ul></ul><ul><ul><li>2-bit Counter with Asynchronous RESET </li></ul></ul><ul><ul><li>Memories </li></ul></ul><ul><ul><li>Array Types </li></ul></ul><ul><ul><li>Array type conversion </li></ul></ul><ul><ul><li>Conversion Summary </li></ul></ul><ul><ul><li>Resizing </li></ul></ul><ul><ul><li>Modelling memories – RAM </li></ul></ul><ul><ul><li>Modelling memories – ROM </li></ul></ul><ul><ul><li>VHDL Test Benches </li></ul></ul><ul><ul><li>WAIT Statement </li></ul></ul><ul><ul><li>Assertion Statement </li></ul></ul><ul><ul><li>A Test Bench Template </li></ul></ul><ul><ul><li>A Test Bench Example </li></ul></ul><ul><ul><li>Credits </li></ul></ul><ul><li>In addition to the resources found below there are supporting documents which should be used in combination with this resource. Please see: </li></ul><ul><li>Mini Projects - Introductory presentation. </li></ul><ul><li>Mini Projects - E-Log. </li></ul><ul><li>Mini Projects - Staff & Student Guide. </li></ul><ul><li>Mini Projects - Standard Grading Criteria. </li></ul><ul><li>Mini Projects - Reflection. </li></ul><ul><li>You will also need the ‘Mini Project- ROM-Based Sine Wave Generator’ text document. </li></ul>
    3. 3. Outline <ul><li>Sequential design using VHDL </li></ul><ul><ul><li>Flip Flops </li></ul></ul><ul><ul><li>Counters </li></ul></ul><ul><ul><li>Memories </li></ul></ul><ul><ul><ul><li>RAMs </li></ul></ul></ul><ul><ul><ul><li>ROMs </li></ul></ul></ul>
    4. 4. Sequential Logic <ul><li>Digital electronics is classified into: </li></ul><ul><ul><li>Combinatorial logic </li></ul></ul><ul><ul><li>Sequential logic </li></ul></ul><ul><li>Combinatorial logic : output is a function of, and only of, the present input </li></ul><ul><li>Sequential logic : output depends not only on the present input but also on the history of the input </li></ul><ul><ul><li>It has storage ( memory ) </li></ul></ul>
    5. 5. Sequential Logic <ul><li>Two types of Sequential circuits: </li></ul><ul><ul><li>Synchronous sequential circuits </li></ul></ul><ul><ul><li>Asynchronous sequential circuits </li></ul></ul><ul><li>Synchronous: logic responds to changes of input signals according to the state of a clock signal </li></ul><ul><li>Asynchronous: logic responds to the external system almost instantly </li></ul>
    6. 6. D Flip-FLOP Timing diagram Truth table
    7. 7. D Flip-FLOP Detecting Rising Clock Edge: (CLK='1' and CLK 'event ) or rising_edge (CLK) Detecting Falling Clock Edge?
    8. 8. D Flip-FLOP with Asynchronous RESET Timing diagram
    9. 9. D Flip-FLOP with Asynchronous RESET
    10. 10. D Flip-FLOP with Synchronous RESET Timing diagram Exercise 1
    11. 11. D Flip-FLOP with Synchronous RESET
    12. 12. 2-bit Counter with Asynchronous RESET Timing diagram Exercise 2
    13. 13. 2-bit Counter with Asynchronous RESET
    14. 14. Memories <ul><li>Array types </li></ul><ul><li>Writing to an array </li></ul><ul><li>Signed and unsigned types </li></ul><ul><li>Array type conversion </li></ul><ul><li>Conversion functions </li></ul><ul><li>Resizing functions </li></ul><ul><li>Modelling memories </li></ul><ul><ul><li>RAMs </li></ul></ul><ul><ul><li>ROMs </li></ul></ul>
    15. 15. Array Types <ul><li>An array is a collection of elements of the same type. The type of the elements can be any kind of type including another array type </li></ul><ul><li>Constrained array declaration : declares a new array type with a fixed number of elements </li></ul><ul><li>Unconstrained array declaration : the number of elements is not specified </li></ul>
    16. 16. Writing to an array <ul><li>Write a value to a single array location </li></ul><ul><li>Fill the entire array with the same value </li></ul>
    17. 17. SIGNED and UNSIGNED types <ul><li>The package NUMERIC_STD exists for the purpose of doing arithmetic on vectors </li></ul><ul><li>It contains two new data types: unsigned and signed </li></ul><ul><ul><li>They represent unsigned and two’s complement binary numbers </li></ul></ul><ul><ul><li>They are vectors, and so are very similar to std_logic_vector in use </li></ul></ul>
    18. 18. Array type conversion <ul><li>unsigned, signed and std_logic_vector are known as closely related types in VHDL </li></ul><ul><ul><li>They are all arrays of the type STD_LOGIC </li></ul></ul><ul><li>X <= type_name (Y) </li></ul>
    19. 19. Conversion functions <ul><li>A function can be written to convert a value from any data type to a different data type </li></ul><ul><li>VHDL does NOT provide any predefined conversion functions </li></ul><ul><ul><li>Ready written conversion functions are available in the packages distributed by synthesis tool vendors and other specialised VHDL utility vendors </li></ul></ul>
    20. 20. Numeric_std and std_logic_vector <ul><li>In order to do arithmetic operations on values of the type std_logic_vector the values must first be converted to one of the types unsigned or signed </li></ul><ul><li>Using numeric_std, conversions between the types std_logic_vector and integer have to be in two steps </li></ul>
    21. 21. Conversions- Summary
    22. 22. Resizing <ul><li>Numeric_std package contains resizing functions </li></ul><ul><li>They are used for resizing a signed/unsigned value </li></ul>
    23. 23. Resizing - Example
    24. 24. Modelling memories - RAM
    25. 25. Modelling memories - RAM
    26. 26. Modelling memories - ROM
    27. 27. Modelling memories - ROM
    28. 28. <ul><li>Wait statement </li></ul><ul><li>After Statement </li></ul><ul><li>Assertion statement </li></ul><ul><li>Writing a VHDL test bench </li></ul><ul><ul><li>Test Bench template </li></ul></ul><ul><ul><li>Example </li></ul></ul>VHDL Test Benches
    29. 29. WAIT Statement <ul><li>The wait statement explicitly specifies the conditions under which a process may resume execution after being suspended </li></ul>
    30. 30. WAIT Statement <ul><li>Causes suspension of the process for a period of time given by the evaluation of time expression </li></ul><ul><li>Causes a process to suspend execution until an events occurs on one or more signals in a group of signals </li></ul><ul><li>The third form can specify a <condition> that evaluates to a Boolean value, TRUE or FALSE </li></ul>
    31. 31. WAIT Statement - Example <ul><li>A process that generates a clock with a 10 ns period </li></ul>
    32. 32. Creating Signal Waveforms Using After Clause <ul><li>It is possible to assign multiple values to a signal, each with a different delay value </li></ul>Example Must appear in increasing order
    33. 33. Assertion Statement <ul><li>A statement that checks that a specified condition is true and reports an error if it is not </li></ul>Must evaluate to a Boolean value (true or false) If false , it is said that an assertion violation occurred A message to be reported when assertion violation occurred Predefined severity names are: NOTE: used to pass information messages from simulator WARNING: used in unusual situation in which the simulation can be continued ERROR: used when assertion violation makes continuation of the simulation not feasible FAILURE: used when the assertion violation is a fatal error and the simulation must be stopped
    34. 34. Assertion Statement Example <ul><li>When the values of the signals S and R are equal to ’1’, the message is displayed and the simulation is stopped because the severity is set to error </li></ul>
    35. 35. VHDL Test Bench <ul><li>A test bench is a specification in VHDL that plays the role of a complete simulation environment for the analysed Design </li></ul><ul><ul><li>Analysed design: Unit Under Test (UUT) </li></ul></ul><ul><li>A test bench contains: </li></ul><ul><ul><li>The UUT </li></ul></ul><ul><ul><li>Stimuli for the simulation </li></ul></ul>
    36. 36. VHDL Test Bench <ul><li>The UUT is instantiated as a component of the test bench </li></ul><ul><li>The architecture of the test bench specifies stimuli for the UUT’s ports </li></ul>
    37. 37. A Test Bench Template
    38. 38. A Test Bench Example Truth table VHDL code to describe the D FF
    39. 39. A Test Bench Example VHDL test bench to simulate the D FF
    40. 40. A Test Bench Example
    41. 41. A Test Bench Example FALSE
    42. 42. A Test Bench Exercise Write the process part of the test bench that generates the following inputs:
    43. 43. Solution
    44. 44. This resource was created by the University of Hertfordshire and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. Where screenshots are taken from Altium Designer 6, and appear courtesy of Premier EDA Solutions Ltd. © University of Hertfordshire 2009                  This work is licensed under a Creative Commons Attribution 2.0 License . The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written permission. The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence.  All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.

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