CICC 2001 - Reducing Multiple Design Flow Support Requirements with OLA

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This presentation demonstrates the advantages of employing Open Library Architecture (OLA) libraries to reduce support for multiple design flows.

This presentation demonstrates the advantages of employing Open Library Architecture (OLA) libraries to reduce support for multiple design flows.

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  • 1. Philips Semiconductors CICC 2001 - Wednesday May 9th ALF/OLA Panel Discussion PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 1 OLA: A New Standard in the EDA World or another car wreck on the side of the EDA road(map) 2001 Custom Integrated Circuits Conference
  • 2. Philips Semiconductors Multiple Design Flows: Reducing Support Requirements with OLA PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 2 Timothy J. Ehrler, Senior Principal ASIC Technical Programs Manager Design Technology Group Philips Semiconductors tim.ehrler@philips.com 2001 Custom Integrated Circuits Conference
  • 3. Philips Semiconductors Current Plight of the ASIC Vendor • Must support many tools within a design flow – many tools within the sub-flows (synthesis, etc.) – multiple tools => multiple file formats PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 3 • Must support many design flows – flows are driven by design applications • ASIC high performance • mixed signal, analog • low power (wireless) • RF design – different design flows require different sets of tools 2001 Custom Integrated Circuits Conference
  • 4. Philips Semiconductors Current Plight of the ASIC Vendor (2) • Must support many libraries – multiple technologies and processes – multiple sets of libraries • core, I/O, memories • high- and low- VT PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 4 • protected and unprotected • complex cores (embedded processors, DSP, etc.) TX RX Tunnel • specialty, IP DTL Conc Tunnel RX TX • Information comes from a variety of sources – multiple characterization tools with different file formats – internal general/specific library packages – internal/external (3rd party) memories, complex cores, IP 2001 Custom Integrated Circuits Conference
  • 5. Philips Semiconductors Impact on Design Flow Support • Many formats required to enable supported tools – multiple sources for characterization/view information – not necessarily 1st generation views from available information – inconsistent interpretation/view by tools from same vendor PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 5 • multiple library “flavors” required by different vendor tools • Qualification process for each tool/library combination – verification of tool/library interoperability – consideration of impact on subsequent tools in flow – preliminary and tactical libraries may not be fully qualified • resource availability may restrict/reduce verification 2001 Custom Integrated Circuits Conference
  • 6. Philips Semiconductors Impact on Design Flow Support (2) • Support and qualification requirements ever increasing – new technologies and processes constantly being introduced – new tools, or additional capabilities therein, always added PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 6 – additional design flows may be required as applications dictate 2001 Custom Integrated Circuits Conference
  • 7. Philips Semiconductors Typical Design Flow SPEC SDB Contents: RTL Simulation Contents: Architectural Analysis Hierarchy planning Behavioral RTL Partitioning & Automatic flatten for P&R Bus interfaces IP Software code development Ref Libs Floorplanning pre-route P/G, clock nets Design RSP platform (Velocity™, Nexperia™) Area estimation Feasibility: Performance, Area, Power, Clocking, Test management LDB RTL Description Contents: Block level synthesis Contents: PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 7 Create top level design (CPU, DSP, Ref Libs Layout: Cell and Block P&R Library analog, memory, IP templates (HDLi™), Cell & Block Functional Design Timing driven extensions I/O, schematics) Models DFT (scan insertion, MBIST, JTAG, padring) Floorplanning LDB Structural Netlist Contents: Layout: Contents: Insert core & pad fillers Delay Calculation Ref Libs Chip Assembly Static Timing Analysis Design Finishing Symbolic verification Library Logic & Timing Gate-level Simulation Bond diagram Models Verification Power Estimation Netlist Screener Verification of specification LDB GDS-II Verification Lib Rules, Timing, Package Contents: DRC, LVS, Layout Test Program To Factory Finish Plots, Extraction, Circuit Generation Simulation, Back-annotation and Mask Making & Timing Analysis multiple & proprietary file formats 2001 Custom Integrated Circuits Conference
  • 8. Philips Semiconductors OLA Support of Design Flow Synthesis Static Timing PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 8 OLA Design for Test Compliant Library OLA Floorplanning (API) includes Timing and Power Calculation Place & Route Routines Semiconductor Sign-Off 2001 Custom Integrated Circuits Conference
  • 9. Philips Semiconductors OLA Impact on Design Flow Support Design Process Tools Standard / Total OLA Total Format Proprietary Formats Replaceable/ Formats Reduction Formats Deleteable RTL Development/Analysis 5 3/0 3 2/0 2 33% Design Synthesis 7 4/6 10 4/1 6 40% Logic/Timing Verification 17 5/11 16 6/5 6 63% Partitioning & Floor Planning 11 3/9 12 5/0 8 33% Layout & Chip Finishing 21 4/15 19 6/2 12 37% PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 9 • Major Reduction in Supported File Formats – corresponding reduction of generation/verification requirements • eliminate generation/translation tool requirements • reduce generation & verification resources (h/w, personnel, time) • Even Greater Savings for Multiple Libraries – relative to OLA Replaceable/Deleteable numbers • 16 libraries per technology ~= 16-fold reduction • dependent on tool set choices and interfaces 2001 Custom Integrated Circuits Conference
  • 10. Philips Semiconductors Multiple Design Flows Flow A Flow B Flow C RTL Development/Analysis RTL Development/Analysis • Define Methodologies Technology Packages + Libraries + IP Technology Packages + Libraries + IP Sub Flow Sub-Flow Sub-Flow Sub Flow Sub-Flow Sub-Flow – design requirement driven Design Synthesis Design Synthesis – drives design processes Design Methodologies Design Methodologies PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 10 Sub-Flow Sub-Flow Sub-Flow Sub-Flow • Define Specific Flows Logic/Timing Verification Logic/Timing Verification – design application driven Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow – drives sub-flow tool types Partitioning & Floor Planning Partitioning & Floor Planning Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow • Determine Specific Tools Layout & Chip Finishing Layout & Chip Finishing – drives library requirements Sub-Flow Sub-Flow Sub-Flow Sub-Flow 2001 Custom Integrated Circuits Conference
  • 11. Philips Semiconductors OLA Impact on Multiple Design Flows • Significant Reduction in Supported File Formats – proportional generation/verification savings • impacted by number of libraries • dependent on sub-flow tool choices • Easier Introduction of Subsequent Flows & Tools PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 11 – reduced/eliminated generation/verification requirements • great impact on tool evaluation requirements and resources • Faster Introduction of Additional Libraries – efforts focused primarily on library validation, not tools • eliminates many flow-dependent verification processes • Reduced Impact on Previously Released IP – eliminates IP package updates for additional flows & tools – ensures stability of released IP during design development 2001 Custom Integrated Circuits Conference
  • 12. Philips Semiconductors Summary & Conclusion • OLA allows the ASIC vendor to be more productive – reduced number of supported file formats – reduction in qualification time – allows easier and faster introduction of new technologies – encourages 3rd party IP generation PS - OLA Impact on Multiple Flow Support - DTG/ADF - TJE - 12 • OLA provides EDA vendor easier entry into design flows – OLA compliant tools don’t require exhaustive library verification – ASIC vendor doesn’t need to generate/qualify “another format” – consistent “behavior” of library eliminates convergence issues • The OLA standard is a WIN-WIN for ASIC and EDA vendors 2001 Custom Integrated Circuits Conference