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By Chong Wei Ting Tuanku Syed Sirajuddin Polytechnic

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- 1. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 1ELECTRICAL ENGINEERING DEPARTMENTEE603-CMOS INTEGRATED CIRCUIT DESIGNLAB REPORT 6DESIGNING HALF ADDER CIRCUITNo Registration No. Name1. 18DTK10F1036 CHONG WEI TING2. 18DTK10F1034 ADLAN BIN ABDULLAHCLASS : DTK 6BLECTURER : EN. MUHAMAD REDUAN BIN ABU BAKARDATE SUBMITTED : 8thARPIL 2013(Date submitted is one week after date lab)TUANKU SYEDSIRAJUDDINPOLYTECHNICMARKSLab Work :Lab Report:Total :
- 2. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 2LAB 6 : DESIGNING HALF ADDER CIRCUITAim: Designing half adder circuit using L-edit software.Objective:After students had done this laboratory, then students should be able to:1) Introduce schematic circuit, logic symbols and truth table of half adder.2) Design half adder circuit using L-edit..Apparatus: PC-set & L-edit student V 7.12 software.Half adder is a combinational arithmetic circuit that adds two numbers and produces asum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S)is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it isclear that a half adder circuit can be easily constructed using one X-OR gate and oneAND gate. Half adder is the simplest of all adder circuit, but it has a majordisadvantage. The half adder can add only two input bits (A and B) and has nothing todo with the carry if there is any in the input. So if the input to a half adder have a carry,then it will be neglected it and adds only the A and B bits. That means the binaryaddition process is not complete and that’s why it is called a half adder. The truth table,schematic representation and XOR//AND realization of a half adder are shown in thefigure below.INTRODUCTION
- 3. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 3Schematic symbol and truth table of exclusive OR (XOR) gate.(5 mark)Explanation of 1-bit half-adder circuit operation. (10mark)The basic 1-bit half-adder circuits. The sum bit is calculated with XOR gates, while theAND gates are used to check whether two (or more) inputs are 1, which implies that thecarry out bit must be set.The half adder adds two single binary digits A and B. It has twooutputs, sum (S) and carry (C). The carry signal represents an overflow into the nextdigit of a multi-digit addition. The value of the sum is 2C + S. The simplest half-adderdesign, pictured on the right, incorporates an XOR gate for S and an AND gate for C. Withthe addition of an OR gate to combine their carry outputs, two half adders can becombined to make a full adder.These are the least possible single-bit combinations. Butthe result for 1+1 is 10. Though this problem can be solved with the help of an EXORGate, if you do care about the output, the sum result must be re-written as a 2-bitoutput.Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out. From theequation it is clear that this 1-bit adder can be easily implemented with the help ofEXOR Gate for the output ‘SUM’ and an AND Gate for the carry.
- 4. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 41. DESIGN Individual xor GATESa) Created a new file in L-edit, and saved the file as Half_adder_chong.tdb.b) Go to cell and then rename cell0 as XOR_gate.LAB WORKACTIVITY
- 5. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 5c) In cell ‘XOR gate’, drawn the layout of XOR gate that according to XOR gatestick diagram in Appendix and then label its.d) Selected ToolDRC, to ensure that the design does not violating any designrules.
- 6. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 62. DESIGN Individual AND GATESa) Open a new cell and renamed it as ‘AND gate’.b) In cell ‘AND gate’, drawn the layout of 2-input AND gate thataccording to ANDgate stick diagram in Appendix and label it.
- 7. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 7c) Selected ToolDRC, to ensure that the design does not violating any designrules.3. DESIGN half adder.a) Open a new cell and renamed it as ‘half adder’.
- 8. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 8b) Go to cell, and then Instanced the XOR gate layout and AND gate layout in thisnew cell and made connection of these two layouts.c) Selected ToolDRC, to ensure that the design does not violating any designrules.
- 9. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 9Area: 7.75µm X 21.25µm=164.688 (denote 1lamda=0.125micron)RESULT OF HALFADDER
- 10. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 10This lab work will consider the complete half adder layout that based combination ofXOR gate and ANDis presented, which after completing the lab phase, we will be ableto design an individual 2-input logic gates which is AND gate and XOR gate based ongiven specification design rule. We had to combine these two gate together to form thehalf adder layout.Initially the design of XORand ANDlayout, we able to recognize schematic circuit, logicsymbols and truth table of XOR gates and AND gate.In half adder lab, we canhad todesign circuits that are capable of performing simple addition with the help of logic gates.APPENDIXCONCLUSION
- 11. [HALF ADDER DESIGN] April 8, 2013DECEMBER 2012 SESSION Page 111 77 6 68 1010 7 9VDDGNDA BA B4 2 3 5FExclusive-OR (XOR) Stick Diagram2-input AND gate Stick DiagramGNDF=A.BA BSSD D SVDDSD SD2-input NAND gate InverterinputVDDGNDF = A.B

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