bulk ieee 2014-15 projects list for VLSI


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provides bulk ieee projects to its regular clients and satisfies all their requirements on time, Also it provides 24/7 supports to all its clients in delivering the resources which is including source code delavery,Documents delivery,Algorithms delivery etc...,Technos Inc is also having around 100 clinets throughout India and across the World.
is an organization that provides software, Embedded, VLSI development and customizations to meet your company's industry specific needs. We consistently deliver quality solutions to our clients who are located worldwide.

As a fast growing company we focus on the complete life cycle of delivering quality software and Hardware from requirement gathering to implementation and maintenance. Technos Inc is empowered by a team of software professionals with rich experience and cutting edge technology skills in managing successful software projects.

The increasing pressure from global competition has forced software companies to look for the ways to reduce the Time-to-Market for their products, and to offer value added services at lower cost with improved quality. Software Product Development is confronting exactly the same concerns and hence it has no longer remained an option but has become the need of time for the businesses to respond to dynamic market forces.

We are mature software engineers in Chennai. Our two development centers in Pondicherry, Bagalore along with a backup site in Chennai provide our clients with high quality software development services. We product high quality software in Oracle, Java, Dot net and Embedded systems.

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bulk ieee 2014-15 projects list for VLSI

  1. 1. TECHNOS INC VLSI TITLES CHACKOTOWERS, ANNA NAGARMAIN ROAD,ANNA NAGAR,(NEXTTOSRI ANNAIXEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com VLSI TITLES 1. High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic 2. Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions 3. Area-Delay Efficient Binary Adders in QCA 4. Area–Delay–Power Efficient Carry-Select Adder 5. Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells 6. Simplifying clock gating logic by matching Factored forms 7. Data encoding techniques for reducing energy Consumption in network-on-chip 8. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation- Delay 9. Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults 10. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} 11. Efficient Integer DCT Architectures for HEVC 12. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation 13. Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata 14. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations 15. Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes 16. Multifunction Residue Architectures for Cryptography 17. Defense Against Primary User Emulation Attacks in Cognitive Radio Networks Using Advanced Encryption Standard 18. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
  2. 2. TECHNOS INC VLSI TITLES CHACKOTOWERS, ANNA NAGARMAIN ROAD,ANNA NAGAR,(NEXTTOSRI ANNAIXEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com 19. Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm 20. Eliminating Synchronization Latency Using Sequenced Latching 21. Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count 22. Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits 23. Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter 24. Non binary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm 25. Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely Constrained Secure Applications 26. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator 27. Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function 28. Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool 29. Parallel AES Encryption Engines for Many-Core Processor Arrays 30. Design of Testable Reversible Sequential Circuits 31. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes 32. A Novel Modulo Adder for 2n-2k- 1Residue Number System 33. Improvement of the Security of ZigBee by a New Chaotic Algorithm 34. CORDIC Based Fast Radix-2 DCT Algorithm 35. Split Radix Algorithm for Length 6mDFT 36. Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials 37. Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic 38. Multicarrier Systems Based on Multistage Layered IFFT Structure 39. Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
  3. 3. TECHNOS INC VLSI TITLES CHACKOTOWERS, ANNA NAGARMAIN ROAD,ANNA NAGAR,(NEXTTOSRI ANNAIXEROX), PUDUCHERRY CT: +91 9566492473, +91 9585338678. E-MAIL: contact.technos@gmail.com , technosprojects@gmail.com 40. Period Extension and Randomness Enhancement Using High-Throughput Reseeding- Mixing PRNG 41. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm 42. Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box 43. Low-Power and Area-Efficient Carry Select Adder