Parasitic Extraction Tanner EDA’s HiPer PX helps you reliably design high-performance circuits in modern process technologies.

First EDA solution on Windows Development, sales and support of IC design tools since 1988 25,000 installed seats worldwide – Global presence Expertise in advanced microelectronics research such as MEMS, speech recognition, active pixel imagers and data acquisition systems Tanner EDA Facts Tanner Research, Inc. Headquarters Monrovia, CA

First EDA solution on Windows

Development, sales and support of IC design tools since 1988

25,000 installed seats worldwide – Global presence

Expertise in advanced microelectronics research such as MEMS, speech recognition, active pixel imagers and data acquisition systems

Interconnect Parasitics in Modern Processes As process geometries shrink, the impact of interconnect parasitic effects gets larger Importance has shifted from vertical to lateral crosstalk capacitance

As process geometries shrink, the impact of interconnect parasitic effects gets larger

Importance has shifted from vertical to lateral crosstalk capacitance

Traditional Approaches Manual estimation on known-critical nets easy to miss unexpected problems Avoidance and mitigation techniques wasteful of area, time Lumped vertical extraction misses now-dominant lateral crosstalk capacitance

Manual estimation on known-critical nets

easy to miss unexpected problems

Avoidance and mitigation techniques

wasteful of area, time

Lumped vertical extraction

misses now-dominant lateral crosstalk capacitance

HiPer PX Tanner EDA’s parasitic extraction tool Proven technology Interconnect extract engine based on the long-running and influential Space project at TU Delft Integrated with L-Edit RC interconnect models 2D, 3D, and hybrid extract modes Frequency based circuit reduction

Tanner EDA’s parasitic extraction tool

Proven technology

Interconnect extract engine based on the long-running and influential Space project at TU Delft

Integrated with L-Edit

RC interconnect models

2D, 3D, and hybrid extract modes

Frequency based circuit reduction

HiPer PX – 2D and 3D 2-D Mode (table interpolation) 2-D extraction is extremely fast (>1M transistors/hr) Accurate enough for many designs, and fast enough to extract huge circuits 3-D Mode (boundary element) Maximum accuracy Still fast enough to run medium sized circuits (thousands of transistors)

2-D Mode (table interpolation)

2-D extraction is extremely fast (>1M transistors/hr)

Accurate enough for many designs, and fast enough to extract huge circuits

3-D Mode (boundary element)

Maximum accuracy

Still fast enough to run medium sized circuits (thousands of transistors)

Extract Early and Often HiPer PX extracts both devices and interconnect parasitics in one pass No requirement for an LVS pass; extract while you work and catch problems early

HiPer PX extracts both devices and interconnect parasitics in one pass

No requirement for an LVS pass; extract while you work and catch problems early

Accurate Post-Layout Simulations All resistors and capacitors are treated the same drawn resistors and capacitors divided into finite elements

All resistors and capacitors are treated the same

drawn resistors and capacitors divided into finite elements

Faster Simulations Netlist reduction fastest possible simulations with accuracy guaranteed up to specified frequency

Netlist reduction

fastest possible simulations with accuracy guaranteed up to specified frequency

Flexible Analyze just resistance or just capacitance at the push of a button Selectively extract parasitics on important nets Extract a single cell, a clipped out region, or the whole chip

Analyze just resistance or just capacitance at the push of a button

Selectively extract parasitics on important nets

Extract a single cell, a clipped out region, or the whole chip

Tanner EDA Find out more via: www.TannerEDA.com Contact sales: [email_address] 1-877-325-2223

Find out more via:

www.TannerEDA.com

Contact sales:

[email_address]

1-877-325-2223