Flip flop, latch, difference between flip flop & latch.ppt
Flip flop, latch,
difference between flip
flop and latch,
triggering and clocking,
shift register, its type
• Logic circuits are classified into two groups
i. Combinational circuit
ii. Sequential circuit
• Basic building block of combinational circuit is logic gates, while indeed
the basic building block of Sequential circuit is flip flops
• Flip flop has better and greater usage in shift register, counters and
• Flip flop is a storage device which store one bit data
• It has two input and two output labeled as Q and Q’
• Normal and complement
• Latch: it is also building block of sequentional circuit, which is constructed
by the pair of, neither, neither crossed, coupled of NOR gate...
• It is a digital storage device, serve as temporary buffer memory.
• There are three types of flip flop
i. Clocked S-R flip flop
ii. D flip flop
iii. J-K flip flop
S-R flip flop:
It has two input S and R and two output Q and Q’.
In flip flop output are always opposite, if Q=1
In wiring diagram of R-S flip flop, there are two
Types of flip flop
S R Q Q’ Effect of output
Prohibited 0 0 1 1 Prohibited do not use
Set 0 1 1 0 For setting Q to 1
Reset 1 0 0 1 For setting Q to 0
Hold 1 1 Q Q’ Depend on privious
Truth table of R-S flip flop
• D stands for delay.
• It has only one data input D and a clock signal
• Output are labeled as Q & Q’.
• Notice that output Q follows input D after one
clock puls (see Qn+1 column).
• D flip flop may be formed as clocked signal R-S
flip flop by adding an inverter.
D flip flop:
J-K flip flop
• J-K flip flop act as R-S flip flop except that it does
not have a invalid state.
• J & K does not mean any special but J is
equivalent to set and K is equivalent to reset.
• R=S=1 state has been replaced with a toggle
• Toggle means the output will change to the
opposite state (0 to 1 or 1 to 0) after every clock
• The JK is in R-S flip flop with feedback from Q &
• Flip flop and latch are two basic building blocks of
sequentional circuit but there is suitable
difference between the two is;
• A flip flop continuously checks its inputs and
corresponding changes its output only at times
determined by clocking the signal.
• Where as latch is a device which continuously
checks all its inputs and correspondingly changes
its output, independent of time determined by
Difference between flip flop and latch
•A unique signal called “enable” is provided with
•The output changes only when enable signal is
•No change in output take place when the
enable signal is inactive.
•Flip flop are edge trigger, while latches are level
• A trigger is a control signal used to initiate an
• In gated latches, the trigger is enable line.
Setting the enable high allows the latch to be
set or reset.
o There are two forms of trigger:
1.Level trigger (High or low)
2.Edge trigger (+ve or –ve going transition)
Triggering and clocking
• Shift registers are type of sequentional logic
circuits mainly for storage of digital data. The
word shift means the device which shift data
right or left. i.e. calculator
• They are a group of flip flop connected in chain so
that output from one flip flop becomes the input
of next flip flop.
• Most of the register posses no characteristics
internal sequence of states.
• All the flip flop are driven by common clock and
all are set or reset simultaneously.
• There are four types of shift registers;
1) Serial in, Serial out (SISO)
2) Serial in, Parallel out (SIPO)
3) Parallel in, Serial out (PISO)
4) Parallel in, Parallel out (PIPO)
Serial in Serial out
Serial in Parallel out
Parallel in Serial out
Parallel in Parallel out
1 0 1 1 0
1 0 1 1 0
1 0 1 1 0
1 0 1 1 0
• The serial load shift register is constructed from
four D flip flop. It is called four bit shift register
because it has four place to store data A, B, C, D.
• In table first clear (CLR input to 0) all output A, B,
C, D to 00000.
• This output 00000 remains same, while they are
await a clock pulse. Pulse the CLK input once the
output now will be 1000, again pulse clocking
Serial load shift register
• The serial load shift register, we studied last has
• It permits only one bit of information at a time
• And it losses all its data out the right side when it
• But in parallel load shift register given in figure it
permits 4 bit at once, these inputs are data inputs
A, B, C, D. This is just like rectangular feature, that
would put output data back into so that is not
Parallel load shift register
• There are so many applications of shift
i. To produce time delay,
ii. To simplify combinational logic
iii. To convert the serial data to parallel data.
• Shift register have both parallel and serial
input and outputs.
• This is bi directional shift register which
allow shifting to both direction LR or RL.
Application of shift register
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