Fresher eee
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Fresher eee






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Fresher eee Fresher eee Document Transcript

  • CURRICULUM VITAE Objective SUGANTHI.R To serve the organization with constant spirit, motivation, while 4/32,Officer colony, also taking up interesting and innovative tasks that places my career in 2nd cross street, Porur, the path of growth in the organization. Chennai-600 116. Academic Record E-Mail: 2005 – 2009 Bachelor Engineering Sugu_eee44@ Arulmigu Meenakshi Amman College Of Engg. Anna University : +91-9789441980 Kanchipuram Specialization: Electrical and Electronics Engineering Personal profile: Aggregate : 69% Father’s Name: Mr. RANGANATHAN.G Educational Records Date of Birth : 05-03-1988 Occupation : FARMER. 2004 – 2005 Higher Secondary Gender : Female Govt. Girls Higher Secondary School , Nationality : Indian Chengam. Marital Status : Single Aggregate: 63% Permanent Address: 2002 – 2003 SSLC Govt. Girls Higher Secondary School # 336, Theettandapattu post, Chengam Taluk, Chengam. Thiruvannamalai Dist., Tamilnadu, India. -606701 Aggregate: 73% Technical Profile Linguistic: Language : C. Spoken : Tamil, Platforms : Windows XP English, Hardware : Programmable Logic Controller (PLC) Kannadam. Competencies Write : Tamil,  Good written communication and presentation skills. English,  Quick learner. Kannadam.  Self-starter and motivated. Read : Tamil, English,
  • Achievements  Participated in District level Athletics and Won 1st Prize in Relay and 2 Interests and Hobbies Prize in Hurdle Reading books, Playing and  Participated in District level Athletics and Won 2nd prize in 800m Net surfing. Running.  Participated in District level Volley-ball and Won 2nd prize. Preferences :  Attended College level NSS campus. Location : Anywhere Project Details Project Title : IMPLEMENTATION OF LOW OUTPUT RIPPLE DC-DC CONVERTER. Environment : Based on POWER ELECRONICS Duration : 4 Months Description The my project is new converter topology is described for application requiring very low output current ripple. The proposed converter consist of two asymmetric off-bridge converter whose output voltage overlap in a finite interval time. The converter provide well regulator on smooth DC output for wide ranges of input and load condition using very small . Comm Declaration I hereby declare that all the details furnished above are true and correct to the best of my knowledge and belief. Date : ____________________ Place : Chennai (SUGANTHI.R)