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• Click to edit Master text styles  – Second level     • Third level         – Fourthg i t a l D e s i g n u s i n g V H D...
about Start Group• Click to edit Master text styles   Mahmoud Abdellatif  – Second level  Alaa Salah Shehata   Mohamed lev...
Refresh Your Memory                                                   5                                              X1   ...
Refresh Your Memory                      [Solution]                                                               5       ...
Outline• Click to edit Master text styles  – Second level     • Third level                            Data Objects : Sign...
Outline• Click to edit Master text styles  – Second level            Data Objects : Signals     • Third level          VHD...
Signals• Click to edit Master text stylesSignals used to connect between systems or connect components inside a systemSign...
Internal Signals• Click to edit Master text stylesSignal Declaration       – Second levelarchitecture <arch_name> of <enti...
Example 05NAND Gate • Click to edit Master text styles        – Second levelLIBRARY ieee;USE ieee.std_logic_1164.all;     ...
Exercise 01Write VHDL code for this logic circuit• Click to edit Master text stylesA    – Second level          • Third le...
Exercise 01         [Solution]Write the VHDL code for this logic circuit • Click to edit Master text stylesLIBRARY ieee;  ...
Outline• Click to edit Master text styles  – Second level            Data Objects : Signals     • Third level          VHD...
Combinational Vs. Sequential logic• Click to edit Master text stylesin any digital system we can divide the circuits into ...
Concurrent & sequential statements• Click to edit Master text stylesVHDL has concurrent statements and sequential statemen...
Process-What is a Process• Click to edit Master text styles           Process allows writing sequential statements within ...
ProcessArchitecture behave of comb_ct is• Click to edit Master text stylesBegin   process (x,y)   begin     – Second level...
IF Statement• Click to edit Master text stylesExecutes a list of sequential statements when the corresponding condition ev...
CASE StatementMakes several conditions on the same signal• Click to edit Master text stylesSyntax     – Second levelcase <...
Outline• Click to edit Master text styles  – Second level            Data Objects : Signals     • Third level          VHD...
Example 06Logic Gate • Click to edit Master text stylesLIBRARY ieee;USE ieee.std_logic_1164.all;      – Second level      ...
Example 07Comparator • Click to edit Master text stylesLIBRARY ieee;USE ieee.std_logic_1164.all;     – Second levelENTITY ...
Example 084 x 1 Multiplexer • Click to edit Master text stylesArchitecture rtl of mux_case is      – Second level         ...
Lab 01• Click to edit2 Master text stylesTitle:      Simulation of a X 4 Decoder on ModelSim         – Second of a simple ...
Lab 01 • Click to edit Master text styles2 X 4 Decoder     – Second levelArchitecture rtl of dec isbegin                  ...
Outline• Click to edit Master text styles  – Second level            Data Objects : Signals     • Third level          VHD...
Sequential Circuits • Click to edit Master text styles      – Second level           •Clock period   Third level          ...
D-Flip Flop• Click to edit Master text styles                                               Reset        Clk         Enabl...
D-Latch• Click to edit Master text styles                                               Reset   Clk   Enable   Q+D        ...
D-Latch vs D-Flip Flop• Click to edit Master text styles        – Second levelWith a D-latch working on High level of cloc...
Example 09Simple D-FF • Click to edit Master text styles                                                       DLibrary ie...
Example 10D-FF with asynchronous reset • Click to edit Master text stylesLibrary ieee;                                    ...
Example 11D-FF with asynchronous reset and clock enable • Click to edit Master text stylesLibrary ieee;                   ...
Example 12D_Latch (positive level) • Click to edit Master text styleslibrary ieee;                                        ...
Start Notes     [Synthesis Notes]• Click to edit Master text D-FF coding                 Example of illegal styles        ...
Start Notes      [Synthesis Notes]• Click to edit MasterRegister D-FF coding                 Example oftext styles        ...
Start Notes        [Simulation Notes]• Click to edit Master text styles                Example of common errors     – Seco...
Start Notes        [Simulation Notes]• Click to edit Master text styles      – Second levelCover all Cases            • Th...
Outline• Click to edit Master text styles  – Second level            Data Objects : Signals     • Third level          VHD...
Mini Project• ALU Arithmetic Logic UnitMaster text styles-   Click to edit      – Second level    It is a circuit capable ...
Mini Project                 Sel          Operation      Function                Unit                 0000         Y<= a  ...
Mini Project-   Required• Click to edit Master text styles           -VHDL code of this ALU           -Verify functionalit...
Assignment 02• Click to edit Master text styles     – Second levelWrite a code describing a 8-bit Register           • Thi...
Summary• Click to edit Master text styles-   Signals are used for internal wiring.-     – Second level    Concurrent state...
Time for Your Questions• Click to edit Master text styles  – Second level     • Third level        – Fourth level         ...
Download Session 02 Files• Click to edit Master text stylesRead Session- 2 Examples carefully to be ready for the next ses...
Take Your Notes                                       Print the slides and take your notes here---------------------------...
Take Your Notes                                       Print the slides and take your notes here---------------------------...
See You Next Session .. Don’t miss• Click to edit Master text styles                     Thank  – Second level     • Third...
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Session 02 v.3

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Transcript of "Session 02 v.3"

  1. 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Two » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
  2. 2. about Start Group• Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Two 2
  3. 3. Refresh Your Memory 5 X1 Y • Click to this codeFind the 7 errors inedit Master text styles X2 5 AND_GATE 5 – Second levellibrary IEEE; • Third levelEntity 5_AND_GATE isPort ( – Fourth levelX1 : in std_logic(5 downto 0 ); » Fifth levelX2 : in std_logic(5 downto 0 );Y : out std_logic(5 downto 0 ); );END 5_and_gate; RefreshArchitecture Behave of AND_GATE_5 IS Your Memory Slides Y <= X1 AND X2 ;END 5_AND_GATE; Session Two 3
  4. 4. Refresh Your Memory [Solution] 5 X1 Y • Click to edit Master text styles X2 5 AND_GATE 5 – Second levellibrary IEEE; • Third levelUSE ieee.std_logic_1164.all; -- 1 Use Package to define operations on std_logic data type – FourthEntity AND_GATE is level -- 2 Don’t Start with numberPort ( » Fifth levelX1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data typeX2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0Y : out std_logic_vector(4 downto 0 ) -- 5 No ; );END AND_GATE;Architecture Behave of AND_GATE IS -- 6 wrong entity nameBegin --7 Reserved wordY <= X1 AND X2 ;END behave ; -- 8 architecture name Session Two 4
  5. 5. Outline• Click to edit Master text styles – Second level • Third level Data Objects : Signals VHDL Statements - Sequential Statements 2 – Fourth level - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 5
  6. 6. Outline• Click to edit Master text styles – Second level Data Objects : Signals • Third level VHDL Statements – Fourth level - Sequential Statements - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 6
  7. 7. Signals• Click to edit Master text stylesSignals used to connect between systems or connect components inside a systemSignals represent physical wiring in hardware – Second levelTypes of signals • Third level -- External Signals – Fourth level Inout ports -In,Out and -Internal connections in structural Description discussed later -- Internal Signals level » Fifth -Connect devices inside the block -Used for Intermediate calculationsNoteWe use Internal Signals for: - Avoid illegal port usage situations like Read Output port - Internal Connections ‘wiring’ Session Two 7
  8. 8. Internal Signals• Click to edit Master text stylesSignal Declaration – Second levelarchitecture <arch_name> of <entity_name> is • Third level -- architecture declarations signal <sig_name> : <sig_type>; – Fourth level. .begin » Fifth level <Architecture body>End <arch_name> ;Note we don’t define a mode for internal signals Session Two 8
  9. 9. Example 05NAND Gate • Click to edit Master text styles – Second levelLIBRARY ieee;USE ieee.std_logic_1164.all; A E DENTITY • Third NAND_GATE ISlevel port ( A,B B C – Fourth STD_LOGIC; : in level : in STD_LOGIC; D : » Fifth level out STD_LOGIC C );END ENTITY NAND_GATE ;ARCHITECTURE behave OF NAND_GATE IS SIGNAL E : std_logic;BEGIN E <= A and B ; D <= E and C ;END behave; Session Two 9
  10. 10. Exercise 01Write VHDL code for this logic circuit• Click to edit Master text stylesA – Second level • Third level GB – Fourth level » Fifth levelC FD Session Two 10
  11. 11. Exercise 01 [Solution]Write the VHDL code for this logic circuit • Click to edit Master text stylesLIBRARY ieee; A – Second levelUSE ieee.std_logic_1164.all; SIG_1 GENTITY NAND_GATE IS B • Third level port ( A,B,C,D : in STD_LOGIC; G,F ); – Fourth STD_LOGIC : out levelEND ENTITY NAND_GATE Fifth level » ; C SIG_2ARCHITECTURE behave OF NAND_GATE IS SIGNAL SIG_1 : std_logic; F SIGNAL SIG_2 : std_logic; DBEGIN SIG_1 <= A and B ; SIG_2 <= SIG_1 and C ; F <= SIG_2 and D ; G <= SIG_1 ;END behave; Session Two 11
  12. 12. Outline• Click to edit Master text styles – Second level Data Objects : Signals • Third level VHDL Statements – Fourth level - Sequential Statements - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 12
  13. 13. Combinational Vs. Sequential logic• Click to edit Master text stylesin any digital system we can divide the circuits into two types : – Second level • Third levelCombinational logic circuitsimplement Boolean functions, so the output in this circuits isfunction only on– Fourth level are not based on previous their inputs, andoutputs. » Fifth levelSequential circuitscompute their output based on input and state(previousoutputs), and that the state is updated based on a clock. Session Two 13
  14. 14. Concurrent & sequential statements• Click to edit Master text stylesVHDL has concurrent statements and sequential statements – Second level•Concurrent statements are executed in parallel w.r.t each other. Process statement • Third level Assign statement With – select When– Fourth level – else » Fifth level•Sequential statements are executed in sequence w.r.t each other. Sequential statements should be written inside a “process” If statement Case statement loop statements Wait and Null statement Session Two 14
  15. 15. Process-What is a Process• Click to edit Master text styles Process allows writing sequential statements within concurrentenvironment – Second level Process is like a container that include the sequential statementsProcess declaration • Third levelprocess (sensitivity list)begin – Fourth level sequential statements ; » Fifth levelend process ;Note<sensitivity_list>: List of signals/input ports that cause the process to be executed whenever there is a change in their values Session Two 15
  16. 16. ProcessArchitecture behave of comb_ct is• Click to edit Master text stylesBegin process (x,y) begin – Second level z <= x and y; • Third or y; h <= x level t <= x xor y; – Fourth level … end process;» Fifth levelEnd behave ;Statements inside a “process” are read sequentially and executed when the process suspends(“end process” is reached)very important note:Process executed one time then become ready for a change on its sensitivity list.How is this statement differs from z<= x and y; Session Two 16
  17. 17. IF Statement• Click to edit Master text stylesExecutes a list of sequential statements when the corresponding condition evaluates to true – Second levelV.IMPORTANT ROLE The branches order is important as they imply a prioritySyntax • Third level – Fourth level » Fifth levelIf <condition> then -- list of sequential statementselsif <condition> then -- list of sequential statementselse -- list of sequential statementsend if;<condition> Boolean expression that evaluates to either TRUE or FALSE Session Two 17
  18. 18. CASE StatementMakes several conditions on the same signal• Click to edit Master text stylesSyntax – Second levelcase <expression> is • Third level when <choice> => -- list of sequential statements when <choice> – Fourth level => -- list of sequential statements when others => » Fifth level -- list of sequential statementsend case;<expression> can be a signal [or a variable (discussed later)]<choice> constants representing one of possible <expression> values.V.IMPORTANT ROLE -“When others” is a must if not all values of <expression> are covered - Each branch of a Case statement can have any number of sequential statements Session Two 18
  19. 19. Outline• Click to edit Master text styles – Second level Data Objects : Signals • Third level VHDL Statements – Fourth level - Sequential Statements - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 19
  20. 20. Example 06Logic Gate • Click to edit Master text stylesLIBRARY ieee;USE ieee.std_logic_1164.all; – Second level AENTITY logic_gate IS C Logic Gate port ( a, b C • Third level : in std_logic; : out std_logic; B Sel : in std_logic); – Fourth levelEND ENTITY logic_gate; » Fifth levelARCHITECTURE behave OF logic_gate IS BEGIN process ( What is sensitivitySel !! a, b, list ) Sel begin if (Sel= 1) then Operation = 1  a and b C <= a and b; Operation = 0  a or b elsif (Sel = „0) then C <= a or b; else C <= „Z‟; end if; end process;END ARCHITECTURE behave; Session Two 20
  21. 21. Example 07Comparator • Click to edit Master text stylesLIBRARY ieee;USE ieee.std_logic_1164.all; – Second levelENTITY comparator IS port( a, b : in std_logic_vector(7 downto 0); c • Third level : out std_logic_vector(1 downto 0); );END ENTITY; – Fourth levelARCHITECTURE behave OF comparator ISBEGIN » Fifth level process (a, b) A begin C if (A = B ) then -- equality Comparator c <= "00"; elsif (A > B) then -- greater than B c <= "01"; elsif (A < B) then -- greater than c <= "10"; A=B C=“00” else -- covers other cases c <= “ZZ"; A>B C=“01” end if; A<B C=“10” end process;END ARCHITECTURE; Session Two 21
  22. 22. Example 084 x 1 Multiplexer • Click to edit Master text stylesArchitecture rtl of mux_case is – Second level Abegin process (a,b,c,d,sel) B Fbegin • Third level CCase sel is When "00" => – Fourth level D f <= a; When "01" => » Fifth level f <= b; When "10" => Sel f <= c; When "11" => f <= d; when others => -- is "when others“ a must? f <= „Z‟; Do we need all these signals? OnEnd case; sensitivity list ?? End process;End architecture; Session Two 22
  23. 23. Lab 01• Click to edit2 Master text stylesTitle: Simulation of a X 4 Decoder on ModelSim – Second of a simple 8-bits Comparator Simulation levelGoal: • Third level  Creating new project on ModelSim  – Fourth a combinational circuit Simulation oflevel » Fifth level Tutorial [1] Slides Session Two 23
  24. 24. Lab 01 • Click to edit Master text styles2 X 4 Decoder – Second levelArchitecture rtl of dec isbegin a f process (a) begin • Third levelCase a is When "00" => – Fourth level f <= “0001”;Fifth level » When "01" => f <= “0010”; When "10" => f <= “0100”; When "11" => f <= “1000”; when others => f <= “ZZZZ”;End case; End process;End rtl ; Session Two 24
  25. 25. Outline• Click to edit Master text styles – Second level Data Objects : Signals • Third level VHDL Statements – Fourth level - Sequential Statements - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 25
  26. 26. Sequential Circuits • Click to edit Master text styles – Second level •Clock period Third level – Fourth level A digital clock signal is a square wave voltage. In complex circuits a clock withlevel frequency is used for timing. » Fifth a fixed To store and pass the data or digital signals through, some specific gates are used which are called latches or flip-flops. These are some kind of memory that store their input over their output by a specific level or edge of the clock. Asynchronous Operation don’t wait clock Synchronous Operation wait clock to get an input and to produce an output Session Two 26
  27. 27. D-Flip Flop• Click to edit Master text styles Reset Clk Enable Q+D 1 - - 0 Q – Second level 0 No rising_edge - QReset 0 Rising_edge 0 Q • Third level D_FF 0 Rising_edge 1 Denable – Fourth level » Fifth level clkClock periodAsynchronous resetSynchronous enable Session Two 27
  28. 28. D-Latch• Click to edit Master text styles Reset Clk Enable Q+D 1 - - 0 Q – Second level 0 0 - QReset 0 1 0 Q • Third level D_Latch 0 1 1 Denable – Fourth level » Fifth level clkClock periodAsynchronous resetSynchronous enable Session Two 28
  29. 29. D-Latch vs D-Flip Flop• Click to edit Master text styles – Second levelWith a D-latch working on High level of clock , a signal can’t propagate through until theclock is high . • Third levelWith a rising edge D-Flip-flop, the signal only propagates through on the rising edge. – Fourth level » Fifth levelClock D Q D_Latch D-Flip Flop Session Two 29
  30. 30. Example 09Simple D-FF • Click to edit Master text styles DLibrary ieee; – Second leveluse ieee.std_logic_1164.all; Q D_FF • Third levelEntity d_ff is Port( D, clk : in std_logic; Q – Fourth std_logic ); : out levelend entity; » Fifth levelArchitecture behav of d_ff is clkBegin process(clk) begin if rising_edge(clk) then Q <= D; end if; rising_edge() : function defined for std_logic type end process; Used to detect rising edge of clockend behav; Session Two 30
  31. 31. Example 10D-FF with asynchronous reset • Click to edit Master text stylesLibrary ieee; D – Second leveluse ieee.std_logic_1164.all; QEntity d_ff is • Third level Reset D_FF Port( d, clk, rst : in std_logic; Q : out std_logic);end entity; – Fourth levelArchitecture behav » Fifth level of d_ff isBegin process(clk, rst) clk begin If (rst = 1) then Q <= 0; elsif rising_edge(clk) then Since rst has higher priority over the clk edge Q <= d; then, We put it on sensitivity list end if; end process; We have now a D Flip Flop with asynchronous resetend behav; Session Two 31
  32. 32. Example 11D-FF with asynchronous reset and clock enable • Click to edit Master text stylesLibrary ieee; Reset 1 Clk - Enable - Q+ 0use ieee.std_logic_1164.all; – Second levelEntity d_ff is 0 No rising_edge - Q 0 Rising_edge 0 Q Q • Third level Port( d, clk, rst,en : in std_logic; : out std_logic); 0 Rising_edge 1 Dend entity; – Fourth levelArchitecture behav » Fifth level of d_ff isBegin process(clk, rst) begin If (rst = 1) then Q <= 0; Enable has lower priority w.r.t the clk edge elsif rising_edge(clk) then So we don’t put it in sensitivity list as it has no If (en = 1) then value and will slow the simulation Q <= d; end if; end if; We have now a D Flip Flop with asynchronous end process; reset and synchronous enableend behav; Session Two 32
  33. 33. Example 12D_Latch (positive level) • Click to edit Master text styleslibrary ieee; Reset 1 Clk - Q+ 0use ieee.std_logic_1164.ALL; – Second levelentity d_ff is 0 0 Q 0 1 Dport( • Third level clk,reset,enable: in std_logic; d: in – Fourth level std_logic; q: out std_logic);end d_ff; » Fifth levelarchitecture Behavioral of d_ff isbeginprocess(clk,reset,d)begin Latch depend on input every time it changes if reset = 1 then while clk =‘1’ so if clk still =‘1’ and input changes q<= 0; process should be triggered elsif clk = 1 then So, d on sensitivity list q<= d; end if;end process;end Behavioral; Session Two 33
  34. 34. Start Notes [Synthesis Notes]• Click to edit Master text D-FF coding Example of illegal styles Legal in VHDL but not synthesized – Second levelD-FF coding rules if reset = 1 then • Third levelFF is a the basic memory q <= 0; Elsif rising_edge(clk)thenunit . We need –a Fourth level lot to q <= d;register the data. Some Elsif d = ‘1’ then » Fifth levelrules should be done on q <= not d;flip flop to be written in end if;the right way. You needonly to keep in your mind this code also not synthesizedthe D-FF code, Latches are if enable = 1 thennot preferred to be used to if rising_edge(clk)thenavoid glitches. q <= d; end if; end if; Session Two 34
  35. 35. Start Notes [Synthesis Notes]• Click to edit MasterRegister D-FF coding Example oftext styles illegal or latch – Second level • Third level Reg : Process (clk) begin – Fourth level if clk = 1 then q <= d; » Fifth level if; end End process reg; The Answer is not latch as d is not in sensitivity list not register (no clock edges detected) Session Two 35
  36. 36. Start Notes [Simulation Notes]• Click to edit Master text styles Example of common errors – Second levelRead Errors forget end if ; awhen you use else if pattern instead of elsif pattern • Third levelYou Should read the error – Fourthfirst , don’t be disturbed. levelCompilers always give » Fifth level you if reset = 1 thenthe position where the q<= 0;error is and also may help Else if clk = 1 thenyou know the reason of q<= d;the error, you may also end if;search the error on theinternet . Session Two 36
  37. 37. Start Notes [Simulation Notes]• Click to edit Master text styles – Second levelCover all Cases • Third levelTo make sure that your – Fourthcode is working well, cover levelall cases that your code go » Fifth levelinside. For example, inmany cases you may see ‘X’values that mean there ismultiple drivers to aspecific signal . Or ‘U’ valuefor unitialized signals Session Two 37
  38. 38. Outline• Click to edit Master text styles – Second level Data Objects : Signals • Third level VHDL Statements – Fourth level - Sequential Statements - What is Process » Fifth level - IF Statement - CASE Statement - Combinational Logic - Sequential Logic Mini Project no.1 ALU Session Two 38
  39. 39. Mini Project• ALU Arithmetic Logic UnitMaster text styles- Click to edit – Second level It is a circuit capable of executing both kinds of operations, arithmetic as well as logical. Its operation is described next slide as follow : • Third level The output (arithmetic or logical) is selected by the MSB of sel The specific operation is selected by sel’s other three bits. – Fourth level » Fifth level A(7:0) Logic B(7:0) Unit C(7:0) Arithmetic Unit Cin SEL(3:0) Session Two 39
  40. 40. Mini Project Sel Operation Function Unit 0000 Y<= a Transfer A• Click to edit MasterY<= a+1 styles A 0001 text Increment 0010 Y<= a-1 Decrement A – Second level 0011 Y<= b Transfer B 0100 Y<= b+1 Increment A • Third level Arithmetic 0101 Y<= b-1 Decrement A – Fourth level 0110 Y<= a+b Add a and b » Fifth level 0111 Y<= a+b+cin Add a and b and carry 1000 Y<= not a Complement a 1001 Y<= not b Complement b 1010 Y<= a AND b AND 1011 Y<= a OR b OR Logic 1100 Y<= a NAND b NAND 1101 Y<= a NOR b NOR 1110 Y<= a XOR b XOR 1111 Y<= a XNOR b XNOR Session Two 40
  41. 41. Mini Project- Required• Click to edit Master text styles -VHDL code of this ALU -Verify functionality using ModelSim (Waveforms required) – Second level -Use ieee.std_logic_arith.all; package in your design- • Deadline Third level -After Next session – Fourth level » Fifth level A(7:0) Logic B(7:0) Unit C(7:0) Arithmetic Unit Cin SEL(3:0) Session Two 41
  42. 42. Assignment 02• Click to edit Master text styles – Second levelWrite a code describing a 8-bit Register • Third levelGrouping Eight D_FF translated into a Register. Describe it with two outputs Q and inverted Q – Fourth level » Fifth level D Q Reset Register Q’ clk Session Two 42
  43. 43. Summary• Click to edit Master text styles- Signals are used for internal wiring.- – Second level Concurrent statements and Sequential statements are statements types of VHDL.- IF ELSIF ELSE and CASE statements should be written inside PROCESS- Process• Third level that should contain all signals have priority than clock. has sensitivity list- D-FF is the main memory unit in Digital logic design. – Fourth level » Fifth level Examples Exercises Labs 5-12 1 1 Session Two 43
  44. 44. Time for Your Questions• Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session Two 44
  45. 45. Download Session 02 Files• Click to edit Master text stylesRead Session- 2 Examples carefully to be ready for the next session’s LAB QUIZ –Lab 01 www.startgroup.weebly.com/vhdl-examples.html Second level • Third level – Fourth level Reserved Words of VHDL www.startgroup.weebly.com/vhdl-examples.html » Fifth level Related Sessions Tutorial 1 Refresh Your Memory 1 Session Two 45
  46. 46. Take Your Notes Print the slides and take your notes here---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ – Second level------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ • Third level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- – Fourth level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- » Fifth level----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  47. 47. Take Your Notes Print the slides and take your notes here---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ – Second level------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ • Third level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- – Fourth level---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- » Fifth level----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  48. 48. See You Next Session .. Don’t miss• Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level
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