Refresh your memory 1

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Refresh your memory 1

  1. 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Two » Fifth level Refresh Your Memory Introduced byName :Group : Cairo-Egypt Session Zero Version 03 – June 2012 1
  2. 2. Refresh Your Memory 5 X1 Y • Click to this codeFind the 8 errors inedit Master text styles X2 5 AND_GATE 5 – Second levellibrary IEEE; • Third levelEntity 5_AND_GATE isPort ( – Fourth levelX1 : in std_logic(5 downto 0 ); » Fifth levelX2 : in std_logic(5 downto 0 );Y : out std_logic(5 downto 0 ); );END 5_and_gate;Architecture Behave of AND_GATE_5 IS Y <= X1 AND X2 ;END 5_AND_GATE; Session Two 2
  3. 3. Refresh Your Memory [Solution] 5 X1 Y • Click to edit Master text styles X2 5 AND_GATE 5 – Second levellibrary IEEE; • Third levelUSE ieee.std_logic_1164.all; -- 1 Use Package to define operations on std_logic data type – FourthEntity AND_GATE is level -- 2 Don’t Start with numberPort ( » Fifth levelX1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data typeX2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0Y : out std_logic_vector(4 downto 0 ); -- 5 No ; );END AND_GATE;Architecture Behave of AND_GATE IS -- 6 architecture of above entityBegin --7 Reserved wordY <= X1 AND X2 ;END behave ; -- 8 architecture name Session Two 3

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