Summer 2012                                                                           3rd Intake• Click to edit Master tex...
about Start Group• Click to edit Master text styles   Mahmoud Abdellatif  – Second level  Alaa Salah Shehata   Mohamed lev...
Digital Design using VHDL courseCourse overview  • Click to edit Master text styles     •Obtain a general appreciation of ...
Course OutlineSession One              -Introduction to the course                        Session Three• Click to edit Mas...
Course OutlineSession Five• Click to edit Master text styles                -Data types                     -Scalar types ...
FPGA WorkshopAfter 9th Session Start Group introduces the last session• Click to edit Master text stylesusing sparton-3E F...
Sessions in a Different Way !!                                       We fill the sessions                                 ...
Download                     CD includes Start Group     Tools Used during course                 Start Group             ...
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Intrduction to the course v.3

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Intrduction to the course v.3

  1. 1. Summer 2012 3rd Intake• Click to edit Master text styles Introduction to the Course – Second level Digital Design using VHDL • Third level Start Group – Fourth level » Fifth level Introduced by  About Start Group  Digital Design using VHDL course  Sessions Plan Cairo-Egypt  Course Outline Introduction 1
  2. 2. about Start Group• Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Introduction 2
  3. 3. Digital Design using VHDL courseCourse overview • Click to edit Master text styles •Obtain a general appreciation of what VHDL is as a hardware description language, and how it is used in the hardware design process. – Second level • Get a comprehensive overview about the VHDL language. • Create synthesizable models (behavioral coding style) • Third level • Use VHDL component instantiations to create hierarchy (structural coding style) – role of level •Understand theFourthtest-benches in gate level simulationCourse Application » Fifth level • Please send to start.courses@gmail.com • In E-mail subject write “Digital Design Course” • in E-mail body write Full Name University Department and Year (example : ECE 2014 – CSE2013 …) Mobile numberCourse prerequisites Basic Digital /Logic conceptsCourse Duration 32 Hours / 10 SessionsCourse Costs 400 LE Introduction 3
  4. 4. Course OutlineSession One -Introduction to the course Session Three• Click to edit Master text styles -Introduction to Digital Design -Introduction to VHDL -Concurrent Statements -Assign statement -Process -What is VHDL – Second level -Why VHDL -when-else -ASIC and FPGA Design Flow -with-select-when -How to read a VHDL code -Combinational circuits • Third level -Libraries and Packages -Entity -Multiplexers, Encoders and Decoders -Modeling concurrency -Architecture -Events and Transactions – Fourth level -Basic data types : BIT vs STD_LOGIC -Data Objects -Simple Combinational logic circuits -External and Internal Signals » Fifth level -Demo 1 : Using Modelsim and Xilinx tools -Variables -ConstantsSession Two -Data Objects : Signals -Statements in VHDL Session Four -Sequential Statements -Data Operators -What is Process -Aggregate -If statement -Concatenation -Case Statement -Attributes -Combinational circuits -Other data operators -Multiplexers, Encoders and Decoders -Simple Counters -Resource sharing -Controlled counters -Sequential Circuits -Rotating LEDs -Flip Flops (DFF-TFF) -Bi-direction Rotating LEDs -Latches -mini-Project no.1 Introduction 4
  5. 5. Course OutlineSession Five• Click to edit Master text styles -Data types -Scalar types Session Eight -Evaluation test -Composite types – Second level -User defined types -Modeling memories -Digital Arithmetic -Generating IP cores -Simulating IP Cores -ROMs • Third level -RAMs -mini-project no.2 -Xilinx Lang. TemplatesSession Six – Fourth level Session Nine -Testbenches » Fifth level -Why -FSM finite state machines -How to generate testbench -More machine -Using Do files -Mealy machine -Modelsim Simulation notes -FSM in VHDL -Loops -Vending machine example -For-Loop -String Detectors -While-Loop -Wait StatementSession Seven -Assert Statement -Design styles -Functions and Procedures -Structural Description -Reading and Writing in files -Components Instantiation -Generic Statement -FOR-GENERATE statement Session 10  FPGA workshop -Packages -VHDL Guide Introduction 5
  6. 6. FPGA WorkshopAfter 9th Session Start Group introduces the last session• Click to edit Master text stylesusing sparton-3E FPGA – Second -VHDL summary FPGA WorkShop level -Introduction to FPGA • Third level -FPGA Structure -Sparton-3E FPGA – Fourth level on FPGA -Implementation » Fifth level -Introduction to Xilinx -Xilinx Tool Flow -Xilinx Product Families -Selection of Xilinx Device -Synthesizing the design -Specifying User Constraints -Translate -Map -Place and Route [PAR] -Generating BitMap File - Configuration of selected Device -Main project discussion Introduction 6
  7. 7. Sessions in a Different Way !! We fill the sessions with our experience The way we control our through Simulation sessions is why we are and synthesis notes . the best. Exercises During sessions there & • Click to edit Master text styles are four main things weIllustration do : There will be many ExamplesLabs • Illustration Mini Projects during – Second level mini-projects • • Examples Exercises sessions to be familiar with projects. • Labs • Third level Time for The Main Project ,chosen carefully, will Questions At first of every session –Demoes Assignments Fourth levelFast you will refresh your double the experience you gain during course Questions memory through MCQs sessions in Digital » Fifth level Main-Project and simple questions. Design Field . You will Summary Refresh Your During sessions there is be ready after this project to make Memory Demoes for parts we graduation project or will discuss later, parts even your own out of our scope or for Start Notes our tutorials. projects. Before the end of the Evaluation Test At end of every session course an Evaluation there is a Time for Test introduced by Questions, Assignments Start Group evaluates Logo used at top of each slide to show you what we are (Homework ). everyone and focuses talking about .. We will never let You puzzled on points of weakness. 50 % Labs … 50 % Illustration
  8. 8. Download CD includes Start Group Tools Used during course Start Group materials & • Click to edit Master text styles material references is available – Second level • Third level – Fourth level » Fifth levelSpartan-3E Starter Kit Board Sessions Slides Used during the course VHDL Guide Certified from Start Group 2011 VHDL Summaries Tutorials See You Next Session  8

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