VLSI Testing Lecture 12: System Diagnosis <ul><li>Definition </li></ul><ul><li>Functional test </li></ul><ul><li>Diagnosti...
A System and Its Testing <ul><li>A system is an organization of components (hardware/software parts and subsystems) with c...
System Test Applications Copyright 2001, Agrawal & Bushnell Lecture 12: System Test A Application  Functional test  Diagno...
Functional Test <ul><li>All or selected (critical) operations executed with non-exhaustive data. </li></ul><ul><li>Tests a...
Gate-Level Diagnosis Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fault...
Gate Replacement Fault Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fau...
Bridging Fault Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests...
Fault Dictionary Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Fault  Test syndrome  t 1   t 2  t 3  t 4 No f...
Diagnosis with Dictionary Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Fault  Test syndrome  Diagnosis t 1  ...
Diagnostic Tree Copyright 2001, Agrawal & Bushnell Lecture 12: System Test T4 T1 T2 T3 No fault found T3 T2 b 1 a 1 c 1 , ...
System Test: PCB vs. SOC <ul><li>Tested parts </li></ul><ul><li>In-circuit test (ICT) </li></ul><ul><li>Easy test access <...
Core-Based Design <ul><li>Cores are predesigned and verified but untested blocks: </li></ul><ul><ul><li>Soft core (synthes...
Partitioning for Test <ul><li>Partition according to test methodology: </li></ul><ul><ul><li>Logic blocks </li></ul></ul><...
Test-Wrapper for a Core <ul><li>Test-wrapper (or collar) is the logic added around a core to provide test access to the em...
A Test-Wrapper Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Wrapper test controller Scan chain  Scan chain  ...
Overhead of Test Access <ul><li>Test access is non-intrusive. </li></ul><ul><li>Hardware is added to each I/O signal of bl...
Overhead Estimate Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Rent’s rule: For a logic block the number of ...
DFT Architecture for SOC Copyright 2001, Agrawal & Bushnell Lecture 12: System Test User defined test access mechanism (TA...
DFT Components <ul><li>Test source :  Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. </li></ul><ul...
Summary <ul><li>Functional test: verify system hardware, software, function and performance; pass/fail test with limited d...
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Copyright 2001, Agrawal

  1. 1. VLSI Testing Lecture 12: System Diagnosis <ul><li>Definition </li></ul><ul><li>Functional test </li></ul><ul><li>Diagnostic test </li></ul><ul><ul><li>Fault dictionary </li></ul></ul><ul><ul><li>Diagnostic tree </li></ul></ul><ul><li>System design-for-testability (DFT) architecture </li></ul><ul><ul><li>System partitioning </li></ul></ul><ul><ul><li>Core test-wrapper </li></ul></ul><ul><ul><li>DFT overhead </li></ul></ul><ul><li>Summary </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  2. 2. A System and Its Testing <ul><li>A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. </li></ul><ul><li>Functional test verifies integrity of system: </li></ul><ul><ul><ul><li>Checks for presence and sanity of subsystems </li></ul></ul></ul><ul><ul><ul><li>Checks for system specifications </li></ul></ul></ul><ul><ul><ul><li>Executes selected (critical) functions </li></ul></ul></ul><ul><li>Diagnostic test isolates faulty part: </li></ul><ul><ul><ul><li>For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystem </li></ul></ul></ul><ul><ul><ul><li>For shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a board </li></ul></ul></ul><ul><ul><ul><li>Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution </li></ul></ul></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  3. 3. System Test Applications Copyright 2001, Agrawal & Bushnell Lecture 12: System Test A Application Functional test Diagnostic test Resolution Manufacturing Yes LRU, SRU Maintenance Yes Field repair LRU Shop repair SRU LRU: Lowest replaceable unit SRU: Shop replaceable unit
  4. 4. Functional Test <ul><li>All or selected (critical) operations executed with non-exhaustive data. </li></ul><ul><li>Tests are a subset of design verification tests (test-benches). </li></ul><ul><li>Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage. </li></ul><ul><li>Examples: </li></ul><ul><ul><ul><li>Microprocessor test – all instructions with random data (David, 1998). </li></ul></ul></ul><ul><ul><ul><li>Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC -1980). </li></ul></ul></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  5. 5. Gate-Level Diagnosis Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 T2 = 011 T3 = 100 T4 = 110 Logic circuit Karnaugh map (shaded squares are true outputs)
  6. 6. Gate Replacement Fault Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (fail) T3 = 100 (pass) T4 = 110 (fail) Faulty circuit (OR replaced by AND) Karnaugh map (faulty output: red sqaure is 1 output)
  7. 7. Bridging Fault Copyright 2001, Agrawal & Bushnell Lecture 12: System Test e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (pass) T3 = 100 (fail) T4 = 110 (pass) Faulty circuit (OR bridge: a, c) Karnaugh map (red squares are faulty 1 outputs) a+c a+c
  8. 8. Fault Dictionary Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Fault Test syndrome t 1 t 2 t 3 t 4 No fault a 0 , b 0 , d 0 a 1 b 1 c 0 c 1 , d 1 , e 1 e 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 a 0 : Line a stuck- at-0 t i = 0, if Ti passes = 1, if Ti fails
  9. 9. Diagnosis with Dictionary Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Fault Test syndrome Diagnosis t 1 t 2 t 3 t 4 OR AND 0 1 0 1 e 0 OR-bridge (a,c) 0 0 1 0 b 1 OR NOR 1 1 1 1 c 1 , d 1 , e 1 , e 0 Dictionary look-up with minimum Hamming distance
  10. 10. Diagnostic Tree Copyright 2001, Agrawal & Bushnell Lecture 12: System Test T4 T1 T2 T3 No fault found T3 T2 b 1 a 1 c 1 , d 1 , e 1 a 0 , b 0 , d 0 e 0 c 0 Pass: t 4 =0 Fail: t 4 =1 a 0 , b 0 , d 0 , e 0 a 1 , c 1 , d 1 , e 1 OR AND OR bridge (a,c) OR NOR
  11. 11. System Test: PCB vs. SOC <ul><li>Tested parts </li></ul><ul><li>In-circuit test (ICT) </li></ul><ul><li>Easy test access </li></ul><ul><li>Bulky </li></ul><ul><li>Slow </li></ul><ul><li>High assembly cost </li></ul><ul><li>High reliability </li></ul><ul><li>Fast interconnects </li></ul><ul><li>Low cost </li></ul><ul><li>Untested cores </li></ul><ul><li>No internal test access </li></ul><ul><li>Mixed-signal devices </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test PCB* SOC** * Printed circuit board ** System on a chip
  12. 12. Core-Based Design <ul><li>Cores are predesigned and verified but untested blocks: </li></ul><ul><ul><li>Soft core (synthesizable RTL) </li></ul></ul><ul><ul><li>Firm core (gate-level netlist) </li></ul></ul><ul><ul><li>Hard core (non-modifiable layout, often called legacy core ) </li></ul></ul><ul><li>Core is the intellectual property of vendor (internal details not available to user.) </li></ul><ul><li>Core-vendor supplied tests must be applied to embedded cores. </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  13. 13. Partitioning for Test <ul><li>Partition according to test methodology: </li></ul><ul><ul><li>Logic blocks </li></ul></ul><ul><ul><li>Memory blocks </li></ul></ul><ul><ul><li>Analog blocks </li></ul></ul><ul><li>Provide test access: </li></ul><ul><ul><li>Boundary scan </li></ul></ul><ul><ul><li>Analog test bus </li></ul></ul><ul><li>Provide test-wrappers (also called collars) for cores. </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  14. 14. Test-Wrapper for a Core <ul><li>Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. </li></ul><ul><li>Test-wrapper provides: </li></ul><ul><ul><li>For each core input terminal </li></ul></ul><ul><ul><ul><li>A normal mode – Core terminal driven by host chip </li></ul></ul></ul><ul><ul><ul><li>An external test mode – Wrapper element observes core input terminal for interconnect test </li></ul></ul></ul><ul><ul><ul><li>An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core </li></ul></ul></ul><ul><ul><li>For each core output terminal </li></ul></ul><ul><ul><ul><li>A normal mode – Host chip driven by core terminal </li></ul></ul></ul><ul><ul><ul><li>An external test mode – Host chip is driven by wrapper element for interconnect test </li></ul></ul></ul><ul><ul><ul><li>An internal test mode – Wrapper element observes core outputs for core test </li></ul></ul></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  15. 15. A Test-Wrapper Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Wrapper test controller Scan chain Scan chain Scan chain to/from TAP from/to External Test pins Wrapper elements Core Functional core inputs Functional core outputs
  16. 16. Overhead of Test Access <ul><li>Test access is non-intrusive. </li></ul><ul><li>Hardware is added to each I/O signal of block to be tested. </li></ul><ul><li>Test access interconnects are mostly local. </li></ul><ul><li>Hardware overhead is proportional to: </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test (Block area) – 1/2
  17. 17. Overhead Estimate Copyright 2001, Agrawal & Bushnell Lecture 12: System Test Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K G  where 1 ≤ K ≤ 5 , and  ~ 0.5 . Assume that block area A is proportional to G , i.e., t is proportional to A 0.5 . Since test logic is added to each terminal t , Test logic added to terminals Overhead = ------------------------------------------------- ~ A –0.5 A
  18. 18. DFT Architecture for SOC Copyright 2001, Agrawal & Bushnell Lecture 12: System Test User defined test access mechanism (TAM) Module 1 Test wrapper Test source Test sink Module N Test wrapper Test access port (TAP) Functional inputs Functional outputs Func. inputs Func. outputs SOC inputs SOC outputs TDI TCK TMS TRST TDO Instruction register control Serial instruction data
  19. 19. DFT Components <ul><li>Test source : Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. </li></ul><ul><li>Test sink : Provides output verification using on-chip signature analyzer, or off-chip ATE. </li></ul><ul><li>Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. </li></ul><ul><li>Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers. </li></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
  20. 20. Summary <ul><li>Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. </li></ul><ul><li>Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. </li></ul><ul><li>SOC design for testability: </li></ul><ul><ul><ul><li>Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. </li></ul></ul></ul><ul><ul><ul><li>Provide external or built-in tests for blocks. </li></ul></ul></ul><ul><ul><ul><li>Provide test access via boundary scan and/or analog test bus. </li></ul></ul></ul><ul><ul><ul><li>Develop interconnect tests and system functional tests. </li></ul></ul></ul><ul><ul><ul><li>Develop diagnostic procedures. </li></ul></ul></ul>Copyright 2001, Agrawal & Bushnell Lecture 12: System Test
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