Shivakumar.A.NTECHNINICAL SKILLSElectronic Design Packages Xilinx ISE, Model SIM, Questa Sim.Programming Verilog HDL, Assembly level language, C, SystemLanguages/Packages Verilog, Perl Scripting Language.FPGA Xilinx FPGAs (Spartan3, Spartan 3E).Familiar Protocols RS232.Familiar OS Microsoft Windows.ACCOMPLISHMENTS 1. Presented an IEEE Technical Paper on “Wireless Traffic Service Communication Platform for Cars”. 2. Co-ordinated and participated in Technical events in College. 3. Won prizes at School Level Sports.PROFESSIONAL COURSES 1. Professional Development Course on VLSI Design at Sandeepani School of VLSI Design, Bangalore. 2. Professional Development Course on Advanced Verification Methodologies at Sandeepani School of VLSI Design, Bangalore. FPGA BASED PROJECTS AT SANDEEPANI 1) Designed and verified 8-bit UART using tools such as Xilinx ISE and ISIM on the Spartan-3 kit. The coding for UART was done using Verilog HDL. 2) Design and Implementation of VGA (Video Graphics Array) Controller for displaying colour spectrum and moving geometrical objects like triangle and square.
PROJECT WORK“Design and Verification of IEEE 754 Standard Floating Point Unit” atRV-VLSI Design Centre.Duration : 4 MonthsTeam Size: 4Language: VerilogTool Used: Synopsys Design Compiler C-2009.06.SP2 Arithmetic circuits form an important part of circuits in digital systems.With the remarkable progress in Very Large Scale Integration (VLSI) circuittechnology, many complex circuits, unthinkable yesterday have become easilyrealizable today. Algorithms that seemed impossible to implement now haveattractive implementation possibilities for the future. This means that not only theconventional computer arithmetic methods, but also the unconventional ones areworth investigation in new designs. In this project, an arithmetic unit based on IEEE standard for floating pointnumbers has been implemented. The arithmetic unit implemented has a 32-bitprocessing unit which allows various arithmetic operations such as addition,subtraction, multiplication, division on floating point numbers. Each operationcan be selected by a particular operation code. Synthesis of the unit has been doneusing Xilinx-ISE and verified on FPGA Spartan 3E board.EDUCATION Name of University/Board Specialization Year Pass Aggregate course/degree Out1 B.E VTU Electronics & 2010 61.88% Communication2 PUC Karnataka P.U PCME 2006 50.83% Board3 SSLC KSEB - 2004 85.76%
PERSONAL DETAILSFather’s name : A.NagarajDate of birth : 16-08-1988Nationality : IndianGender : MalePermanent Address : #13, 8th Main, 11th Cross, 3rd Phase, Girinagar, Bangalore, 560-085Email ID : firstname.lastname@example.orgContact No. : +91-9036014601Languages Known : Kannada, English, Hindi. DECLARATIONI hereby swear that all the information I have provided is true to the best of myknowledge. I also assure my complete dedication and hard work towards yourorganization if I am provided an opportunity.Date:Place: Bangalore (SHIVAKUMAR.A.N)