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Pdf lowpower pdf_iep_ppt_s kal

  1. 1. Microelectronics – Historical Perspective PRESENT ERA BEGINS WITH THE INVENTION OF SOLID STATE ELECTRONICS Point Contact Transistor invented in 1947 by Bardeen, Brattain, Schockly at Bell Telephone Laboratories Santiram Kal - Nobel prize in 1956 Department of Electronics & ECE Oxidation demonstrated Indian Institute of Technology in 1953 by Brattain and Kharagpur - 721302 Bardeen at Bell Telephone Laboratories Courtesy: Lucent Technologies, Bell Labs Innovations S. Kal, IIT-Kharagpur Microelectronics – Historical Perspective Microelectronics – Historical Perspective Integrated Circuit – 1958 Nobel Prize in 2000 Jack Kilby US Patent # 3,138,743 ICs in the early 1960s (four ICs in the early 1990s (over Filed Feb. 6, 1959 BJTs and several resistors) one million MOS transistors ) S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Why silicon for VLSI ? Crystallographic Planes Pure silicon has a relatively high electrical resistivity By adding ppm level of special impurities (dopant), resistivity can be lowered by many orders of magnitude There are two types of mobile carriers (electron & holes) in Si: Donor dopants will increase the electron concentration; Acceptor dopants will increase hole concentrations Good dielectrics such as SiO2 and Si3N4 can High performance semiconductor require easily be formed from silicon. defect-free crystal S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  2. 2. Si and Ge crystal has the three-dimensional diamond structure Viewing direction S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Silicon VLSI – Status & in VLSI Technology Trends Trends Silicon VLSI – Status & in VLSI Technology Trends Trends 10 um Modern CMOS Modern CMOS Moores Law Beginning of Beginning of Submicron CMOS Submicron CMOS 1 um Deep UV Litho Deep UV Litho 34 Years of Scaling History 90 nm in 2004 90 nm in 2004 Every generation 100 nm – Feature size shrinks by 70% – Transistor density doubles Presumed Limit Presumed Limit – Wafer cost increases by 20% to Scaling to Scaling – Chip cost comes down by 40% 10 nm Generations occur regularly – On average every 2.9 years over the past 34 years – Recently every 2 years 1 nm 1970 1980 1990 2000 2010 2020 S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Fundamental scaling limits for Technology Trends in MOS VLSI conventional MOS devices • Gate oxide thickness MOS gate dimensions • Junction depths reduced from 10 µm • Source-Drain Extension (SDE) • Gate lengths (1970’s) to 0.1 µm (2005) Unacceptable off-state leakage currents below 0.1 µm gate length Gate leakage for different toxide S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  3. 3. Technology Trends in MOS VLSI Power Management in VLSI Technology Total chip power dissipation (P) = Dynamic power dissipation (Pdyn) + Static power dissipation (Pstat) Pdyn = Cactive Vdd f clock 2 PStatic = N off W Vdd I leak 1 τi = = C g V dd / I on Power supply and threshold voltage Chip power and frequency trends fi scaling trends Vdd = power supply voltage τi = transistor intrinsic delay Cactive = total capacitance being fi = transistor intrinsic frequency switched during an average clock cycle Cg = gate capacitance per micron of transistor width for a MOSFET of gate Fclock = chip clock frequency length Lg Noff = No. of transistors that do not Ion = transistor saturation drive current, switch during an average clock cycle. which must be maximized to maximize fi W = average transistor width Ileak = total transistor leakage Off-state leakage vs L for 0.25 Active and standby power trends current ( A/ µm of transistor width) transistor with different Vth S. Kal, IIT-Kharagpur High Performance Technology Requirement Table (Data from 2003 ITRS) Low Power VLSI Technology Year Units 2003 2006 2009 2012 2015 2018 Lgate nm 45 28 20 14 10 7 Major Issues…….. EOT A 13 10 8 7 6 5 • Reduction of power supply Vdd V 1.2 1.1 1.0 0.9 0.8 0.7 • Reduction of device leakage currents Vth V 0.21 0.21 0.16 0.14 0.12 0.11 • Reduction of parasitic resistances and Parasitic Ohm capacitances 180 171 144 116 88 60 (RSD) µm Cg F/µm 7.4E-16 5.7E-16 5.8E-16 4.4E-16 3.5E-16 2.7E-16 Active power is set by circuit switching, P = CLoad Vcc2 f ( f is operating freq. and CLoad is the switching capacitance of the gate and wire load ) Cpara F/µm 2.4E-16 2.3E-16 1.9E-16 1.5E-16 1.2E-16 8.0E-17 4.0E-07 6.1E-07 7.7E-07 9.9E-07 2.6E-06 3.9E-06 Standby power results from junction and transistor sub- Psatic W/µm threshold source-to-drain leakage tD pS 30.24 18.92 12.06 7.47 4.45 2.81 (NAND) Equivalent Oxide Thickness (EOT) = Td / ( K/Kox) ; using high-K dielectric of thickness Td and relative dielectric constant K. Kox = 3.9 (SiO2) S. Kal, IIT-Kharagpur The fabrication process sequence of an Low Power VLSI Technology Integrated Circuit Solutions…….. • Use of proper isolation scheme to reduce parasitics • SOI Technologies • Complementary transistor structures • BiCMOS Technologies S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  4. 4. Crystal Growth VLSI Technology :Unit Processes • Wafer Cleaning • Oxidation • Lithography • Etching • Diffusion • Ion-implantation • Epitaxy • Deposition of thin films • Metallization • Bonding & Packaging S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Wafer Cleaning & Clean Room Contaminants Impact of Defects Killing Defects and Contaminations in VLSI S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur DEFECTS & CONTAMINATIONS DEFECTS & CONTAMINATIONS Impact of Contaminants on Device Parameters Parameters Hydro - Alkali metals Heavy Dopants Particulates Carbons,O2, metals N2 Clean Room Performance ( Yellow Room ) MOS drive X X X currents 1. Cleanliness class → Process area ≤ 10 Threshold, X X X → Service area ≤ 1000 Flatband Oxide leakage X X X 2. Temperature → 22 ± 0.5 º C Minority life X X X time 3. Humidity → 43 ± 5 % Diode leakage X X X X Junction break down - X X X X 4. Air quality → NO2 < 0.5 ppb Bipolar gain X X → SO2 < 0.5 ppb Crystal defects X X X → Hydrocarbon < 100 ppb Inter c - onnect X X open/short S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  5. 5. LITHOGRAPHY LITHOGRAPHY Photolithography is a process of transferring an image from a photographic mask to a resultant pattern on a wafer. A photosensitive polymer film is applied to the silicon wafer, dried and then exposed with the proper geometrical patterns through a photomask to UV light or other radiation and finally developed. Depending on the polymer used, either exposed or non- exposed area of the film is removed in the developing process. It requires resists, spinner, mask, mask-aligner, developer solution, baking ovens etc. Resists are made sensitive to a) UV light b) Electron beam c) X-rays d) Ion beams. Photolithography process using positive & negative resists S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur ETCHING Etching ETCHING is a process by which patterns are transferred by selective removal of un- masked portions of a layer. Pattern resist mask Two types of Etching: Etching thin 1. Wet Etching: Removal of unmasked layer is film done by selective liquid etchants. 2. Dry Etching: (Synonymous with plasma- Etching completed assisted etching) Here plasma is used in the form of low-pressure gaseous discharges to remove unmasked layer. Remove Examples: Plasma etching, Sputtering, RIE, resist mask IBE, RIBE etc. Etching (Anisotropic) Etching (Isotropic) S. Kal, IIT-Kharagpur ETCHING Thermal Oxidation Temp. 900-1200oC Si + SiO2 ⇒ SiO2 Si + 2 H2O ⇒ SiO2 + 2H2 O2 (or H2O) diffuses through SiO2 and reacts with Si at the interface to form SiO2. 1 μm of SiO2 formed consumes 0.44 μm of Si substrate Thin oxide growth (e.g. gate oxide) use O2 dry oxidation Subtractive Additive while thick oxide growth (e.g. field oxide) – use H2O. S. Kal, IIT-Kharagpur Wet oxidation S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  6. 6. Uneven surface topography with window Local Oxidation (LOCOS) oxidation Note surface topography S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur ION IMPLANTATION Ion Implantation Typically used to introduce dopants in to Ion implantation is a process of introduction semiconductor of ionized projectile atoms (impurity) in to targets (Si-substrates) with enough energy to penetrate beyond surface region of a single crystal substrate in order to change its electronic properties. Dopant atoms are vaporized, accelerated and directed at silicon substrate. Dopants enter the crystal lattice, collide with silicon atoms, gradually lose energy, finally coming to rest at some depth within the lattice S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Thermal Diffusion Predeposition + Drive-in To introduce dopants into semiconductor Half-Gaussian (Predeposition) profile after long To spread out the drive-in dopant profile ( Drive-in) Dopant dose conserved during drive-in Diffusion distance, ≅ Dt S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  7. 7. ION IMPLANTATION In present VLSI process pre-deposition diffusion is totally Physical vapor deposition replaced by ion implantation. Why? (Evaporation deposition) Implant Pre-deposition diffusion a. Control of doping Excellent Good profile 0 b. Shallow junction Min. 100 A No c. Max. doping > Solid solubility Solubility limit d. Control parameter Electrical Thermodynamic (Ion energy,dose, ( Temp, time ) ion current) e. Elec. conductivity Poor (requires Good annealing) f. Damages High (requires Low annealing) S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Physical vapor deposition Chemical vapor deposition (Sputtering deposition) Solid films are formed by chemical reaction taking place at the surface S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur EPITAXY Epitaxial Growth Epitaxy Epitaxy ( “epi” → upon + “taxis” → ordered ) is the ordered growth of thin single crystal layer upon a crystalline substrate Purity and crystal quality of epi-layer is better than in substrate Silicon epitaxy is used for bipolar devices and in CMOS –latch up prevention Processing temperature 950 – 1050 deg C Widely employed in compound semiconductor Require an ultra-clean Si surface prior to epi materials growth Bipolar IC application (1 – 3 μm in high speed Require deposition of Si at very high temperature digital circuits and 3 – 10 μm in linear circuits) for perfect crystallinity S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  8. 8. EPITAXY EPITAXY Molecular Beam Epitaxy Vapor Phase Epitaxy reactor system Features : Non – CVD vapor phase epitaxy via evapo- ration of material in ultra – high vacuum environment. By utilizing very low growth rates ( ≈ 1 μm/hour) can tailor doping profiles and composition on a monolayer scale. Growth temperature 400o – 800oC Background vacuum pressures ≈ 10-11 Torr Used for growth of Silicon, GaAs, AlGaAs, II – VI materials S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur EPITAXY MBE Reactor Configuration S. Kal, IIT-Kharagpur 6 Device Isolation Methods ISOLATION TECHNOLOGY Junction / Diode Isolation This method makes use of the fact that a reverse biased p – n junction has extremely low leakage current. Two regions on a semiconductor substrate are effectively isolated by applying a suitable reverse bias Junction isolation suffers from low breakdown voltage and unwanted parasitic capacitances which prevent it to be used for high frequency application S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  9. 9. ISOLATION TECHNOLOGY ISOLATION TECHNOLOGY Complete Dielectric Isolation Oxide Isolation This is basically a junction – dielectric isolation This isolation scheme produces several pockets on a where p-n junction isolation is combined with single crystal substrate surrounded by thin dielectric isolation produced by local oxidation of silicon layers This scheme produces isolated silicon islands, whose boarders are defined by a frame of locally thermally grown SiO2 that completely or partially penetrates the epitaxial layer. This technique has resulted in great reduction in the This scheme is specially suitable for high voltage physical dimension of the devices making it suitable applications and for nuclear-radiation environments for VLSI circuits. S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur ISOLATION TECHNOLOGY ISOLATION TECHNOLOGY LOCal Oxidation of Silicon (LOCOS) Isolation LOCOS Since oxidation consumes 44% as much silicon as it LOCOS has now become the standard isolation grows, the resultant oxide is partially recessed and has scheme in VLSI. It addresses both the isolation and a gradual step on to the field that forms Bird’s Head. parasitic device formation. Oxide encroachment in active area produces Bird’s Beak Formation of defects (dislocation) in silicon because of If the silicon is etched first, the field oxide can be made fully stress; Si3N4 causes Kooi effect or white ribbon effect i.e., it recessed, resulting a nearly planner surface. inhibits subsequent oxidation due to nitride patches Although recessed silicon with pad oxide offers isoplanar surface Pad oxide is used ⇒ get Bird’s Head, Bird’s Beak and reduces Bird’s Head, Bird’s Beak still remains. S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur ISOLATION TECHNOLOGY ISOLATION TECHNOLOGY Side Wall Masked Isolation ( SWAMI) Process Silicon on Insulator (SOI) Isolation Important consequence of Bird’s Beak from device Encasing of each device in an insulating material is an standpoint are —— ideal method of device isolation. Generically they are called Silicon on Insulator (SOI) o Encroachment reduces the active width of the device, reducing the amount of current that a transistor will SOI devices suffer from problems related to defect drive density. For that reason Si SOI technologies occupied small market such as radiation hardened devices o Field doping may increase the threshold voltage reducing its drive current – known as narrow channel One of the most promising SOI technique discussed effect. earlier is SIMOX, where a buried oxide is formed by implanting the wafer with 150 to 300 keV O+ at doses of about 2 X 1018 cm -2 SWAMI process reduces real estate waste. It redu- One of the first SOI methods, called dielectric isolation (DI). DI was developed to build high voltage telecomm- ces Bird’s Beak length unication ICs that required electrically isolated bi- directional switches S. Kal, IIT-Kharagpur S.KAL, IIT- KHARAGPUR S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  10. 10. ISOLATION TECHNOLOGY Contacts to Silicon Silicon on Insulator Isolation Technique Deep grooves are first etched in the surface of the wafer The wafer is oxidized and a very thick ( > 200 μm) poly-Si is deposited by conventional CVD The wafer is turned over and mechanically ground until the grooves penetrate through the wafer Finally the wafer is chemically polished and devices are fabricated in the isolated islands Problems are planarity, high cost, small isolation density S.KAL, IIT- KHARAGPUR S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Contacts to Silicon Resistance and Sheet Resistance Sheet Resistance (in ohms/square) RS = ρ /t when W = L R = RS L / W S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur BASE DIFFUESD RESISTOR RESISTOR CROSS SECTION RESISTOR GEOMETRIES S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  11. 11. CROSS SECTION SCHEMATIC OF AN INTEGRATED NPN TRANSISTOR CONCENTRATION PROFILE (INTRINSIC REGION) OF N-P-N TRANSISTOR I. ISOLATION EPITAXY: 5.2 μm, P, 5×1015/cc II. DEEP BURIED LAYER: SB, COLLECTOR 80 Kev, 1.5 × 1015 cm –2 III. EXTRINSIC EMITTER JUNCTION: 1.08 μm COLLECTOR BASE JUNCTION: 1.78 μm IV. INTRINSIC EPI / SUB JUNCTION: 9.42 μm BASE BASE WIDTH = 0.7 μm V. EXTRINSIC NET EPI WIDTH = 1.12 μm BASE S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Progress of transistor geometries from Planar to BIPOLAR PROCESS TECHNOLOGY 9 the Isoplanar II Process flow for an oxide isolated triple diffused bipolar technology S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur BIPOLAR PROCESS TECHNOLOGY BIPOLAR PROCESS TECHNOLOGY 11 Process flow for an oxide isolated triple diffused bipolar Process flow for an oxide isolated triple diffused bipolar technology technology Steps include:(a) buried layer formation, (b) epitaxial growth, (c) LOCOS patterning, (d) silicon recessing and channel stop implants, (e) local oxidation, (f) intrinsic base implant, (g) contact growth, (h) extrinsic base implant, (i) emitter and collector contact implant, and (j) metallization. S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  12. 12. BIPOLAR PROCESS TECHNOLOGY 24 BIPOLAR PROCESS TECHNOLOGY 25 Process flow for a self aligned double poly bipolar tech. Process flow for a self aligned double poly bipolar tech. After buried collector and A second oxide is deposited or isolation formation, a p+ grown and reactive ion etched layer of polysilicon is back down to substrate, leaving deposited. This layer is sidewall spacers on the base doped in-situ during contacts deposition The intrinsic base is implanted A layer of oxide is then through the hole deposited or grown on The second poly is deposited, the p+ poly doped n-type, and the emitter is The first poly is then driven patterned to open window Finally some of the base and in an active region emitter areas may be silicided to reduce series resistance The extrinsic base is diffused out of the first Base and emitter contacts align themselves automatically due poly to the surface topology without the need for a critical alignment step S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur BIPOLAR PROCESS TECHNOLOGY 31 Sidewall Base Contact Structure ( SICOS) Transistor 1. An n– collector is selec- tively grown epitaxially in the window and p-silicon is formed epitaxially 2. Base contacts are diffused laterally from the p+ poly 3. After oxide patterning, n+ poly is deposited and n+ poly contact emitter is formed Although many reports of SICOS have appeared, it is yet to be used in any mainstream process because of higher defects and leakage during selective epi growth S. Kal, IIT-Kharagpur MOS PROCESS TECHNOLOGY 9 MOS PROCESS TECHNOLOGY 10 Salicide NMOS Process Sequence Salicide NMOS Process Sequence After LOCOS process, thin Metal (Ti, Co) is deposited gate oxide is formed. Poly then annealed using RTP. – Si deposited and Metal film is allowed to patterned. Source/ Drain react with exposed active implanted regions of the devices and silicides are formed over Formation of sidewall gate and S/D contacts. Un- oxide spacers – the spacers is formed by reacted metal is removed depositing oxide layer selectively about 200 nm thick and etching it with anisotropic It is found that Ti thickness RIE. All the oxide in the showed to be one fifth of field will be cleared except the original junction depth at regions next to sharp in order to avoid excessive steps where deposited leakage current oxide is thickest. S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  13. 13. MOS PROCESS TECHNOLOGY 11 MOS PROCESS TECHNOLOGY 12 Salicide NMOS Process Sequence Hot Carrier Effects in Short-Channel MOS • In the reverse-bias drain-to-substrate junction, the electric field Glass passivation layer is may be quite high in the short-channel devices deposited, contacts are • Carriers that are injected into the depletion layer are formed and metallization accelerated by the high field, and some of them may gain follows enough energy to cause impact ionization. These carriers have higher energy than the thermal energy and are called hot The use of salicide carriers process can significantly • Holes – may terminate to substrate giving Isubs, may find their reduce the parasitic way to source lowering the source barrier to induce electron series resistance of the injection MOSFET • Drain-channel-source structure now acts as npn transistor with floating base and collector under avalance multiplication → Although TiSi2 is highly popular in SALICIDE process MoSi2 may be a better choice for NMOS application • The electrons may be attracted to +ve gate and may tunnel into because of its lower barrier height (0.55 eV) which oxide to produce gate current. Trapped electrons in gate oxide may change Vt provides a lower sp. contact resistance S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur MOS PROCESS TECHNOLOGY 13 MOS PROCESS TECHNOLOGY 17 Drain Engineering in MOS Lightly Doped Drain (LDD) MOS Process Lightly Doped Drain (LDD) structure Formation of oxide sidewall spacers Hot carrier effects are alleviated by LDD structure which reduces the drain field Source/ drain implant In LDD structure, the drain is formed by two implants, Silicide contact forma- one of these is self-aligned to the gate electrode and tion and metallization the other is self-aligned to an oxide spacer at the edge of the gate However, LDD structure Lateral dimension of oxide spacer ≈ 75 % of oxide adds additional parasi- thickness. In nMOS ; lighter drain → P, 10-13 cm-2 tic resistance dose and higher doped region → As, 10-15 cm-2 dose, LS ≈ 160 nm ≈ 0.16 μm An optimization process for the reachthrough doping, Thus electric field is reduced to an acceptable level depth and length must be carried out in which the tra- near the gate edge because of lighter drain. nsistor performance must be balanced against device reliability S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur BiCMOS TECHNOLOGY BiCMOS TECHNOLOGY Standard Buried Collector (SBC) BiCMOS Process BiCMOS is a technology that integrates both CMOS and bipolar device structures on the same chip 3D BiCMOS suffers from high collector resistance due to use of lightly doped n-well as collector CMOS can offer low power and high density to a digital IC, but it is usually slower than the emitter-coupled logic (ECL)-based ICs Bipolar transistors, on the other hand, can deliver large drive currents, operate with small logic swings, and have high noise immunity; however, they exhibit high power consumption, poor density, and limited circuit options. BiCMOS offer the benefits of both bipolar and CMOS circuits By appropriate trading off the characteristics of each SBC BiCMOS process uses a buried n+ layer under the technology, speed and power can be balanced n-well This desirable result, however, is attained with the penalty of Buried n+ layer is first formed in p-substrate by adding more process complexity arsenic implant and capped with 2 μm thick n-epi layer S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  14. 14. BiCMOS TECHNOLOGY BiCMOS TECHNOLOGY Twin-Well BiCMOS Process Twin-Well BiCMOS Process Earlier BiCMOS processes suffer from low packing density due to p- substrate doping level and large spacing between collectors to prevent punch through Raising doping level would increase collector-to- substrate capacitance P-type epi-layer is to be counter doped to form n-well regions (p-MOS) which cause process control difficulties Standard n-MOS and p-MOS implant to set MOS device threshold Twin-well BiCMOS process improves bipolar packing Pattern contact plug and high dose phosphorus implant for npn density by self-aligning buried p-layer to the buried collector n+ region at the cost of higher collector-to-substrate capacitance Form gate oxide and deposit n+ poly layer Form electrodes for MOS and poly-Si emitter contact for BJT S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur BiCMOS TECHNOLOGY BiCMOS TECHNOLOGY High Performance Twin-well Sub-micron BiCMOS High Performance Sub-micron Trench-isolated BiCMOS Features: Double level metal interconnect, LDD structure Local interconnect without need for contact holes and metal Features: Trench isolation borders Self-aligned silicided gates, emitters for low Sheet Res. Salicide process in which gates, emitters and diffusions are LDD n-MOS and p-MOS structure silicides in a self-aligned manner to reduce Sheet Res. Double level metal interconnect Self-aligned p+ ext. base S. Kal, IIT-Kharagpur S. Kal, IIT-Kharagpur Future MOS for 21st Century Future MOS for 21st Century Dynamic Threshold Voltage MOS Inverter SOI MOS Structure Serious complications for circuit design due to floating body effect. • Si1 xGex under compressive - strain improves hole mobility over Si. For low supply voltage operation ( < 0.6 V), a dynamic • Valence band offset between threshold MOS device (DTMOS) is proposed by connecting Si and Si1 xGex localizes the - the gate to the well, which causes the threshold voltage of hole inversion charge away the device to be lowered during switching thereby from the SiO2/Si interface, increasing the transistor drive current Si1 xGex channel MOS structure - which reduces the effects of surface roughness scattering. S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR
  15. 15. Conclusions Conclusions Traditional scaling methods will not continue • Historical perspective beyond 0.10 µm device technologies Fundamental limitations in…. • Technology Trends • SiO2 scaling due to tunneling current • Low power management in VLSI • SDE junction depths due to large increase in external resistance • Basics of IC Technology • Well engineering due to leakage constraints • Bipolar VLSI processes No clear device architecture for continuing the • MOS VLSI Processes present performance trends Aggressive exploration continues…. • BiCMOS VLSI Processes • High dielectric constant materials • Future MOS structure for 21st century • Developing a way to reduce SDE resistance S. Kal, IIT-Kharagpur S. Kal, IIT-KharagpurS.KAL, IIT - KHARAGPUR