Router architectures in no c


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Routers in Network on Chip

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Router architectures in no c

  1. 1. Router Architectures In Network on Chip (NoC) Sharvari Malunjkar Colorado State University, fort Collins 830144176
  2. 2. Routers NoC Routers: Noc (Network on Chip)is Paradigm for SoC (System on Chip). NoC has processors and memories, IP blocks which are connected to routers. Router makes the routing decisions with the help of routing algorithms.
  3. 3. Classification of Router Architecture
  4. 4. Routers Classified with Routing Algorithms : Oblivious Router : Oblivious Routing algorithms are the one in which routing is done without information of traffic amount and condition of the network. Routers designed with the same algorithms are Oblivious Routers. Adaptive Router : It is dynamic routing, the route calculation is based on shortest path which gets modified depending on the routing conditions.
  5. 5. Oblivious Router Architectures       Virtual Channel Router Æthereal Router MANGO Router RASoC Router Xpipes Router Proteo Router
  6. 6. Virtual Channel Router Architecture  Wormhole routing is used.  Crossbar switch is present.  Arbitration Unit (AU) decides the channel to be advanced from virtual channels. (SLIP arbiter)  For better performance architecture was modified : • Round robin Arbiter is used. • To make arbitration conflict free id system to VCs is used. • The multiplexing of VCs before crossbar is omitted to remove conflicts
  7. 7. Æthereal Router Architecture Two types of architectures depending on programming models are present. Namely GS-BE distributed programing architecture and GS-BE centralized programing architecture. GS-BE distributed programing architecture  BES (Best effort service) Arbiter is used.  Header passing unit (HPU) is bypassed due to absence of header.  Routing is done by RCU (Reconfiguration Unit) with respect to STU (Slot Table unit)  BES packets are translated to read/write which are then transmitted through crossbar switch  To make architecture contention free registers may be used instead of SRAM.
  8. 8. Æthereal Router Architecture GS- BE Centralized Programming Architecture  From previous design this design becomes simple having BES queue, GS queue, Arbiter and controller, HPU and crossbar switch.  Arbiter becomes simple , controller can be used for its operations. GS-BE with distributed programming is scalable and GS router with centralized programming is faster, cheaper
  9. 9. MANGO Router (Message-Passing Asynchronous Network-onChip providing Guaranteed services through OCP interfaces) Architecture MANGO Router has two Routers GS(Guaranteed service) and BE (Best Effort) Routers. GS Router:  VC control channel is used to avoid blocking.  Link arbitration is used  Routing from any input to any VC buffer is done with the help of switching module.  Arbitration may be removed to simplify design and saving area and latency.  Credit based VC control scheme improves the performance of the router.
  10. 10. BE Router:  Packets are variable in length. Control bits are used to detect the last flit.  Packet coherency is maintained as the access to input port is maintained till the last flit transmission. To avoid deadlocks XY routing is used. Due to non blocking GS router gives better performance.
  11. 11. RASoC Router Architecture Router architecture mainly consists of input channel module and output channel module.  Input channel module:  IFC block has logic for translation between handshake and FIFO flow.  IB is buffer stores the packet when can not be forwarded.  IC performs routing function using RIB(Routing information bits), header.  IRS sends the packets after receiving command from output.  Output Channel Module: • OC (Output controller) selects request from input. • Grant signal is sent by selected request by ODS (Output data switch) and ORS (Output Read Switch) • OFC (Output Flow control) used for connections.
  12. 12. Xpipes Router Architecture  Wormhole flow control is used.  Use of source routing.  Deterministic routing is done so simple switch is present for transmission.  Routing decision is taken before forwarding of packets.  Architecture is similar to virtual channel router.
  13. 13. Proteo Router  Sub networks are present.  Two routers Initiator and target routers are present.  Destination tag routing method is used.  Comparison of destination address with current address decides the flit transmission by greeting block.
  14. 14. Dynamic Router Architecture  DyXY Router  DyAD Router  Both the routers take congestion condition into consideration.  Deadlock free and live lock free behavior can be obtained with the help of these router architectures.
  15. 15. DyXY Router  DyXY routing takes into consideration congestion condition of the network.  With respect to up, down, left, right routers the data lines, request lines and signal lines are present.  Input arbiter referring to history buffer proceeds the requests to input buffer.  Controller determines the shortest path depending on the stress value which is the congestion condition representing value.
  16. 16. DyAD Router  DyAD architecture combines the advantages of deterministic and adaptive routing.  Depending on congestion condition (congestion flag) the routing is switched between deterministic and adaptive routing.  OE-fixed algorithm which is a deterministic version of even odd routing is used.  Buffering of each input before transmission is done by input controller.  Address decoder analyzes the arrived flits.  Port controller sends connection requests.  Mode controller monitors the neighboring congestion condition to decide routing type.
  17. 17. Performance Characteristics based Router Architecture      Congestion Aware Router Asynchronous on chip Router Low latency Router High Throughput Router Power and Area efficient Router
  18. 18. Congestion Aware Router  For various traffic conditions the router is designed with the help of dynamic input arbitration and adaptive path selection.  For mesh and diagonally linked mesh better performance is obtained.  NePA architecture is used for the design.  These routers enhance latency and throughput.
  19. 19. Asynchronous on chip Router  This router architecture is similar to virtual channel router architecture with priority based algorithm for scheduling which differentiate between GS and BE traffics.  Unused bandwidth is allocated to BE without affecting the performance of GS.  So Better worst case utilization of network resources.  Results into high Qos as HOL (Head of blocking) problem is solved and enough memory space is now available for traffic management.
  20. 20. Low latency Router  Routing and arbitration logic overheads are removed from critical path which minimizes the cycle time and latency. Apart from this router architecture is similar to virtual channel router architecture.  Dynamic cycle improvement is done increases the router’s limited buffering resource.  Grid based distributed clocking scheme is used to ensure the skew present in the adjacent routers is minimum.
  21. 21. High Throughput Router  IBR (Input Buffer Router), OBR (Output Buffer Router) handle buffering.  OBR need speedup equal to input ports for direct implementation of router.  So Distributed Shared Buffer is used, result into low power overhead and negligible degradation.  Efficient pipeline and flow control help DSB router to have high throughput.
  22. 22. Power and Area efficient Router  Power consumption and Area overhead depend on router buffers.  To improve them resource sharing is done.  To enhance the performance Virtual channel buffer sharing is done.  Optimization is done with the help of utilizing idle buffers rather than increasing number or size of buffers for high throughput.  FIFO’s, parameterized components, input –output controllers, buffer allocation, output crossbar and computation elements are used for the design of the router.  This router can be used in 3D NoC .
  23. 23. Conclusion  Depending on routing algorithms and performance characteristics the router architecture are proposed in detail.  Low latency, High throughput ,low power consumption and low congestion can be possible with the architectures proposed above.  Depending on the need of application, the routers can be used for the design of Network on chip.
  24. 24. THANK YOU.