Cmos digital integrated_circuits


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Cmos digital integrated_circuits

  1. 1. Physical and Materials ConstantsBoltzmanns constant k 1.38 x 10-23 J/KElectron charge q 1.6 x 10-19 CThermal voltage kT/q 0.026 V (at T= 300 K)Energy gap of silicon (Si) Eg 1.12 eV (at T = 300 K)Intrinsic carrierconcentration of silicon (Si) ni 1.45 x 1010 cm73 (at T = 300 K)Dielectric constantof vacuum 60 8.85 x 10-14 F/cmDielectric constantof silicon (Si) ESi 11.7 x O F/cmDielectric constantof silicon dioxide (SiO2 ) 6.x 3.97 x EO F/cm Commonly Used Prefixes for Units giga G 109 mega M 106 kilo k 103 milli m 10-3 In 10-6 micro nano n 10-9 pico p 10-12 femto f 10-15
  2. 2. second editionCMO SDIGITALINTE GRATE DCI RCUITSAnalysis and DesignSUNG-MO (STEVE) ANGUniversity of Illinois at Urbana- ChampaignYUSUF LEBLEBIGIWorcester Polytechnic InstituteSwiss Federal Institute of Technology-Lausanne U McGraw-Hill.* Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco St. Louis Bangkok Bogota Caracas Lisbon London Madrid Mexico City Milan New Delhi Seoul Singapore Sydney Taipei Toronto
  3. 3. Copyrighted MaterialMcGmlfl-Hill Higher Education sz A Division off1tt M:Ora•·H ill OmtpanicsCMOS DIGITAL lNTEORATEO CIRCUITS: ANALYSIS ANDD€SIGNTliJRD EDITIONPi•blislled by McGr:to·HiU. a businCS.!unil o(The McOrnw·Hill Comp:mic s. Inc.. 122 I AvenueoftheAtnericas, New YO•k, NY 10020. Copyrighl() 2003. 1999, 1996 by The McOrsw-HillCompanies, loc. All rights �!laved. No Jllllt of lhis publkation muy be reproduooc.l or di�tribotedin My form or by any means. or stored in l.ll.iatilbi•St Of teltleval systenl. without the prior wr inwconsent o(The McCr-.1w·Hill Co.npanks. Inc .. including. but oot limih!d t(), in any nctviotk or ()(herelectronic SlorlgC or I.Jnnsm•ssion. ()r bll);ui�M for distance lenming.Some: ;uKiUaries, inc-luding electronic and prim compoDCnts. nl:l) n(lt bt ;h;lll:d)IC to eusaomcrsouiSide the United Stutt5.Tbi$ boot Is r-imed on acid·froc PQper.Jntcmational 2 J4 56 7 8 90 QPF/QP109 8765 4 3Po n�oestic 2 3-1 56 7 8 9 0 QPF/QPF 0 98 7 6 S 4 3ISBN G-07-246053-9ISBN �-119644-7(1SE)PuhU:Ulet: Ell:.aMthA. JonesSenior t.])OOIIOrint,edil(lr: Crul;�ePmllwltDevelopmenlal editor: Mklr�:.llt: 1... f.l(»fUrdwfiExecutive marketing manager: John UlmnemtKI!erSenior project manager: Ro.�e KoosProdue1ion super i.SQf: S/t crry {... KcmeMedia projce1manager. Jodi K. & 1 0nrt. t1 ..Senior media technol�y producer: Plt llllp MNkCoordnat r of( liiOce design; Rick D. NOt:! i o ltltCOver desig ner: Sht!li(JitBorreuCo•c:r DtCAlt/Jm mif:Jt�rtN.:esSI)r cltlp phologmplt, �nesy /tfidwellkn-idrm•. fh,it/(J Swte UnlwrsityNmiorwl 1/iglt Magnetir; f t:lr/ Lulwrow r. v i "Composi1or: lmemctRoe Compositim• CorpomtiQ1tJYptft�te:: JOI121iJ�W RomanPrinter: Qu(becQr %rid ftlirfit:M, PA Library orCong.ras Cnllll(l�ln�·ln-Publkation OacaKang, Sung·�IO, 1945- CMOS digital imeyatcd crcuits : analysis :md d�gn I Sung-Mo (Sit�·c) Kang. Yusur i lLeblebicL -3rd cd. p. c1n. lnc:ludes biblk>y.tphie:tl references and indc:.x. lSBN 0-07-24605�9- ISDN 0.00-119644-7 (ISE) 1. Metal oxide. semicondoctors. Complement.vy. 2. Digi1;d�rnted circuits. t Ublebid,Yu:suf. U. TiOe.TK7871.99.M44 K36 2003621.395-dcll 2002026558 CIPlNTERNATIONALEDITION ISBN 0-07-119644-7Cop)ri,a.hl 0 2003. Exclusi� tighLS byThe McGraw-Hill CompaniQ.. Inc., for mOlnuf;u.:ture ;tndexpcJrL lnil boot cannot be rt·C.XJIOC1cd from the ooontry towtaicb it i s llold by Mc.:Gr;,w.liill.The lntemation;•l Edilion1s nOi tlilil:•ble ln Nanh An..eric Copyrighted Material
  4. 4. CONTENTSPREFACE xi1 INTRODUCTION 1 1.1 Historical Perspective 1 1.2 Objective and Organization of the Book 5 1.3 A Circuit Design Example 82 FABRICATION OF MOSFETs 20 2.1 Introduction 20 2.2 Fabrication Process Flow: Basic Steps 21 2.3 The CMOS nWell Process 29 2.4 Layout Design Rules 37 2.5 Full-Custom Mask Layout Design 40 References 44 Exercise Problems 453 MOS TRANSISTOR 47 3.1 The Metal Oxide Semiconductor (MOS) Structure 48 3.2 The MOS System under External Bias 52 3.3 Structure and Operation of MOS Transistor (MOSFET) 55 3.4 MOSFET Current-Voltage Characteristics 66 3.5 MOSFET Scaling and Small-Geometry Effects 81 3.6 MOSFET Capacitances 97 References 110 Exercise Problems 111
  5. 5. vi. 4 MODELING OF MOS TRANSISTORS USING SPICE 117Contents 4.1 Basic Concepts 118 4.2 The LEVEL 1 Model Equations 119 4.3 The LEVEL 2 Model Equations 123 4.4 The LEVEL 3 Model Equations 130 4.5 Capacitance Models 131 4.6 Comparison of the SPICE MOSFET Models 135 References 137 Appendix: Typical SPICE Model Parameters 138 Exercise Problems 139 5 MOS INVERTERS: STATIC CHARACTERISTICS 141 5.1 Introduction 141 5.2 Resistive-Load Inverter 149 5.3 Inverters with n-Type MOSFET Load 160 5.5 CMOS Inverter 172 References 190 Exercise Problems 191 6 MOS INVERTERS: SWITCHING CHARACTERISTICS AND INTERCONNECT EFFECTS 196 6.1 Introduction 196 6.2 Delay-Time Definitions 198 6.3 Calculation of Delay Times 200 6.4 Inverter Design with Delay Constraints 210 6.5 Estimation of Interconnect Parasitics 222 6.6 Calculation of Interconnect Delay 234 6.7 Switching Power Dissipation of CMOS Inverters 242 References 250 Appendix: Super Buffer Design 251 Exercise Problems 254 7 COMBINATIONAL MOS LOGIC CIRCUITS 259 7.1 Introduction 259 7.2 MOS Logic Circuits with Depletion nMOS Loads 260 7.3 CMOS Logic Circuits 274 7.4 Complex Logic Circuits 281 7.5 CMOS Transmission Gates (Pass Gates) 295 References 305 Exercise Problems 306
  6. 6. 8 SEQUENTIAL MOS LOGIC CIRCUITS 312 vii 8.1 Introduction 312 Contents 8.2 Behavior of Bistable Elements 314 8.3 The SR Latch Circuit 320 8.4 Clocked Latch and Flip-Flop Circuits 326 8.5 CMOS D-Latch and Edge-Triggered Flip-Flop 334 Appendix: Schmitt Trigger Circuit 341 Exercise Problems 3459 DYNAMIC LOGIC CIRCUITS 350 9.1 Introduction 350 9.2 Basic Principles of Pass Transistor Circuits 352 9.3 Voltage Bootstrapping 365 9.4 Synchronous Dynamic Circuit Techniques 368 9.5 High-Performance Dynamic CMOS Circuits 378 References 395 Exercise Problems 39610 SEMICONDUCTOR MEMORIES 402 10.1 Introduction 402 10.2 Read-Only Memory (ROM) Circuits 405 10.3 Static Read-Write Memory (SRAM) Circuits 417 10.4 Dynamic Read-Write Memory (DRAM) Circuits 435 References 447 Exercise Problems 44711 LOW-POWER CMOS LOGIC CIRCUITS 451 11.1 Introduction 451 11.2 Overview of Power Consumption 452 11.3 Low-Power Design Through Voltage Scaling 463 11.4 Estimation and Optimization of Switching Activity 474 11.5 Reduction of Switched Capacitance 480 11.6 Adiabatic Logic Circuits 482 References 489 Exercise Problems 49012 BiCMOS LOGIC CIRCUITS 491 12.1 Introduction 491 12.2 Bipolar Junction Transistor (BJT): Structure and Operation 494
  7. 7. viii 12.3 Dynamic Behavior of BJTs 509 12.4 Basic BiCMOS Circuits: Static Behavior 516Contents 12.5 Switching Delay in BiCMOS Logic Circuits 519 12.6 BiCMOS Applications 524 References 529 Exercise Problems 530 13 CHIP INPUT AND OUTPUT (O) CIRCUITS 534 13.1 Introduction 534 13.2 ESD Protection 535 13.3 Input Circuits 538 13.4 Output Circuits and L(di/dt) Noise 543 13.5 On-Chip Clock Generation and Distribution 549 13.6 Latch-Up and Its Prevention 555 References 562 Exercise Problems 563 14 VLSI DESIGN METHODOLOGIES 566 14.1 Introduction 566 14.2 VLSI Design Flow 569 14.3 Design Hierarchy 570 14.4 Concepts of Regularity, Modularity and Locality 573 14.5 VLSI Design Styles 576 14.6 Design Quality 586 14.7 Packaging Technology 589 14.8 Computer-Aided Design Technology 592 References 593 Exercise Problems 594 15 DESIGN FOR MANUFACTURABILITY 598 15.1 Introduction 598 15.2 Process Variations 599 15.3 Basic Concepts and Definitions 601 15.4 Design of Experiments and Performance Modeling 608 15.5 Parametric Yield Estimation 615 15.6 Parametric Yield Maximization 621 15.7 Worst-Case Analysis 622 15.8 Performance Variability Minimization 628 References 633 Exercise Problems 633
  8. 8. 16 DESIGN FOR TESTABILITY 638 ix 16.1 Introduction 638 Contents 16.2 Fault Types and Models 638 16.3 Controllability and Observability 642 16.4 Ad Hoc Testable Design Techniques 644 16.5 Scan-Based Techniques 646 16.6 Built-In Self Test (BIST) Techniques 648 16.7 Current Monitoring IDDQ Test 651 References 653 Exercise Problems 653INDEX 655
  9. 9. ABOUT THE AUTIORSSung-Mo (Steve) Kang received the Ph.D. degree in electrical engineering from theUniversity of California at Berkeley. He has worked on CMOS VLSI design at AT&TBell Laboratories at Murray Hill, N.J. as supervisor and member of technical staff ofhigh-end CMOS VLSI microprocessor design. Currently, he is professor and head of thedepartment of electrical and computer engineering at the University of Illinois at Urbana-Champaign. He was the founding editor-in-chief of the IEEE Transactions on Very LargeScale Integration (VLSI) Systems and has served on editorial boards of several IEEE andinternational journals. He has received a Humboldt Research Award for Senior USScientists, IEEE Graduate Teaching Technical Field Award, IEEE Circuits and SystemsSociety Technical Achievement Award, SRC Inventor Recognition Awards, IEEE CASDarlington Prize Paper Award and other best paper awards. He has also co-authoredDesignAutomationforTiming-DrivenLayout Synthesis, Hot- Carrier ReliabilityofMOSVLSI Circuits, Physical Design for Multichip Modules, and Modeling of ElectricalOvertstress in Integrated Circuits from Kluwer Academic Publishers, and Computer-Aided Design of Optoelectronic Integrated Circuits and Systems from Prentice Hall.Yusuf Leblebici received the Ph.D. degree in electrical and computer engineeringfrom the University of Illinois at Urbana-Champaign. He was a visiting assistantprofessor of electrical and computer engineering at the University of Illinois at Urbana-Champaign, associate professor of electrical and electronics engineering at IstanbulTechnical University, and invited professor of electrical engineering at the SwissFederal Institute of Technology in Lausanne, Switzerland. Currently, he is an associateprofessor of electrical and computer engineering at Worcester Polytechnic Institute.Dr. Leblebici is also a member of technical staff at the New England Center forAnalog and Digital Integrated Circuit Design. His research interests include high-performance digital integrated circuit architectures, modeling and simulation of semi-conductor devices, computer-aided design of VLSI circuits, and VLSI reliability analy-sis. He has received a NATO Science Fellowship Award, has been an Horiors Scholarof the Turkish Scientific and Technological Research Council, and has received the Young Scientist Award of the same council. Dr. Leblebici has co-authored about fifty technical papers and two books.
  10. 10. PREFACEComplementary metal oxide semiconductor (CMOS) digital integrated circuits are theenabling technology for the modern information age. Because of their intrinsic featuresin low-power consumption, large noise margins, and ease of design, CMOS integratedcircuits have been widely used to develop random access memory (RAM) chips,microprocessor chips, digital signal processor (DSP) chips, and application- specificintegrated circuit (ASIC) chips. The popular use of CMOS circuits will grow with theincreasing demands for low-power, low-noise integrated electronic systems in thedevelopment of portable computers, personal digital assistants (PDAs), portable phones,and multimedia agents. Since the field of CMOS integrated circuits alone is very broad, it is conventionallydivided into digital CMOS circuits and analog CMOS circuits. This book is focused onthe CMOS digital integrated circuits. At the University of Illinois at Urbana-Champaign,we have tried some of the available textbooks on digital MOS integrated circuits for oursenior-level technical elective course, ECE382 - Large!ScaleIntegratedCircuitDesign.Students and instructors alike realized, however, that-there was a need for a new book withmore comprehensive treatment of CMOS digital circuits. Thus, our textbook project wasinitiated several years ago by assembling our own lecture notes. Since 1993, we have usedevolving versions of this material at the University of Illinois at Urbana-Champaign, atIstanbul Technical University and at the Swiss Federal Institute of Technology inLausanne. Both authors were very much encouraged by comments from their students,colleagues, and reviewers. The first edition of CMOS Digital Integrated Circuits:Analysis and Design was published in late 1995.
  11. 11. xii Soon after publishing the first edition, we saw the need for updating the it to reflect many constructive comments from instructors and students who used the textbook, toPreface include the topic of low-power circuit design and provide more rigorous treatment of interconnects in high-speed circuit design as well as the deep submicron circuit design issues. We also felt that in a very rapidly developing field such as CMOS digital circuits, the quality of a textbook can only be preserved by timely updates reflecting the current state-of-the-art. This realization has led us to embark on the extensive project of revising our work, to reflect recent advances in technology and in circuit design practices. This book, CMOS Digital Integrated Circuits: Analysis and Design, is primarily intended as a comprehensive textbook at the senior level and first-year graduate level, as well as a reference for practicing engineers in the areas of integrated circuit design, digital design, and VLSI. Recognizing that the area of digital integrated circuit design is evolving at an increasingly faster pace, we have made every.possible effort to present up- to-date materials on all subjects covered. This book contains sixteen chapters; and we recognize that it would not be possible to cover rigorously all of this material in one semester. Thus, we would propose the following based on our teaching experience: At the undergraduate level, coverage of the first ten chapters would constitute sufficient material for a one-semester course on CMOS digital integrated circuits. Time permitting, some selected topics in Chapter 11, Low-Power CMOS Logic Circuits, Chapter 12, BiCMOS Logic Circuits and Chapter 13, Chip Input and Output (1/O) Circuits can also be covered. Alternatively, this book can be used for a two-semester course, allowing a more detailed treatment of advanced issues, which are presented in the later chapters. At the graduate level, selected topics from the first eleven chapters plus the last five chapters can be covered in one semester. The first eight chapters of this book are devoted to a detailed treatment of the MOS transistor with all its relevant aspects; to the static and dynamic operation principles, analysis and design of basic inverter circuits; and to the structure and operation of combinational and sequential logic gates. The issues of on-chip interconnect modeling and interconnect delay calculation are covered extensively in Chapter 6. Indeed, Chapter 6 has been significantly extended to provide a more complete view of switching characteristics in digital integrated circuits. The coverage of technology-related issues has been complemented with the addition of several color plates and graphics, which we hope will also enhance the educational value of the text. A separate chapter (Chapter 9) has been reserved for the treatment of dynamic logic circuits which are used in state-of- the-art VLSI chips. Chapter 10 offers an in-depth presentation of semiconductor memory circuits. Recognizing the increasing importance of low-power circuit design, we decided to add a new chapter (Chapter 11) on low-power CMOS logic circuits. This new chapter provides a comprehensive coverage of methodologies and design practices that are used to reduce the power dissipation of large-scale digital integrated circuits. BiCMOS digital circuit design is examined in Chapter 12, with a thorough coverage of bipolar transistor basics. Considering the on-going use of bipolar circuits and BiCMOS circuits, we believe that at least one chapter should be allocated to cover the basics of bipolar transistors. Next, Chapter 13 provides a clear insight into the important subject of chip I/O design. Critical issues such as ESD protection, clock distribution, clock buffering, and latch-up phenom- enon are discussed in detail. Design methodologies and tools for very large scale integration (VLSI) are presented in Chapter 14. Finally, the more advanced but very
  12. 12. important topics of design for manufacturability and design for testability are covered in xiiiChapters 15 and 16, respectively, The authors have long debated the coverage of nMOS circuits in this book. We have Prefacefinally concluded that some coverage should be provided for pedagogical reasons.Studying nMOS circuits will better prepare readers for analysis of other field effecttransistor (FET) circuits such as GaAs circuits, the topology of which is quite similar tothat of depletion-load riMOS circuits. Thus, to emphasize the load concept, which is stillwidely used in many areas in digital circuit design, we present basic depletion-loadnMOS circuits along with their CMOS counterparts in several places throughout thebook. Although an immense amount of effort and attention to detail were expended toprepare the camera-ready manuscript, this book may still have some flaws and mistakesdue to erring human nature. The authors would welcome and greatly appreciate sugges-tions and corrections from the readers, for the improvement of the technical content aswell as the presentation style.Acknowledgements for the First EditionOur colleagues have provided many constructive comments and encouragement for thecompletion of the first edition. Professor Timothy N. Trick, former head of the depart-ment f electrical and computer engineering at the University of Illinois at Urbana-Champaign, has strongly supported our efforts from the very beginning. The appointmentof Sung-Mo Kang as an associate in the Center for Advanced Study at the University ofIllinois at Urbana-Champaign helped to start the process. Yusuf Leblebici acknowledges the full support and encouragement from the depart-ment of electrical and electronics engineering at Istanbul Technical University, where heintroduced a new digital integrated circuits course based on the early version of this bookand received very valuable feedback from his students. Yusuf Leblebici also thanks theETA Advanced Electronics Technologies Research and Development Foundation atIstanbul Technical University for their generous support. Professor Elyse Rosenbaum and Professor Resve Saleh used the early versions of themanuscript as the textbook for ECE382 at Illinois and provided many helpful commentsand corrections which have been fully incorporated with deep appreciation. ProfessorElizabeth Brauer, currently at Northern Arizona University, has also done the same at theUniversity of Kentucky. The authors would like to express sincere gratitude to Professor Janak Patel of theUniversity of Illinois at Urbana-Champaign for generously mentoring the authors inwriting Chapter 16, Designfor Testability. Professor Patel has provided many construc-tive comments and many of his expert views on the subject are reflected in this chapter.Professor Prith Banerjee of Northwestern University and Professor Farid Najm of theUniversity of Illinois at Urbana-Champaign also provided many good comments. Wewould also like to thank Dr. Abhijit Dharchoudhury for his invaluable contribution toChapter 15, Designfor Manufacturability. Professor Duran Leblebici of Istanbul Technical University, who is the father of thesecond author, reviewed the entire manuscript in its early development phase, andprovided very extensive and constructive comments, many of which are reflected in thefinal version. Both authors gratefully acknowledge his support during all stages of this
  13. 13. xiv venture. We also thank Professor Cem Goknar of Istanbul Technical University, who offered very detailed and valuable comments on Design for Testability, and ProfessorPreface Ugur Qilingiroglu of the same university, who offered many excellent suggestions for improving the manuscript, especially the chapter on semiconductor memories. Many of the authors former and current students at the University of Illinois at Urbana-Champaign also helped in the preparation of figures and verification of circuits using SPICE simulations. In particular, Dr. James Morikuni, Dr. Weishi Sun, Dr. Pablo Mena, Dr. Jaewon Kim, Mr. Steve Ho and Mr. Sueng-Yong Park deserve recognition. Ms. Lilian Beck and the staff members of the Publications Office in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign read the entire manuscript and provided excellent editorial comments. The authors would also like to thank Dr. Masakazu Shoji of AT&T Bell Laboratories, Professor Gerold W. Neudeck of Purdue University, Professor Chin-Long Wey of Michigan State University, Professor Andrew T. Yang of the University of Washington, Professor Marwan M. Hassoun of Iowa State University, Professor Charles E. Stroud of the University of Kentucky, Professor Lawrence Pileggi of the University of Texas at Austin, and Professor Yu Hen Hu of the University of Wisconsin at Madison, who read all or parts of the manuscript and provided many valuable comments and encouragement. The editorial staff of McGraw-Hill has been an excellent source of strong support from the beginning of this textbook project. The venture was originally initiated with the enthusiastic encouragement from the previous electrical engineering editor, Ms. Anne (Brown) Akay. Mr. George Hoffman, in spite of his relatively short association, was extremely effective and helped settle the details of the publication planning. During the last stage, the new electrical engineering editor, Ms. Lynn Cox, and Mr. John Morriss, Mr. David Damstra, and Mr. Norman Pedersen of the Editing Department were superbly effective and we enjoyed dashing with them to finish the last mile. Acknowledgements for the Second Edition The authors are truly indebted to many individuals who, with their efforts and their help, made the second edition possible. We would like to thank Dr. Wolfgang Fichtner, President and CEO of ISE Integrated Systems Engineering, Inc. and the technical staff of ISE in Zurich, Switzerland for providing computer-generated cross-sectional color graphics of MOS transistors and CMOS inverters, which are featured in the color plates. The first author acknowledges the support provided by the U.S. Senior Scientist Research Award from the Alexander von Humbold Stiftung in Germany, which was very helpful for the second edition. The appointments of the second author as Associate Professor at Worcester Polytechnic Institute and as Visiting Professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland have provided excellent environments for the completion of the revision project. The second author also thanks Professor Daniel Mlynek of the the Swiss Federal Institute of Technology in Lausanne for his continuous encouragement and support. Many of the authors former and current students at the University of Illinois at Urbana-Champaign, at the Swiss Federal Institute of Technology in Lausanne and at Worcester Polytechnic Institute also helped in the preparation of figures and verification of circuits using SPICE simulations. In particular, Dr. James Stroming and Mr. Frank K. Gilrkaynak deserve special recogni- tion for their extensive and valuable efforts.
  14. 14. The authors would also like to thank Professor Charles Kime of the University of xvWisconsin at Madison, Professor Gerold W. Neudeck of Purdue University, ProfessorD.E. oannou of George Mason University, Professor Subramanya Kalkur of the PrefaceUniversity of Colorado, Professor Jeffrey L. Gray of Purdue University, Professor JacobAbraham of the University of Texas at Austin, Professor Hisham Z. Massoud of DukeUniversity, Professor Norman C. Tien of Cornell University, Professor Rod Beresford ofBrown University, Professor Elizabeth J. Brauer of Northern Arizona University andProfessor Reginald J. Perry of Florida State University, who read all or parts of the revisedmanuscript and provided their valuable comments and encouragement. The editorial staff of McGraw-Hill has, as always, been wonderfully supportive fromthe beginning of the revision project. We thankfully recognize the contributions of ourprevious electrical engineering editor, Ms. Lynn Cox, and we appreciate the extensiveefforts of Ms. Nina Kreiden, who helped the project get off the ground in its early stages.During the final stages of this project, Ms. Kelley Butcher, Ms. Karen Nelson and Mr.Francis Owens have been extremely effective and helpful, and we enjoyed sharing thisexperience with them. Finally, we would like to acknowledge the support from our families, Myoung-A(Mia),,Jennifer and Jeffrey Kang, and Anl and Ebru Leblebici, for tolerating many ofour physical and mental absences while we worked on the second edition of this book,and for providing us invaluable encouragement throughout the project. Sung-Mo (Steve) Kang Yusuf Leblebici Urbana, Illinois Worcester, Massachusetts August 1998 August 1998
  15. 15. CHAPTER 1INTRODUCTION1.1. Historical PerspectiveThe electronics industry has achieved a phenomenal growth over the last few decades,mainly due to the rapid advances in integration technologies and large-scale systemsdesign. The use of integrated circuits in high-performance computing, telecommunica-tions, and consumer electronics has been growing at a very fast pace. Typically, therequired computational and information processing power of these applications is thedriving force for the fast development of this field. Figure 1.1 gives an overview of theprominent trends in information technologies over the next decade. The current leading-edge technologies (such as low bit-rate video and cellular communications) alreadyprovide the end-users a certain amount of processing power and portability. This trendis expected to continue, with very important implications for VLSI and systems design.One of the most important characteristics of information services is their increasing needfor very high processing power and bandwidth (in order to handle real-time video, forexample). The other important characteristic is that the information services tend tobecome more personalized, which means that the information processing devices mustbe more intelligent and also be portable to allow more mobility. This trend towardsportable, distributed system architectures is one of the main driving forces for systemintegration, even though it does not preclude a concurrent and equally important trendtowards centralized, highly powerful information systems such as those required fornetwork computing (NC) and video services. As more and more complex functions are required in various data processing andtelecommunications devices, the need to integrate these functions in a small package isalso increasing. The level of integration as measured by the number of logic gates in a
  16. 16. 2 monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Table 1.1 shows theCHAPTER 1 evolution of logic complexity in integrated circuits over the last three decades, and marks the milestones of each era. Here, the numbers for circuit complexity should be viewed only as representative measures to indicate the order-of-magnitude. A logic block can contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art ULSI chips, such as the DEC Alpha or the INTEL Pentium, contain 3 to 6 million transistors. Note that the term VLSI has been used continuously even for chips in the ULSI (Ultra Large Scale Integration) category, not necessarily abiding by the distinction in Table 1.1. I Video-on-demand I I Speech processing/recognition | C I- Wireless/cellular data communication c I Data communication Multi-media applications | I Consumer electronics] I Portable computers | I Mainframe co I Personal computers I I Network computers I -------------- 1970 1980 1990 2000 Figure1.1. Prominent "driving" trends in information service technologies. ERA DATE COMPLEXITY (# of logic blocks per chip) Single transistor 1958 <1 Unit logic (one gate) 1960 1 Multi-function 1962 2 -4 Complex function 1964 5 - 20 Medium Scale Integration (MSI) 1967 20 - 200 Large Scale Integration (LSI) 1972 200 - 2,000 Very Large Scale Integration (VLSI) 1978 2,000 - 20,000 Ultra Large Scale Integration (ULSI) 1989 20,000 - ? Table 1.1. Evolution of logic complexity in integrated circuits.
  17. 17. The monolithic integration of a large number of functions on a single chip usually 3provides: Introduction * Less area/volume and therefore, compactness * Less power consumption * Less testing requirements at system level * Higher reliability, mainly due to improved on-chip interconnects * Higher speed, due to significantly reduced interconnection length * Significant cost savingsTherefore, the current trend of integration will continue in the foreseeable future.Advances in device manufacturing technology allow the steady reduction of minimumfeature size (such as the minimum channel length of a transistor or an interconnect widthrealizable on chip). Figure 1.2 shows the evolution of the minimum feature size oftransistors in integrated circuits, starting from the late 1970s. In 1980, at the beginningof the VLSI era, the typical minimum feature size was 2 pm, and a feature size of 0.3 gmwas expected around the year 2000. The actual development of the technology, however,has far exceeded these expectations. A minimum feature size of 0.25 gm was achievedby 1995. The first 64-Mbit DRAM and the INTEL Pentium microprocessor chipcontaining more than 3 million transistors were already available by 1994, pushing theenvelope of integration density. The first 4-Gbit DRAM based on 0.15 gm manufacturingtechnology was announced by NEC in early 1997. 4.0 i-D .5 3-0 a) 3.0 E 1.5 2 1.0 0.5 0 1975 1980 1985 1990 1995 2000 YearFigure 1.2. Evolution of minimum feature size in integrated circuits over time. When comparing the integration density of integrated circuits, a clear distinctionmust be made between the memory chips and logic chips. Figure 1.3 shows the level ofintegration over time for memory and logic chips, starting in 1970. The number oftransistors per chip has continued to increase at an exponential rate over the last threedecades, effectively confirming Gordon Moores prediction on the growth rate of chip
  18. 18. 4 complexity, which was made in the early 1960s (Moores Law). It can be observed that in terms of transistor count, logic chips contain significantly fewer transistors in anyCHAPTER 1 given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular, and thus more cells can be integrated with much less area for interconnects. This has also been one of the main reasons why the rate of increase of chip complexity (transistor count per chip) is consistently higher for memory circuits. 100 M 10 M 0 0. CD 1M 0 U C a) a, 0 100 K .0 E z 10K 1K 70 75 80 85 90 95 2000 Year Figure 1.3. Level of integration versus time for memory chips and logic chips. Digital CMOS (Complementary Metal Oxide Semiconductor) integrated circuits (ICs) have been the driving force behind Very Large Scale Integration (VLSI) for high- performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and ongoing improvements in processing technology. It is now projected that the minimum feature size in CMOS ICs can decrease to 0.1 gum within a few years. With such a technology, the level of integration in a single chip can be on the order of several hundreds of millions of transistors for logic chips or even higher in the case of memory chips, which presents an immense challenge for chip developers inprocessing, design methodology, testing, and projectmanagement. Through
  19. 19. i the "divide-and-conquer" approach and more advanced design automation using corm- 5 puter-aided design (CAD) tools, ultra-large-scale problems should be solvable. Bipolar and gallium arsenide (GaAs) circuits have been used for very high speed Introduction circuits, and this practice may continue. For instance, in Monolithic Microwave Inte- grated Circuits (MMICs), GaAs MESFET (MEtal Semiconductor Field Effect Transis- tor) technology has been highly successful. However, they are still not efficient for VLSI or Ultra Large Scale Integration (ULSI) due to processing difficulties and high power consumption, although for special applications their use may continue. As long as the downward scaling of CMOS technology remains strong, other technologies are likely to remain the technology of tomorrow. 1.2. Objective and Organization of the Book The objective of this book is to help readers develop in-depth analytical and design capabilities in digital CMOS circuits and chips. The development of VLSI chips requires an interdisciplinary team of architects, logic designers, circuit and layout designers, packaging engineers, test engineers, and process and device engineers. Also essential are the computer aids for design automation and optimization. It is not possible to discuss the full spectrum of development issues in any single book. Therefore, this book concentrates on digital circuits and also presents related materials in processing and device principles essential to in-depth understanding of CMOS digital circuits. Often readers can become lost in details and fail to see the global picture. For VLSI circuit design, however, it is important that the design be done in the context of global optimization with proper boundary conditions. In fact, the beauty of integrated circuits is that the final design goal is the concerted performance of all interconnected transistors, and not of individual transistors. Therefore, the interconnect issues are almost as important as the issues of individual transistors.-No matter how well an individual transistor performs, if the technology fails to have equally good interconnects, the total performance can be very poor due to large parasitic capacitances and resistances; these translate into a large delay in the interconnection lines between transistors or logic gates. This volume is intended as a comprehensive textbook for senior-level undergradu- ate students and first-year graduate students in an advanced course on digital circuit design. The material presented in this book should also be very useful to practicing VLSI design engineers. Most of the material presented has been taught over several years in undergraduate and graduate-level courses in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign. It is assumed that the readers of this book already have sufficient fundamental background on semiconductor devices, electronic circuit design and analysis, and logic theory. While the interactions among logic design, circuit design, and layout design are strongly emphasized throughout the text, the main focus is on transistor-level circuit design and analysis. This requires a fair amount of detailed current and voltage calculations, as well as a good understanding of how device characteristics affect overall circuit performances, such as propagation delay, noise margins, and power dissipation. The relational ordering and extent of the topics covered in a typical digital integrated circuits course are depicted in Fig. 1.4. First, a fundamental knowledge of basic device physics is required to understand and use various MOSFET device models in circuit
  20. 20. 6 analysis. Following a review of device fundamentals, the emphasis will shift from single devices to simple two-transistor circuits, such as inverters, and then to more complexCHAPTER 1 logic circuits. We will see that as we move to more advanced topics, the breadth of each subject also increases significantly. In fact, a large number of different variations may be considered for implementing complex circuits and systems. Consequently, we will examine representative examples for large-scale system implementations and compare their relative merits in terms of performance, reliability, and manufacturability. Physics Device Electronics Increasing Complexity Two-Transistor Circuits (inver~ters) mbinational and Sequential r Logic Circuits u ar res i. VLSI Sub-Systems ROMs, RAMs, PLAs 1 Adders, Multipliers i ------------------------------------------------------------ System-Related issues, Reliability, Manufacturability, Testability -< ---------- Breadth of Topics - Figure 1.4. The ordering of topics covered in a typical digital integrated circuits course. The book begins with a review of fabrication-related issues. Representative inte- grated circuit fabrication techniques are summarized very briefly in the beginning, in order to establish a simple view of process flow and to provide the reader with the necessary terminologies related to processing. The level and the extent of MOS device physics covered in this book are specifically geared toward hands-on circuit design and analysis applications; hence, most of the device models used are relatively simple. The choice of simple device models imposes certain limitations on the accuracy; however, the emphasis is primarily on the clear understanding of basic design concepts and on the importance of generating meaningful estimates for circuit performance during the early design stages. The very importantrole of computer-aided circuit simulation tools in VLSI design is also well recognized. The book contains a large number of computer simulation examples and exercise problems based on SPICE (Simulation Program with Integrated Circuit Emphasis), which has become a de facto standard in transistor-level circuit simulation in a wide range of computing platforms. An entire chapter is devoted to the examination and comparison of MOSFET models implemented in SPICE, including the identification of various device model parameters. Computer simulation is, and will
  21. 21. continue to be, an essential part of the design process, both for performance verification 7and for fine-tuning of circuits. However, the emphasis on simulation must be well-balanced with the emphasis on hands-on design and analytical estimates, so that the Introductionsignificance of the latter is not overwhelmed by the extensive use of computer-aidedtechniques. The main focus of this book is on CMOS digital integrated circuits, but a significantamount of material on nMOS digital circuits is also presented. Although CMOS hasbecome the technology of choice in many applications in recent years, the fundamentalconcepts of nMOS logic provide a strong basis both for the conceptual understanding andfor the development of CMOS designs. Chapters 5 through 9 are devoted exclusively tothe analysis and design of basic CMOS and also some nMOS digital circuits. Fig. 1.5shows a simple "family tree" for digital integrated circuits that clarifies the classificationand relations among different types of circuits. Based on the fundamental operatingprinciples, the circuits are classified into two main categories, i.e., static circuits anddynamic circuits. The static CMOS circuits are further divided into sub-categories suchas classical (fully complementary) CMOS circuits, transmission-gate logic circuits, pass-transistor logic circuits and cascade voltage switch logic (CVSL) circuits. The dynamicCMOS circuits are divided into sub-categories such as domino logic, NORA, and truesingle-phase clock (TSPC) circuits.Figure .5 Classification of CMOS digital circuit types.
  22. 22. 8 In addition to transistor-level circuit design issues, the accurate prediction and reduction of interconnect parasitics has become a very significant topic in high-CHAPTER 1 performance digital integrated circuits, especially for sub-micron technologies. A large portion of Chapter 6 is therefore devoted to interconnect effects. Semiconductor memo- ries are covered in detail in Chapter 10. Specific emphasis is given to the design and operation of different static and dynamic memory types and to comparisons of their performance characteristics. One chapter of the book is devoted to bipolar transistors and to bipolar/BiCMOS digital circuits, which continue to play an important role in the high- performance digital circuits arena. The inclusion of bipolar-based circuits in this book may be puzzling to some readers, but the significance of BiCMOS design techniques cannot be neglected in a comprehensive text on digital design. One chapter is entirely dedicated to input/output (I/O) circuits and related issues, including ESD protection, level shifting, super-buffer design, and latch-up prevention. Various VLSI design styles, large-scale design considerations, and system-level design issues are discussed in Chapter 14. Finally, two chapters on design for manufacturability and design for testability cover many of the important topics, such as yield estimation, statistical design, and system testability, which deserve special attention in the context of large-scale integrated circuit design. The second edition of this text includes an entirely new chapter, Low-Power CMOS Logic Circuits. The increasing prominence of portable systems and the need to limit power consumption (and hence, heat dissipation) in very high density ULSI chips have led to rapid and very interesting developments in low-power design in recent years. In most cases, the requirements of low power consumption must be combined with the equally demanding tasks of higher integration density and higher circuit performance. In view of these developments, we feel that low-power design of digital integrated circuits should be treated in a separate chapter. Here, various aspects of power consumption are discussed in detail and strategies are introduced to reduce the power dissipation. The chapters are organized in order to allow several different variations of course plans and self-study programs. A number of chapters can be grouped together to accommodate a specific course syllabus, and others can be skipped without a significant loss of continuity. Each chapter contains a large number of solved problems and examples, integrated into the text to enhance the understanding of the material at hand. Also, a collection of problems, some of which are geared specifically for computer-based SPICE simulation, is provided at the end of each chapter. 1.3. A Circuit Design Example To help form a global picture of the digital circuit design cycle, in this chapter we begin with a "once over lightly" design exercise wherein we, as circuit designers, start from a logic diagram along with design specifications. The logic circuit is first translated into a CMOS circuit and the initial layout is done. From the layout, all of the important parasitics are calculated by using a circuit extraction program. Once a full circuit description is obtained from the initial layout, we analyze the circuit for DC and transient performance by using the circuit-level simulation program, SPICE, and then compare the results with the given design specifications. If the initial design fails to meet any one of
  23. 23. the specifications, which is the case in this exercise, we devise an improved circuit design 9to meet the design objective. Then the improved design will be implemented into a newlayout and the design-analysis cycle will be repeated until all of the design specifications Introductionare met. The simplified flow of this circuit design procedure is illustrated in Fig. 1.6. Notethat the topics covered in this textbook concern primarily the two important stepsenclosed in the dotted box, namely, VLSI design and design verification. System Requirements Logic diagram / description Technology Design Rules Device Models Design Rule Checking Circuit Simulation (SPICE) Fail Mask Generation Silicon Processing To: Wafer Testing Packaging Reliability QualificationFigure 1.6. The flow of circuit design procedures.
  24. 24. CHAPTER 1 Example 1.1; In the following example, we will design a one-bit binary full-adder circuit using 0.8-,um, twin-well CMOS technology. The design specifications are Propagation delay times of sum and carryout signals < 1.2 ns (worst case) Transition delay times of sum and carry-out signals < 1.2 ns (worst case) Circuit area < 1500 ,m 2 Dynamic power dissipation (@ VDD = 5 V andfmax = 20 MHz) < 1 mW We start our design by considering the Boolean description of the binary adder circuit. Let A and B represent the two input variables (addend bits), and let C represent the carry-in bit. The binary full adder is a three-input, two-output combinational circuit which satisfies the truth table below. A C sum_ out carry_ out B 0 00 0 0 0 0 1 1 0 0 1 0 1 0 - sum-out 0 11 0 1 Full Adder 1 0 0 1 0 - carry-out C - 1 0 1 0 1 1 1 0 0 1 11 1 1 The sumout and carry-out signals can be found as the following two combinational Boolean functions of the three input variables, A, B and C. sumout =AEBEC =ABC+ABC+ABC+ACB carry out = AB +AC + BC A gate-level realization of these two functions is shown in Fig. 1.7. Note that instead of realizing the two functions independently, we use the carry-out signal to generate the sum output, since the output can also be expressed as sumout =ABC+(A+B+C)carryout
  25. 25. This implementation will ultimately reduce the circuit complexity and, hence, save chip 11 area. Also, we identify two separate sub-networks consisting of several gates (high- lighted with dashed boxes) which will be utilized for the transistor-level realization of the Introduction full-adder circuit. A B C A B C sumFigure 1.7. Gate-level schematic of the one-bit full-adder circuit. For translating the gate-level design into a transistor-level circuit description, we note that both the sum..out and the carryout functions are represented by nested AND- OR-NOR structures in Fig. 1.7. Each such combined structure (complex logic gate) can be realized in CMOS as follows: the AND terms are implemented by series-connected nMOS transistors, and the OR terms are implemented by parallel-connected nMOS transistors. The input variables are applied to the gates of the nMOS (and the complemen- tary pMOS) transistors. Thus, the nMOS net may consist of nested series-parallel,connections of nMOS transistors between the output node and the ground. Once the nMOS part of a complex CMOS logic gate is realized, the corresponding pMOS net, which is connected between the output node and the power supply, is obtained as the dual network of the nMOS net. The resulting transistor-level design of the CMOS full-adder circuit is shown in Fig. 1.8. Note that the circuit contains a total of 14 nMOS and 14 pMOS transistors, together with the two CMOS inverters which are used to generate the outputs. In this specific example, it can also be shown that the dual (pMOS) network is actually equivalent to the nMOS network for both the sum_out and the carry-out functions, which leads to a fully symmetric circuit topology. The alternate circuit diagram obtained by applying this principle of symmetry in shown in Fig. 1.9. Note that the Boolean functions realized by the circuits shown in Fig. 1.8 and Fig. 1.9 are identical; yet the symmetric circuit topology shown in Fig. 1.9 significantly simplifies the layout. These issues will be discussed in detail in Chapter 7.
  26. 26. 12 Initially, we will design all nMOS and pMOS transistors with a (WIL) ratio of (2 um/IO;8 tm), which is the minimum transistor size allowed in this particular technology.CHAPTER 1 This initial sizing of transistors, which is obviously not an optimum solution, may be changed later depending on the performance characteristics of the adder circuit. Choos- ing minimum-size transistors in the initial design stage usually provides a simple, first- cut verification of the circuit functionality and helps the designer in developing a simple initial layout. V-n sum Figure 1.8. Transistor-level schematic of the one-bit full-adder circuit. VDD Figure 1.9. Alternate transistor-level schematic of the one-bit full-adder circuit (note that the nMOS and pMOS networks are completely symmetric).
  27. 27. Next, the initial layout of the full-adder circuit is generated. Here we use a regular, 13gate-matrix layout style in order to simplify the overall geometry and the signal routing.The initial layout using minimum-size transistors is shown in Fig. 1.10. Note that in this Introductioninitial adder cell layout, all nMOS and pMOS transistors are placed in two parallel rows,between the horizontal power supply and the ground lines (metal). All polysilicon linesare laid out vertically. The area between the n-type and p-type diffusion regions is usedfor running local metal interconnections (routing). Also note that the diffusion regions ofneighboring transistors have been merged as much as possible, in order to save chip area.The regular gate-matrix layout style used in this example also has the inherent advantageof being easily adaptable to computer-aided design (CAD). The silicon area occupied bythis full-adder layout is (21 gtm x 54 gtm) = 1134 ,um 2. EHE A B C Ale---. I --IrD -I-*------Ae -u--*4*- - - u - - - ...... . . ... ...... |i.!-, gg ....... ... . . . . .................................. -................. _g0, 1 . o 1 l l!::::: ... .............. ...... i ..... . .... ... IEI Im - _~~~~~~~~~~~~~~~~~~~~~~~~~~~~~: ........................,,i i , i~~~II ............... DD iN : US U ND CO SUMFigure 1.10. Initial layout of the full-adder circuit using minimum-size transistors. The designer must confirm, using an automatic design rule checker (DRC) tool, thatnone of the physical layout design rules are violated in this adder layout. This is usuallydone concurrently during the graphical entry of the layout. The next step is to extract theparasitic capacitances and resistances from the initial layout, and then to use a detailedcircuit simulation tool (e.g. SPICE) to estimate the dynamic performance of the addercircuit. Thus, we are now in the design verification stage of the design-flow diagramshown in Fig. 1.6. The parasitic extraction tool reads in the physical layout file, analyzesthe various mask layers to identify transistors, interconnects and contacts, calculates theparasitic capacitances and the parasitic resistances of these structures, and finallyprepares a SPICE input file that accurately describes the circuit (see Chapter 4). The extracted circuit file is now simulated using SPICE in order to determine itsdynamic performance. The three input waveforms (A, B and C) are chosen so that all ofthe eight possible input combinations are applied consecutively to the full-adder circuit.Assuming that the outputs of this adder circuit may drive a similar circuit, both outputnodes are loaded with capacitors which represent the typical input capacitance of a fulladder. Figure 1.11 shows the simulated input and output waveforms. Unfortunately, the
  28. 28. simulation results show that the circuit does not meet all of the design specifications. The propagation delay times of the sum_out and carry-out signals are found to violate theCHAPTER 1 timing constraints, since the minimum-size transistors are not capable of properly driving the capacitive output loads. 0 Minimum Size Full Adder, Extracted d10 .. . Ccory IN 4.0 2.0 0.0 . . . . . . .. . 10 2 I0 1 . . . .. . . . * . I- . . . . . < . . . 0 x10 2.0 E0 o. OUT .: Carry 5.0 2.0 . . . . . . . . . . . . I . . . . . . . . . . . . . . . I . .1 I -S . 0¢ .: SUM 5 5t - 9~~~~~~~~~~~~~~ 1. 0.0 40_...-t Figure1.11. Simulated input and output waveforms of the full-adder circuit. In particular, the worst-case delay is found to be about 2.0 ns, whereas the timing requirements dictate a maximum delay of 1.2 ns. Figure 1.12 shows the signal propaga- tion delay of both inputs in detail during one of the worst-case input transitions. Design modifications will be necessary to correct this problem. Thus, we go back to the layout design stage. One approach to increase switching speed, and thus, to reduce delay times, would be to increase the (WIL) ratios of all transistors in the circuit. However, increasing the transistor (WIL) ratios also increases the gate, source, and drain areas and, consequently, increases the parasitic capacitances loading the logic gates. Hence, the resizing of
  29. 29. transistors is strictly an iterative process which involves several cycles of consecutive executivee 15 layout modification, circuit extraction, and simulation. Since the carry_out signalI is used to generate the sum output, reducing the delay in the carry_out stage should generally take dly Introduction a higher prio auhigherdedority. Also, one should be careful to consider all possible input tra isitions: Optimiing te Optimizing ti propagation delay for one particular input transition only may resuina alt in an unintended ices fpoaain eay uigohrtastos F iger 1.12. 18 19 20 21 22 23 24 255 Time [nslFigure 1.12. Simulated output waveforms of the full adder circuit with minimum transistor -ansistordimensions, sl showing the signal propagation delay during one of the worst-case transitions. ons. While w, resize the nMOS and pMOS transistors in the full-adder circuit to meet the we rieetthetiming requir requirements, we can also reorganize the whole layout in order to achieve a morecompact placplacement, to increase silicon area utilization, and to reduce the interconnection sectionparasitics within the cell. The resulting cell layout is shown in Fig. 1.12. The new full-Vparasitics wii -W adder layout occupies an area of (43 Atm x 90 gm) = 1290 ,um2 , which is about 14% larger bthan the initiz layout (despite rather aggressive resizing of the transistor dimensions) but initial )ns) still below th pre-set upper limit of 1500 ,um 2. the For the optimized full-adder circuit, we find that all propagation and transition (rise onand fall) dela times are now within the specified limits, i.e., less than 1.2 ns. Figure 1.14 and delay ire 1 14 shows the si signal propagation delay of both inputs during the same worst-case inputetransition de depicted in Fig. 1.11. Note that the propagation delay is about 1.0 ns, a0 nsreduction of.50%. The dynamic power dissipation of this circuit is estimated to be 460 ofAW. Thus, th circuit now satisfies the design specifications given in the beginning. lW. the ning.
  30. 30. 16CHAPTER 1 A B C 01...lDFF; I NWFLL _ POLY = MET-1 E MET 2 MU Figure1.13. Modified layout of the full-adder circuit, with optimized transistor dimensions. Worst Case Delay, otimized Size Transistors, EXTRACTED INPUT . .^ . ~~~CARRY -- 5 I . ! ~~SUM 4 3 A 0 i -_____-L ___-__ .1______ ------------- _---------------- 2.5 -H 2 . . . . . . ....... .. ..... .... .... .. .. .. . .. . . ... ... . 1 .. .... .. .. .. ....... ... ... . .. .. .. .. . .. .. ... . . .. ... .. .. 0 q n 1 nq .1 1 I ~.1.7.....A.. 18 19 20 21 22 23 Z4 2 25b Time [ns] Figure 1.14. Simulated output waveforms of the full-adder circuit with optimized transistor dimensions, showing the signal propagation delay during the same worst-case transition.
  31. 31. The full-adder circuit designed in this example can now be used as the basic building 17block of an 8-bit binary adder, which accepts two 8-bit binary numbers as input andproduces the binary sum at the output. The simplest such adder can be constructed by a Introductioncascade-connection of eight full adders, where each adder stage performs a two-bitaddition, produces the corresponding sum bit, and passes the carry output on to the nextstage. Hence, this cascade-connected adder configuration is called the carry ripple adder(Fig. 1.15). The overall speed of the carry ripple adder is obviously limited by the delayof the carry bits rippling through the carry chain; therefore, a fast carryout responsebecomes essential for the overall performance of the adder chain. S7 .. . C, AO Bo A1 B1 A2 B2 A B 7 7Figure 1.15. Block diagram of a carry ripple adder chain consisting of full adders. Figure 1.16 shows the mask layout of a 4-bit-section of the carry ripple adder circuitwhich is designed by simply cascading full-adder cells to form a regular array. Note thatthe input signals Ai and Bi are applied to a row of pins along the lower boundary of thearray, while the output signals Si (sum bits) are made available along the upper boundaryof the array. This arrangement of the input and output pins simplifies signal routing byplacing the input bus below, and the output bus above the adder array. Also note that no S0 Si S9 S3 MN4 0 D0 1 Da MD 2 2 M3 3 0Figure 1.16. Mask layout of the 8-bit carry ripple adder array.
  32. 32. 18 additional routing is necessary for the carry signal, since the carry-in and carryout pin locations of consecutive full-adder cells are aligned against each other. Such structuresCHAPTER 1 are routinely used in circuits where a large number of arithmetic operations are required, such as arithmetic-logic units (ALUs) and digital signal processing (DSP) circuits. The overall performance of the multi-bit adder can be further increased by various measures, and some of these issues will be discussed in later chapters. The simulated input and output waveforms of the 8-bit binary adder circuit are shown in Fig. 1.17 for a series of sample input vectors. It can be seen that the sum bit of the last adder stage is typically generated last, and the overall delay can be as much as 7 ns. 8Sit Fl1Add., A (Bbit) 00 e14 I9 8 (Bbtt) 00 64 IX9 12 X2 C."r IN, SUM(LS) SUM(1) SUM(2) SUM(4) SUM(5) SUM(6) SUM(7) SUM(MS _ 7.0 a: SUM(7) f Lot Adder SN Stoge 70 SUM(M50) OUT LostAdder Corey of Stage I_01 ~ ~ ~ ~ ~ ~ ~ ~ ~~~~~~~~~~~~l0 710 SUM(WB) Last Add.,Stage~ cwyof .-.Ie .- I Figure 1.17. Simulated input and output waveforms of the 8-bit carry ripple adder circuit, showing a maximum signal propagation delay of about 7 ns.
  33. 33. This example has shown us that the design of CMOS digital integrated circuits 19 involves a wide range of issues, from Boolean logic to gate-level design, to transistor- level design, to physical layout design, and to parasitics extraction followed by detailed Introduction circuit simulation for design tuning and performance verification. In essence, the final output of integrated circuit design is the mask data from which the actual circuit is fabricated. Thus, it is important to design the layout and, hence, the mask set such that the fabricated integrated circuits meet test specifications with a high yield. To achieve such a goal, designers perform extensive simulations using computer models extracted from the layout data and iterate the design until simulated results meet the specifications with sufficient margins. In the following chapters, we will discuss the fabrication of MOS transistors using a set of masks, layout design rules, and electricalproperties of MOS transistors and their computer models, before discussing the most basic CMOS inverter circuit.
  34. 34. CHAPTER 2FABRICATION OF MOSFETs2.1. IntroductionIn this chapter, the fundamentals of MOS chip fabrication will be discussed and the majorsteps of the process flow will be examined. It is not the aim of this chapter to present adetailed discussion of silicon fabrication technology, which deserves separate treatmentin a dedicated course. Rather, the emphasis will be on the general outline of the processflow and on the interaction of various processing steps, which ultimately determine thedevice and the circuit performance characteristics. The following chapters show thatthere are very strong links between the fabrication process, the circuit design process, andthe performance of the resulting chip. Hence, circuit designers must have a workingknowledge of chip fabrication to create effective designs and to optimize the circuits withrespect to various manufacturing parameters. Also, the circuit designer must have a clearunderstanding of the roles of various masks used in the fabrication process, and how themasks are used to define various features of the devices on-chip. The following discussion will concentrate on the well-established CMOS fabrica-tion technology, which requires that both n-channel (nMOS) and p-channel (pMOS)transistors be built on the same chip substrate. To accommodate both nMOS and pMOSdevices, special regions must be created in which the semiconductor type is opposite tothe substrate type. These regions are called wells or tubs. A p-well is created in an n-typesubstrate or, alternatively, an n-well is created in a p-type substrate. In the simple n-wellCMOS fabrication technology presented here, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built into the p- type substrate. In the twin-tub CMOS technology, additional tubs of the same type as the substrate can also be created for device optimization.
  35. 35. The simplified process sequence for the fabrication of CMOS integrated circuits on 21a p-type silicon substrate is shown in Fig. 2.1. The process starts with the creation of then-well regions for pMOS transistors, by impurity implantation into the substrate. Then, Fabricationa thick oxide is grown in the regions surrounding the nMOS and pMOS active regions. of MOSFETsThe thin gate oxide is subsequently grown on the surface through thermal oxidation.These steps are followed by the creation of n+ and p+ regions (source, drain, and channel-stop implants) and by final metallization (creation of metal interconnects).Figure 2.1. Simplified process sequence for the fabrication of the n-well CMOS integratedcircuit with a single polysilicon layer, showing only major fabrication steps. The process flow sequence pictured in Fig. 2.1 may at first seem to be too abstract,since detailed fabrication steps are not shown. To obtain a better understanding of theissues involved in the semiconductor fabrication process, we first have to consider someof the basic steps in more detail.2.2. Fabrication Process Flow: Basic StepsNote that each processing step requires that certain areas are defined on chip byappropriate masks. Consequently, the integrated circuit may be viewed as a set of
  36. 36. 22 patterned layers of doped silicon, polysilicon, metal, and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on the chip.CHAPTER 2 The process used to transfer a pattern to a layer on the chip is called lithography. Since each layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask. To illustrate the fabrication steps involved in patterning silicon dioxide through optical lithography, let us first examine the process flow shown in Fig. 2.2. The sequence Si - substrate (a) SiO 2 (Oxide) .......-................ .................... : :!:!!!!!!!!! (b) . -substrate Photoresist SiO2 (Oxide) (c) Si -substrate UV - Light Glass mask with feature Insoluble .ItI IIII .I photoresist S102 (Oxide) , ::.- ............................. : ::.:: ..... Exposed photoresist becomes soluble (d) Si - substrate Figure 2.2. Process steps required for patterning of silicon dioxide.
  37. 37. 23 Fabrication Chemical etch (HF acid) or dry etch (plasma) of MOSFETs Hardened photoresist SiO 2 (Oxide) . A. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ (e) Si -substrate Hardened photoresist SiO2 (Oxide) ..... .................. ........ E! Si -substrate (f) SiO 2 (Oxide) Si -substrate (9)Figure 2.2. Process steps required for patterning of silicon dioxide (continued).starts with the thermal oxidation of the silicon surface, by which an oxide layer of about1 m thickness, for example, is created on the substrate (Fig. 2.2(b)). The entire oxidesurface is then covered with a layer of photoresist, which is essentially a light-sensitive,acid-resistant organic polymer, initially insoluble in the developing solution (Fig.2.2(c)). If the photoresist material is exposed to ultraviolet (UV) light, the exposed areasbecome soluble so that they are no longer resistant to etching solvents. To selectivelyexpose the photoresist, we have to cover some of the areas on the surface with a maskduring exposure. Thus, when the structure with the mask on top is exposed to UV light,areas which are covered by the opaque features on the mask are shielded. In the areaswhere the UV light can pass through, on the other hand, the photoresist is exposed andbecomes soluble (Fig. 2.2(d)).
  38. 38. 24 * The type of photoresist which is initially insoluble and becomes soluble after exposure to UV light is called positive photoresist. The process sequence shown in Fig.CHAPTER 2 2.2 uses positive photoresist. There is another type of photoresist which is initially soluble and becomes insoluble (hardened) after exposure to UV light, called negative photoresist. If negative photoresist is used in the photolithography process, the areas which are not shielded from the UV light by the opaque mask features become insoluble, whereas the shielded areas can subsequently be etched away by a developing solution. Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high as that of the positive photoresists. Therefore, negative photoresists are-used less commonly in the manufacturing of high-density integrated circuits. Following the UV exposure step, the unexposed portions of the photoresist can be removed by a solvent. Now, the silicon dioxide regions which are not covered by hardened photoresist can be etched away either by using a chemical solvent (HF acid) or by using a dry etch (plasma etch) process (Fig. 2.2(e)). Note that at the end of this step, we obtain an oxide window that reaches down to the silicon surface (Fig. 2.2(f)). The remaining photoresist can now be stripped from the silicon dioxide surface by using another solvent, leaving the patterned silicon dioxide feature on the surface as shown in Fig. 2.2(g). The sequence of process steps illustrated in detail in Fig. 2.2 actually accomplishes a single pattern transfer onto the silicon dioxide surface, as shown in Fig. 2.3. The fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps, however, is quite similar to the one shown in Fig. 2.2. Also note - Si -substrate l v Figure2.3. The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps. Compare the unpatterned structure (top) and the patterned structure (bottom) with Fig. 2.2(b) and Fig. 2.2(g), respectively.