Microprocessors Introduction to PowerPC Architecture History & Interesting Tidbits
Outline <ul><li>Motorola has a long tradition as the leading provider of embedded technologies has produced revolutionary ...
Background of POWER1 <ul><li>Part of IBM’s first attempt at making a real workstation </li></ul><ul><li>POWER – Performanc...
POWER1 Branch unit <ul><li>Had three Instruction Caches – branch, integer, and floating point units </li></ul><ul><li>Bran...
POWER1 Branch unit cont. <ul><li>Loop register is a counter for ‘decrement and branch on zero’ loops with no branch penalt...
Integer/Float units <ul><li>Two 32-bit registers for the integer unit and all load/store operations </li></ul><ul><li>Regi...
MQ register <ul><li>The MQ Register is 36 bits </li></ul><ul><li>During a multiply instruction, MQ contains the multiplier...
PowerPC <ul><li>Born out of a desire to produce a version of the POWER that would succeed both the Motorola 68000 & Intel ...
PowerPC 601 (G1) <ul><li>Meant to bridge the POWER1 and PowerPC features </li></ul><ul><li>Geared towards consumers using ...
The POWER2 is RISCy <ul><li>The big selling point of the POWER2 was its ability to handle six instructions at one time </l...
POWER2 cont. <ul><li>Other additions to the Power2 were: </li></ul><ul><ul><li>Quad-word load and store instructions </li>...
PowerPC 603 (G2) <ul><li>Separated the load/store ops from the integer unit </li></ul><ul><li>Split the branch unit into a...
The little processor that couldn’t <ul><li>Strategy for reducing the size of the 603 –  </li></ul><ul><ul><li>Use a split ...
603’s Marketing Blunder <ul><li>The 603 was compared to the 601 and other high end machines </li></ul><ul><li>MHz per doll...
603 – The Engergizer processor <ul><li>Despite initial marketing problems, this processor became prolific and had far more...
PowerPC 604 <ul><li>The G2 processors were split into two different families (the 603's and the 604's).  </li></ul><ul><ul...
PowerPC 604 float support <ul><li>604's also had tweaks to improve its ability to run inside of its larger L2 cache </li><...
Dynamic Branch Prediction <ul><li>Processors take big performance penalties if they can't preload the cache </li></ul><ul>...
G3’s – The Next Generation <ul><li>Initially, the plan had been to create a new chip ‘solely’ based on the 604 </li></ul><...
740 (Arthur) <ul><li>The first was the 603 derivative </li></ul><ul><li>This processor got some changes to the core (the w...
750 (Typhoon) <ul><li>A variant of the 740 that has a fast method of access to the L2 ‘backside’ cache  </li></ul><ul><ul>...
Hardware Aside <ul><li>Aluminum has long been the standard material used for semiconductor wiring </li></ul><ul><li>IBM ma...
Make room for 4 th  Generation <ul><li>The 603 derived G3 performed very well with its backside cache and was very cheap t...
G4 <ul><li>In direct response to Intel’s MMX instructions, AltiVec extensions were added to the G4 PowerPC </li></ul><ul><...
G4 cont. <ul><li>Supports a 2 Megabyte L2 Cache which can help performance over the previous 1 MB L2 limit. </li></ul><ul>...
Conclusion <ul><li>Obviously, the PowerPC architecture will play a part in imbedded technology for years to come (due to l...
MHz vs. Mega Bucks <ul><li>“ Only weeks ago, Motorola announced at a semiconductor conference that it would soon start shi...
Works Cited <ul><li>http://www.g4store.com/news/ </li></ul><ul><li>http://www.mackido.com/Hardware/ </li></ul><ul><li>http...
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  1. 1. Microprocessors Introduction to PowerPC Architecture History & Interesting Tidbits
  2. 2. Outline <ul><li>Motorola has a long tradition as the leading provider of embedded technologies has produced revolutionary microprocessor and microcontroller solutions </li></ul><ul><li>And Motorola continues to build on that tradition of leadership and innovation with the ever-expanding family of microprocessors that implement the PowerPC instruction set architecture </li></ul><ul><li>In these slides, we’ll take a look at just how the PowerPC got to be in the place it is today. </li></ul>
  3. 3. Background of POWER1 <ul><li>Part of IBM’s first attempt at making a real workstation </li></ul><ul><li>POWER – Performance Optimization With Enhanced RISC </li></ul><ul><li>IBM redefined RISC to mean Reduced Instruction Set Cycle </li></ul><ul><li>Unlike classic RISC design, the POWER1 would be a complex processor </li></ul><ul><ul><li>This meant more high level instructions and more memory-data processors </li></ul></ul><ul><li>This goes against initial RISC philosophy! </li></ul>
  4. 4. POWER1 Branch unit <ul><li>Had three Instruction Caches – branch, integer, and floating point units </li></ul><ul><li>Branch unit unusually complex </li></ul><ul><ul><li>Contained a program counter, condition code (CC) register, and loop register </li></ul></ul><ul><li>CC register – 8 fields </li></ul><ul><ul><li>First 2 reserved for fixed & float ops </li></ul></ul><ul><ul><li>The 7 th for vector operations </li></ul></ul><ul><ul><li>and the rest could be set separately </li></ul></ul>
  5. 5. POWER1 Branch unit cont. <ul><li>Loop register is a counter for ‘decrement and branch on zero’ loops with no branch penalty </li></ul><ul><li>Branch unit could dispatch multiple instructions while itself executing a program control op (up to four ops at once, and out of order) </li></ul><ul><ul><li>This meant this is one of the first superscalar CPUs! </li></ul></ul>
  6. 6. Integer/Float units <ul><li>Two 32-bit registers for the integer unit and all load/store operations </li></ul><ul><li>Register R0 treated as a constant zero for some instructions </li></ul><ul><li>Used an MQ register for extended precision mutiply/divides </li></ul><ul><ul><li>Similar to the MIPS HI/LO registers </li></ul></ul><ul><li>Thirty two 64-bit registers for floating point unit </li></ul><ul><ul><li>Performed only double precision operations </li></ul></ul><ul><ul><li>Used a condition bit to catch float errors (no exceptions!) </li></ul></ul>
  7. 7. MQ register <ul><li>The MQ Register is 36 bits </li></ul><ul><li>During a multiply instruction, MQ contains the multiplier </li></ul><ul><li>During a divide instruction, MQ receives the quotient </li></ul><ul><li>It can be shifted right or left, independently, or combined with AC into a 72-bit register </li></ul>
  8. 8. PowerPC <ul><li>Born out of a desire to produce a version of the POWER that would succeed both the Motorola 68000 & Intel x8086 </li></ul><ul><li>Most notable changes: </li></ul><ul><ul><li>Elimination of the MQ register </li></ul></ul><ul><ul><ul><li>Replaced by separate upper and lower half instructions (able to execute simultaneously) </li></ul></ul></ul><ul><ul><li>Some complex instructions were removed </li></ul></ul><ul><ul><ul><li>Emulated in the new PowerPC </li></ul></ul></ul><ul><ul><li>Support for 32-bit floating point </li></ul></ul>
  9. 9. PowerPC 601 (G1) <ul><li>Meant to bridge the POWER1 and PowerPC features </li></ul><ul><li>Geared towards consumers using workstations rather than high end </li></ul><ul><li>Essentially the same as the POWER1 except for a 32K cache (rather than separate I/D caches) </li></ul><ul><li>Held onto many of ‘legacy’ instructions from the POWER1 </li></ul>
  10. 10. The POWER2 is RISCy <ul><li>The big selling point of the POWER2 was its ability to handle six instructions at one time </li></ul><ul><li>However, it came with the caveat “under ideal conditions” </li></ul><ul><li>They couldn’t be just any old instructions -- to maintain that performance, the POWER2 had to mix exactly two integer instructions, two floating-point instructions, and two branch or condition-code instructions </li></ul>
  11. 11. POWER2 cont. <ul><li>Other additions to the Power2 were: </li></ul><ul><ul><li>Quad-word load and store instructions </li></ul></ul><ul><ul><li>Hardware square root instruction </li></ul></ul><ul><ul><li>New instructions for conversion of floating-point values to integers </li></ul></ul><ul><li>Like the POWER1, this was targeted to high end systems, leaving average users to use the PowerPC </li></ul>
  12. 12. PowerPC 603 (G2) <ul><li>Separated the load/store ops from the integer unit </li></ul><ul><li>Split the branch unit into a fetch/branch unit, a dispatch unit, and a completion/exception unit </li></ul><ul><li>Added a ‘rename’ buffer in the dispatch unit for speculative execution using renamed integer & float registers </li></ul>
  13. 13. The little processor that couldn’t <ul><li>Strategy for reducing the size of the 603 – </li></ul><ul><ul><li>Use a split cache design (instead of a more complex unified cache) </li></ul></ul><ul><ul><li>Remove &quot;unused“ or “legacy” instructions </li></ul></ul><ul><li>Reduced the cost and the power, so 603’s could be made much cheaper, and at higher speeds. </li></ul><ul><li>Had a slight performance penalty (per MHz) but the chips could be made at higher speeds -- which would more than make up for it. </li></ul><ul><li>A good idea, but marketing can be unpredictable </li></ul>
  14. 14. 603’s Marketing Blunder <ul><li>The 603 was compared to the 601 and other high end machines </li></ul><ul><li>MHz per dollar, the 603 beat out the 601 </li></ul><ul><li>But simply comparing MHz to MHz, the 601 was largely faster </li></ul><ul><li>So buyers got the impression that they were getting ripped off </li></ul><ul><li>A case of mistaken expectations! </li></ul>
  15. 15. 603 – The Engergizer processor <ul><li>Despite initial marketing problems, this processor became prolific and had far more variants than any other PowerPC </li></ul><ul><ul><li>603e (603+ / Stretch) – used to solve cache size problems </li></ul></ul><ul><ul><li>603ev, 603p (Valiant), 603r, 603er (Goldeneye) – manufacturing optimization </li></ul></ul>
  16. 16. PowerPC 604 <ul><li>The G2 processors were split into two different families (the 603's and the 604's). </li></ul><ul><ul><li>The 604's were meant to be the ‘bad boys’ of the desktop - Power and cost were not as important as pure blinding speed. </li></ul></ul><ul><li>Unlike the 601 and 603, the 604 can do as many as 4 simultaneous instructions </li></ul>
  17. 17. PowerPC 604 float support <ul><li>604's also had tweaks to improve its ability to run inside of its larger L2 cache </li></ul><ul><li>Floating Point units can become very dependant on cache and memory performance </li></ul><ul><li>The results: </li></ul><ul><ul><li>20% faster than the 603 at integer </li></ul></ul><ul><ul><li>roughly 70% faster in floating point </li></ul></ul><ul><ul><li>Just over twice as fast as the Pentiums of the same time </li></ul></ul>
  18. 18. Dynamic Branch Prediction <ul><li>Processors take big performance penalties if they can't preload the cache </li></ul><ul><li>Being able to accurately &quot;guess&quot; the most likely used path can help keep the cache &quot;preloaded&quot; and increase processor performance </li></ul><ul><li>The 604 was the first mainstream processor to use &quot;Dynamic Branch Prediction“ </li></ul><ul><ul><li>This greatly increased performance </li></ul></ul>
  19. 19. G3’s – The Next Generation <ul><li>Initially, the plan had been to create a new chip ‘solely’ based on the 604 </li></ul><ul><li>But after the highly successful second generation of PowerPC's, IBM and Motorola decided to split out development and create more processors </li></ul>
  20. 20. 740 (Arthur) <ul><li>The first was the 603 derivative </li></ul><ul><li>This processor got some changes to the core (the way it executes instructions) </li></ul><ul><ul><li>Optimized the processor for the Macintosh OS </li></ul></ul><ul><ul><li>This of course resulted in a large performance boost, even more so than the boosts offered by the new backside cache </li></ul></ul><ul><li>The 740 was fast, extremely small and efficient </li></ul><ul><ul><li>It was outperforming Pentium II's while using less than 1/5th the amount of power and size </li></ul></ul>
  21. 21. 750 (Typhoon) <ul><li>A variant of the 740 that has a fast method of access to the L2 ‘backside’ cache </li></ul><ul><ul><li>Allows higher performance </li></ul></ul><ul><ul><li>L2 cache runs much faster than most -- and at speeds up to the clock rate of the main processor </li></ul></ul><ul><li>Cache system really speeds things up, but requires more electronics (and pins) than the 740 </li></ul><ul><ul><li>So while the chip cost isn't much more, the added cache can drive the cost of the system up (and increase the total power usage). </li></ul></ul><ul><li>Still has very good performance per cost </li></ul>
  22. 22. Hardware Aside <ul><li>Aluminum has long been the standard material used for semiconductor wiring </li></ul><ul><li>IBM managed to use copper technology in their G3’s </li></ul><ul><li>The result? </li></ul><ul><ul><li>Enhance chip performance </li></ul></ul><ul><ul><li>Reduced die size and power consumption </li></ul></ul><ul><li>750 first created with standard aluminum design operating at up to 300 MHz </li></ul><ul><li>Applying IBM's copper manufacturing process to the same chip, the 750 featured speeds of at least 400MHz - a 33 percent performance improvement for the same chip! </li></ul>
  23. 23. Make room for 4 th Generation <ul><li>The 603 derived G3 performed very well with its backside cache and was very cheap to make and quite scalable by just adding more L2 cache (or faster L2 cache) </li></ul><ul><li>Apple killed clones and focused the product lines, which all reduced demands for as many different high-end desktop PPC's </li></ul><ul><li>The end results being that the 604 derived G3's (code named Habanero), and some of the other flavors (like ones with better MP support) were scrapped in favor of focusing on the G4's. Which makes sense, considering these other processors wouldn't be coming out until basically the same time as the G4's anyway, and you shouldn't split into that many different development efforts (waste of money) </li></ul>
  24. 24. G4 <ul><li>In direct response to Intel’s MMX instructions, AltiVec extensions were added to the G4 PowerPC </li></ul><ul><li>AltiVec adds a new set of 128-bit registers </li></ul><ul><li>Separate vector execution unit & instruction set supported by branch unit </li></ul><ul><li>Allows multimedia instruction to be executed in parallel with both int and float ops </li></ul><ul><li>Added an addition VRSAVE register to track which vector registers are being used </li></ul><ul><ul><li>Reduces the # of registers needed to be saved </li></ul></ul>
  25. 25. G4 cont. <ul><li>Supports a 2 Megabyte L2 Cache which can help performance over the previous 1 MB L2 limit. </li></ul><ul><li>The mpx bus (used on the G4) is asynchronous and allows for up 4 outstanding accesses at the same time </li></ul><ul><ul><li>The results are up to a 3 fold performance increase for memory bound operations. </li></ul></ul><ul><ul><li>This is why specs can be so deceptive. Without changing the speed of the bus at all, Apple/Motorola made it up to 3 times faster! </li></ul></ul>
  26. 26. Conclusion <ul><li>Obviously, the PowerPC architecture will play a part in imbedded technology for years to come (due to low cost & energy) </li></ul><ul><li>As far as personal computers and workstations go, the PowerPCs generally outperform their Pentium counterparts </li></ul><ul><li>However, much of what’s holding the PowerPC back is consumer obsession with MHz </li></ul>
  27. 27. MHz vs. Mega Bucks <ul><li>“ Only weeks ago, Motorola announced at a semiconductor conference that it would soon start shipping G4 processors operating close to the 1GHz mark. During his conference call, Jobs indicated that Apple would be working closely with Motorola to bridge the MHz gap, and introduce faster chips into the G4 systems. And in a rare preview of the future, Jobs indicated that new, faster G4 systems would begin shipping within the next 6 months.” </li></ul><ul><li>- G4 Store Special Report </li></ul>
  28. 28. Works Cited <ul><li>http://www.g4store.com/news/ </li></ul><ul><li>http://www.mackido.com/Hardware/ </li></ul><ul><li>http://developer.apple.com/technotes/ </li></ul><ul><li>http://www.byte.com/art/9401/sec7/art2.htm </li></ul><ul><li>http://www3.sk.sympatico.ca/jbayko/cpu5.html </li></ul><ul><li>http:// www.mot.com /SPS/PowerPC/ </li></ul>
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