Upcoming SlideShare
×

# Memory Mapping Cache

4,327 views

Published on

Published in: Technology
2 Likes
Statistics
Notes
• Full Name
Comment goes here.

Are you sure you want to Yes No
• Be the first to comment

Views
Total views
4,327
On SlideShare
0
From Embeds
0
Number of Embeds
3
Actions
Shares
0
146
0
Likes
2
Embeds 0
No embeds

No notes for slide

### Memory Mapping Cache

1. 1. Associative Mapping <ul><li>A main memory block can load into any line of cache </li></ul><ul><li>Memory address is interpreted as tag and word </li></ul><ul><li>Tag uniquely identifies block of memory </li></ul><ul><li>Every line’s tag is examined for a match </li></ul><ul><li>Cache searching gets expensive </li></ul>
2. 2. Fully Associative Cache Organization
3. 3. Associative Mapping Example
4. 4. Comparison <ul><li>Direct Cache Example: </li></ul><ul><li>8 bit tag </li></ul><ul><li>14 bit Line </li></ul><ul><li>2 bit word </li></ul><ul><li>Associate Cache Example: </li></ul><ul><li>22 bit tag </li></ul><ul><li>2 bit word </li></ul>
5. 5. Set Associative Mapping <ul><li>Cache is divided into a number of sets </li></ul><ul><li>Each set contains a number of lines </li></ul><ul><li>A given block maps to any line in a given set </li></ul><ul><ul><li>e.g. Block B can be in any line of set i </li></ul></ul><ul><li>e.g. 2 lines per set </li></ul><ul><ul><li>2 way associative mapping </li></ul></ul><ul><ul><li>A given block can be in one of 2 lines in only one set </li></ul></ul>
6. 6. Two Way Set Associative Cache Organization
7. 7. Two Way Set Associative Mapping Example
8. 8. Comparison <ul><li>Direct Cache Example: </li></ul><ul><li>8 bit tag </li></ul><ul><li>14 bit line </li></ul><ul><li>2 bit word </li></ul><ul><li>Associate Cache Example: </li></ul><ul><li>22 bit tag </li></ul><ul><li>2 bit word </li></ul><ul><li>Set Associate Cache Example: </li></ul><ul><li>9 bit tag </li></ul><ul><li>13 bit set </li></ul><ul><li>2 bit word </li></ul>
9. 9. Replacement Algorithms (1) Direct mapping <ul><li>No choice </li></ul><ul><li>Each block only maps to one line </li></ul><ul><li>Replace that line </li></ul>
10. 10. Replacement Algorithms (2) Associative & Set Associative <ul><li>Hardware implemented algorithm (speed) </li></ul><ul><li>First in first out (FIFO) </li></ul><ul><ul><li>replace block that has been in cache longest </li></ul></ul><ul><li>Least frequently used (LFU) </li></ul><ul><ul><li>replace block which has had fewest hits </li></ul></ul><ul><li>Random </li></ul>
11. 11. Write Policy Challenges <ul><li>Must not overwrite a cache block unless main memory is correct </li></ul><ul><li>Multiple CPUs may have the block cached </li></ul><ul><li>I/O may address main memory directly ? </li></ul><ul><li>(may not allow I/O buffers to be cached) </li></ul>
12. 12. Write through <ul><li>All writes go to main memory as well as cache </li></ul><ul><li>( Only 15% of memory references are writes) </li></ul><ul><li>Challenges: </li></ul><ul><li>Multiple CPUs MUST monitor main memory traffic to keep local (to CPU) cache up to date </li></ul><ul><li>Lots of traffic – may cause bottlenecks </li></ul><ul><li>Potentially slows down writes </li></ul>
13. 13. Write back <ul><li>Updates initially made in cache only </li></ul><ul><li>(Update bit for cache slot is set when update occurs – Other caches must be updated) </li></ul><ul><li>If block is to be replaced, memory overwritten only if update bit is set </li></ul><ul><li>( Only 15% of memory references are writes ) </li></ul><ul><li>I/O must access main memory through cache or update cache </li></ul>
14. 14. Coherency with Multiple Caches <ul><li>Bus Watching with write through </li></ul><ul><li>1) mark a block as invalid when another </li></ul><ul><li>cache writes back that block, or </li></ul><ul><li>2) update cache block in parallel with </li></ul><ul><li>memory write </li></ul><ul><li>Hardware transparency </li></ul><ul><li>(all caches are updated simultaneously) </li></ul><ul><li>I/O must access main memory through cache or update cache(s) </li></ul><ul><li>Multiple Processors & I/O only access non-cacheable memory blocks </li></ul>
15. 15. Choosing Line (block) size <ul><li>8 to 64 bytes is typically an optimal block </li></ul><ul><li>(obviously depends upon the program) </li></ul><ul><li>Larger blocks decrease number of blocks in a given cache size, while including words that are more or less likely to be accessed soon. </li></ul><ul><li>Alternative is to sometimes replace lines with adjacent blocks when a line is loaded into cache. </li></ul><ul><li>Alternative could be to have program loader decide the cache strategy for a particular program. </li></ul>
16. 16. Multi-level Cache Systems <ul><li>As logic density increases, it has become advantages and practical to create multi-level caches: </li></ul><ul><li>1) on chip </li></ul><ul><li>2) off chip </li></ul><ul><li>L1 (on chip) & L2 (off chip) caches </li></ul><ul><li>L2 cache may not use system bus to make caching faster </li></ul><ul><li>If L2 does not use the system bus, it can potentially be moved into the chip </li></ul><ul><li>Contemporary designs are now incorporating an on chip(s) L3 cache </li></ul>
17. 17. Split Cache Systems <ul><li>Split cache into: </li></ul><ul><li>1) Data cache </li></ul><ul><li>2) Program cache </li></ul><ul><li>Advantage: </li></ul><ul><li>Likely increased hit rates – data and program </li></ul><ul><li>accesses display different behavior </li></ul><ul><li>Disadvantage </li></ul><ul><li>Complexity </li></ul><ul><li>Impact of Superscaler machine implementation ? </li></ul><ul><li>(Multiple instruction execution, prefetching) </li></ul>
18. 18. Comparison of Cache Sizes     a Two values seperated by a slash refer to instruction and data caches b Both caches are instruction only; no data caches Processor Type Year of Introduction Primary cache (L1) 2 nd level Cache (L2) 3 rd level Cache (L3) IBM 360/85 Mainframe 1968 16 to 32 KB — — PDP-11/70 Minicomputer 1975 1 KB — — VAX 11/780 Minicomputer 1978 16 KB — — IBM 3033 Mainframe 1978 64 KB — — IBM 3090 Mainframe 1985 128 to 256 KB — — Intel 80486 PC 1989 8 KB — — Pentium PC 1993 8 KB/8 KB 256 to 512 KB — PowerPC 601 PC 1993 32 KB — — PowerPC 620 PC 1996 32 KB/32 KB — — PowerPC G4 PC/server 1999 32 KB/32 KB 256 KB to 1 MB 2 MB IBM S/390 G4 Mainframe 1997 32 KB 256 KB 2 MB IBM S/390 G6 Mainframe 1999 256 KB 8 MB — Pentium 4 PC/server 2000 8 KB/8 KB 256 KB — IBM SP High-end server/ supercomputer 2000 64 KB/32 KB 8 MB — CRAY MTA b Supercomputer 2000 8 KB 2 MB — Itanium PC/server 2001 16 KB/16 KB 96 KB 4 MB SGI Origin 2001 High-end server 2001 32 KB/32 KB 4 MB — Itanium 2 PC/server 2002 32 KB 256 KB 6 MB IBM POWER5 High-end server 2003 64 KB 1.9 MB 36 MB CRAY XD-1 Supercomputer 2004 64 KB/64 KB 1MB —
19. 19. Intel Cache Evolution Problem Solution Processor on which feature first appears External memory slower than the system bus. Add external cache using faster memory technology. 386 Increased processor speed results in external bus becoming a bottleneck for cache access. Move external cache on-chip, operating at the same speed as the processor. 486 Internal cache is rather small, due to limited space on chip Add external L2 cache using faster technology than main memory 486 Contention occurs when both the Instruction Prefetcher and the Execution Unit simultaneously require access to the cache. In that case, the Prefetcher is stalled while the Execution Unit’s data access takes place. Create separate data and instruction caches. Pentium Increased processor speed results in external bus becoming a bottleneck for L2 cache access. Create separate back-side bus that runs at higher speed than the main (front-side) external bus. The BSB is dedicated to the L2 cache. Pentium Pro Move L2 cache on to the processor chip. Pentium II Some applications deal with massive databases and must have rapid access to large amounts of data. The on-chip caches are too small. Add external L3 cache. Pentium III   Move L3 cache on-chip. Pentium 4
20. 20. Intel Caches <ul><li>80386 – no on chip cache </li></ul><ul><li>80486 – 8k using 16 byte lines and four way set associative organization </li></ul><ul><li>Pentium (all versions) – two on chip L1 caches </li></ul><ul><ul><li>Data & instructions </li></ul></ul><ul><li>Pentium 3 – L3 cache added off chip </li></ul><ul><li>Pentium 4 </li></ul><ul><ul><li>L1 caches </li></ul></ul><ul><ul><ul><li>8k bytes </li></ul></ul></ul><ul><ul><ul><li>64 byte lines </li></ul></ul></ul><ul><ul><ul><li>four way set associative </li></ul></ul></ul><ul><ul><li>L2 cache </li></ul></ul><ul><ul><ul><li>Feeding both L1 caches </li></ul></ul></ul><ul><ul><ul><li>256k </li></ul></ul></ul><ul><ul><ul><li>128 byte lines </li></ul></ul></ul><ul><ul><ul><li>8 way set associative </li></ul></ul></ul><ul><ul><li>L3 cache on chip </li></ul></ul>
21. 21. Pentium 4 Block Diagram
22. 22. Pentium 4 Core Processor <ul><li>Fetch/Decode Unit </li></ul><ul><ul><li>Fetches instructions from L2 cache </li></ul></ul><ul><ul><li>Decode into micro-ops </li></ul></ul><ul><ul><li>Store micro-ops in L1 cache </li></ul></ul><ul><li>Out of order execution logic </li></ul><ul><ul><li>Schedules micro-ops </li></ul></ul><ul><ul><li>Based on data dependence and resources </li></ul></ul><ul><ul><li>May speculatively execute </li></ul></ul><ul><li>Execution units </li></ul><ul><ul><li>Execute micro-ops </li></ul></ul><ul><ul><li>Data from L1 cache </li></ul></ul><ul><ul><li>Results in registers </li></ul></ul><ul><li>Memory subsystem </li></ul><ul><ul><li>L2 cache and systems bus </li></ul></ul>
23. 23. Pentium 4 Design Reasoning <ul><li>Decodes instructions into RISC like micro-ops before L1 cache </li></ul><ul><li>Micro-ops fixed length </li></ul><ul><ul><li>Superscalar pipelining and scheduling </li></ul></ul><ul><li>Pentium instructions long & complex </li></ul><ul><li>Performance improved by separating decoding from scheduling & pipelining </li></ul><ul><ul><li>(More later – ch14) </li></ul></ul><ul><li>Data cache is write back </li></ul><ul><ul><li>Can be configured to write through </li></ul></ul><ul><li>L1 cache controlled by 2 bits in register </li></ul><ul><ul><li>CD = cache disable </li></ul></ul><ul><ul><li>NW = not write through </li></ul></ul><ul><ul><li>2 instructions to invalidate (flush) cache and write back then invalidate </li></ul></ul><ul><li>L2 and L3 8-way set-associative </li></ul><ul><ul><li>Line size 128 bytes </li></ul></ul>
24. 24. PowerPC Cache Organization (Apple-IBM-Motorola) <ul><li>601 – single 32kb 8 way set associative </li></ul><ul><li>603 – 16kb (2 x 8kb) two way set associative </li></ul><ul><li>604 – 32kb </li></ul><ul><li>620 – 64kb </li></ul><ul><li>G3 & G4 </li></ul><ul><ul><li>64kb L1 cache </li></ul></ul><ul><ul><ul><li>8 way set associative </li></ul></ul></ul><ul><ul><li>256k, 512k or 1M L2 cache </li></ul></ul><ul><ul><ul><li>two way set associative </li></ul></ul></ul><ul><li>G5 </li></ul><ul><ul><li>32kB instruction cache </li></ul></ul><ul><ul><li>64kB data cache </li></ul></ul>
25. 25. PowerPC G5 Block Diagram