Flip & flop by Zaheer Abbas Aghani

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Flip & flop by Zaheer Abbas Aghani

  1. 1. 1..FLIP & FLOPA traditional flip-flop circuit based on bipolar junction transistorsIn electronics, a flip-flop is a circuit that has two stable states and can be used to storestate information. The circuit can be made to change state by signals applied to one ormore control inputs and will have one or two outputs. A circuit incorporating flip-flopshas the attribute of state; its output depends not only on its current input, but also on itsprevious inputs. Such a circuit is described as sequential logic. Where a single input isprovided, the circuit changes state every time a pulse appears on the input signal. Sincethe flip-flop retains the state after the signal pulses are removed, one type of flip-flopcircuit is also called a "latch". Other types of flip-flops may have inputs that set aparticular state, set the opposite state, or change states, depending on which input ispulsed.Flip-flops are used as data storage elements, for counting of pulses, and for synchronizingrandomly-timed input signals to some reference timing signal. Flip-flops are afundamental building block of digital electronics systems used in computers,communications, and many other types of systems.Read more: http://www.answers.com/topic/flip-flop-electronics#ixzz1HWhF4dmG
  2. 2. TYPES OF FLIP & FLOPD flip-flopD flip-flop symbolThe D flip-flop is the most common flip-flop in use today. It is better known as data ordelay flip-flop (as its output Q looks like a delay of input D).The Q output takes on the state of the D input at the moment of a positive edge at theclock pin (or negative edge if the clock input is active low).[23] It is called the D flip-flopfor this reason, since the output takes the value of the D input or data input, and delays itby one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprevotherwise.Truth table: Clock D Q Qprev Rising edge 0 0 X
  3. 3. Rising edge 1 1 X Non-Rising X QprevT FLIP AND FLOPT flip-flopA circuit symbol for a T-type flip-flopIf the T input is high, the T flip-flop changes state ("toggles") whenever the clock input isstrobed. If the T input is low, the flip-flop holds the previous value. This behavior isdescribed by the characteristic equation: (expanding the XOR operator)and can be described in a truth table: T flip-flop operation[25] Characteristic table Excitation tableT Q Qnext Comment Q Qnext T Comment0 0 0 hold state (no clk) 0 0 0 No change0 1 1 hold state (no clk) 1 1 0 No change1 0 1 toggle 0 1 1 Complement1 1 0 toggle 1 0 1 ComplementWhen T is held high, the toggle flip-flop divides the clock frequency by two; that is, ifclock frequency is 4 MHz, the output frequency obtained from the flip-flop will be
  4. 4. 2 MHz. This "divide by" feature has application in various types of digital counters. A Tflip-flop can also be built using a JK flip-flop (J & K pins are connected together and actas T) or D flip-flop (T input and Qprevious is connected to the D input through an XORgate). A T flip-flop can also be built using an edge-triggered D flip-flop with its D inputfed from its own inverted output.JK FLIP & FLOPJK flip-flopA circuit symbol for a positive-edge-triggered JK flip-flopJK flip-flop timing diagramThe JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) byinterpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, thecombination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1is a command to reset the flip-flop; and the combination J = K = 1 is a command totoggle the flip-flop, i.e., change its output to the logical complement of its current value.Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state.To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flopis therefore a universal flip-flop, because it can be configured to work as an SR flip-flop,a D flip-flop, or a T flip-flop.NOTE: The flip-flop is positive-edge triggered (rising clock pulse) as seen in the timingdiagram.The characteristic equation of the JK flip-flop is:
  5. 5. and the corresponding truth table is: JK Flip Flop operation[25]Characteristic table Excitation tableJ K Qnext Comment Q Qnext J K Comment0 0 Q hold state 0 0 0 X No change0 1 0 reset 0 1 1X Set1 0 1 set 1 0 X 1 Reset1 1 Q toggle 1 1 X 0 No changeRs flip and flop) SR flip-flop - (Or "RS flip-flop") A "set/reset" flip-flop in which activating the "S" input will switch it to one stable state and activating the "R" input will switch it to the other state. The outputs of a basic SR flip-flop change whenever its R or S inputs change appropriately. A clocked SR flip-flop has an extra clock input which enables or disables the other two inputs. When they are disabled the outputs remain constant. If we connect two clocked SR flip-flops so that the Q and /Q outputs of the first, "master" flip-flop drive the S and R inputs of the second, "slave" flip-flop, and we drive the slaves clock input with an inverted version of the masters clock, then we have an edge-triggered RS flip-flop. The external R and S inputs of this device are latched on one edge (transition) of the clock (e.g. the falling edge) and the outputs will only change on the next opposite (rising) edge. If both R and S inputs are active (when enabled), a race condition occurs and the outputs will be in an indeterminate state. A JK flip-flop avoids this possibility.2..Counter In digital logic and computing, a counter is a device which stores(and sometimes displays) the number of times a particular event or process has occurred,often in relationship to a clock signal
  6. 6. Types.Up/down counterA counter that can change state in either direction, under the control of an up/downselector input, is known as an up/down counter. When the selector is in the up state, thecounter increments its value. When the selector is in the down state, the counterdecrements the count.4..Digital logic designCombinational And Sequential Circuit Analysis And Design, Digital Circuit Design OptimizationMethods Using Random Logic Gates, Multiplexers, Decoders, Registers, Counters, AndProgrammable Logic Arrays. Computer Aided Tools In The Design, Simulation, And Testing OfDigital Circuits.Importance of digital logic design New, due to popular request! I have received a number of questions regarding the internal structure and operation of logic gates. This is not as simple as it may seem, because there are many different ways to implement logical functions electronically. Therefore, I am now adding some new pages on the major logic families and their internal operation. Ive also had some requests regarding building and demonstrating actual circuits to perform logical functions. If youd like to get some hands-on experience, Ive set up a series of pages on breadboarding logic circuits to demonstrate their operation. If these prove as popular as I expect, I will add to the list soon.
  7. 7. Digital or binary logic has fascinated many people over the years. The very idea that a two-valued number system can possibly be the basis for the most powerful and sophisticated computers seems astounding, to say the least. Nevertheless, it is so, and the how and the why of this requires some explanation. Everything in the digital world is based on the binary number system. Numerically, this involves only two symbols: 0 and 1. Logically, we can use these symbols or we can equate them with others according to the needs of the moment. Thus, when dealing with digital logic, we can specify that: 0 = false = no 1 = true = yes Using this two-valued logic system, every statement or condition must be either "true" or "false;" it cannot be partly true and partly false. While this approach may seem limited, it actually works quite nicely, and can be expanded to express very complex relationships and interactions among any number of individual conditions. One essential reason for basing logical operations on the binary number system is that it is easy to design simple, stable electronic circuits that can switch back and forth between two clearly-defined states, with no ambiguity attached. It is also readily possible to design and build circuits that will remain indefinitely in one state unless and until they are deliberately switched to the other state. This makes it possible to construct a machine (the computer) which can remember sequences of events and adjust its behavior accordingly.ApplicationsDigital electronicsFrom Wikipedia, the free encyclopediaJump to: navigation, searchDigital electronics represent signals by discrete bands of analog levels, rather than by acontinuous range. All levels within a band represent the same signal state. Relativelysmall changes to the analog signal levels due to manufacturing tolerance, signalattenuation or parasitic noise do not leave the discrete envelope, and as a result areignored by signal state sensing circuitry.
  8. 8. In most cases the number of these states is two, and they are represented by two voltagebands: one near a reference value (typically termed as "ground" or zero volts) and a valuenear the supply voltage, corresponding to the "false" ("0") and "true" ("1") values of theboolean domain respectively. • An industrial digital controller • Intel 80486DX2 microprocessorDigital techniques are useful because it is easier to get an electronic device to switch intoone of a number of known states than to accurately reproduce a continuous range ofvalues.Digital electronic circuits are usually made from large assemblies of logic gates, simpleelectronic representations of Boolean logic functions.[1]AdvantagesOne advantage of digital circuits when compared to analog circuits is [2] that signalsrepresented digitally can be transmitted without degradation due to noise. For example, acontinuous audio signal, transmitted as a sequence of 1s and 0s, can be reconstructedwithout error provided the noise picked up in transmission is not enough to preventidentification of the 1s and 0s. An hour of music can be stored on a compact disc as about6 billion binary digits.In a digital system, a more precise representation of a signal can be obtained by usingmore binary digits to represent it. While this requires more digital circuits to process thesignals, each digit is handled by the same kind of hardware. In an analog system,additional resolution requires fundamental improvements in the linearity and noisecharacteristics of each step of the signal chain.
  9. 9. DisadvantagesDisadvantagesIn some cases, digital circuits use more energy than analog circuits to accomplish thesame tasks, thus producing more heat which increases the complexity of the circuits suchas the inclusion of heat sinks. In portable or battery-powered systems this can limit use ofdigital systems.For example, battery-powered cellular telephones often use a low-power analog front-endto amplify and tune in the radio signals from the base station. However, a base station hasgrid power and can use power-hungry, but very flexible software radios. Such basestations can be easily reprogrammed to process the signals used in new cellular standards.Digital circuits are sometimes more expensive, especially in small quantities.Most useful digital systems must translate from continuous analog signals to discretedigital signals. This causes quantization errors. Quantization error can be reduced if thesystem stores enough digital data to represent the signal to the desired degree of fidelity.The Nyquist-Shannon sampling theorem provides an important guideline as to how muchdigital data is needed to accurately portray a given analog signal.Analog issues in digital circuitsDigital circuits are made from analog components. The design must assure that theanalog nature of the components doesnt dominate the desired digital behavior. Digitalsystems must manage noise and timing margins, parasitic inductances and capacitances,and filter power connections.Bad designs have intermittent problems such as "glitches", vanishingly-fast pulses thatmay trigger some logic but not others, "runt pulses" that do not reach valid "threshold"voltages, or unexpected ("undecoded") combinations of logic states.Additionally, where clocked digital systems interface to analogue systems or systems thatare driven from a different clock, the digital system can be subject to metastability wherea change to the input violates the set-up time for a digital input latch. This situation willself-resolve, but will take a random time, and while it persists can result in invalid signalsbeing propagated within the digital system for a short time.Since digital circuits are made from analog components, digital circuits calculate moreslowly than low-precision analog circuits that use a similar amount of space and power.However, the digital circuit will calculate more repeatably, because of its high noiseimmunity. On the other hand, in the high-precision domain (for example, where 14 ormore bits of precision are needed), analog circuits require much more power and areathan digital equivalents.
  10. 10. Structure of digital systemsEngineers use many methods to minimize logic functions, in order to reduce the circuitscomplexity. When the complexity is less, the circuit also has fewer errors and lesselectronics, and is therefore less expensive.The most widely used simplification is a minimization algorithm like the Espressoheuristic logic minimizer within a CAD system, although historically, binary decisiondiagrams, an automated Quine–McCluskey algorithm, truth tables, Karnaugh Maps, andBoolean algebra have been used.Representations are crucial to an engineers design of digital circuits. Some analysismethods only work with particular representations.The classical way to represent a digital circuit is with an equivalent set of logic gates.Another way, often with the least electronics, is to construct an equivalent system ofelectronic switches (usually transistors). One of the easiest ways is to simply have amemory containing a truth table. The inputs are fed into the address of the memory, andthe data outputs of the memory become the outputs.For automated analysis, these representations have digital file formats that can beprocessed by computer programs. Most digital engineers are very careful to selectcomputer programs ("tools") with compatible file formats.To choose representations, engineers consider types of digital systems. Most digitalsystems divide into "combinational systems" and "sequential systems." A combinationalsystem always presents the same output when given the same inputs. It is basically arepresentation of a set of logic functions, as already discussed.Automated design toolsTo save costly engineering effort, much of the effort of designing large logic machineshas been automated. The computer programs are called "electronic design automationtools" or just "EDA."Simple truth table-style descriptions of logic are often optimized with EDA thatautomatically produces reduced systems of logic gates or smaller lookup tables that stillproduce the desired outputs. The most common example of this kind of software is theEspresso heuristic logic minimizer.Most practical algorithms for optimizing large logic systems use algebraic manipulationsor binary decision diagrams, and there are promising experiments with genetic algorithmsand annealing optimizations.To automate costly engineering processes, some EDA can take state tables that describestate machines and automatically produce a truth table or a function table for the
  11. 11. combinational logic of a state machine. The state table is a piece of text that lists eachstate, together with the conditions controlling the transitions between them and thebelonging output signals.It is common for the function tables of such computer-generated state-machines to beoptimized with logic-minimization software such as Minilog.Often, real logic systems are designed as a series of sub-projects, which are combinedusing a "tool flow." The tool flow is usually a "script," a simplified computer languagethat can invoke the software design tools in the right order.Tool flows for large logic systems such as microprocessors can be thousands ofcommands long, and combine the work of hundreds of engineers.Writing and debugging tool flows is an established engineering specialty in companiesthat produce digital designs. The tool flow usually terminates in a detailed computer fileor set of files that describe how to physically construct the logic. Often it consists ofinstructions to draw the transistors and wires on an integrated circuit or a printed circuitboard.Trade-offsSeveral numbers determine the practicality of a system of digital logic. Engineersexplored numerous electronic devices to get an ideal combination of fanout, speed, lowcost and reliability.The cost of a logic gate is crucial. In the 1930s, the earliest digital logic systems wereconstructed from telephone relays because these were inexpensive and relatively reliable.After that, engineers always used the cheapest available electronic switches that couldstill fulfill the requirements.The earliest integrated circuits were a happy accident. They were constructed not to savemoney, but to save weight, and permit the Apollo Guidance Computer to control aninertial guidance system for a spacecraft. The first integrated circuit logic gates costnearly $50 (in 1960 dollars, when an engineer earned $10,000/year). To everyonessurprise, by the time the circuits were mass-produced, they had become the least-expensive method of constructing digital logic. Improvements in this technology havedriven all subsequent improvements in cost.With the rise of integrated circuits, reducing the absolute number of chips usedrepresented another way to save costs. The goal of a designer is not just to make thesimplest circuit, but to keep the component count down. Sometimes this results in slightlymore complicated designs with respect to the underlying digital logic but neverthelessreduces the number of components, board size, and even power consumption.
  12. 12. For example, in some logic families, NAND gates are the simplest digital gate to build.All other logical operations can be implemented by NAND gates. If a circuit alreadyrequired a single NAND gate, and a single chip normally carried four NAND gates, thenthe remaining gates could be used to implement other logical operations like logical and.This could eliminate the need for a separate chip containing those different types of gates.The "reliability" of a logic gate describes its mean time between failure (MTBF). Digitalmachines often have millions of logic gates. Also, most digital machines are "optimized"to reduce their cost. The result is that often, the failure of a single logic gate will cause adigital machine to stop working.Digital machines first became useful when the MTBF for a switch got above a fewhundred hours. Even so, many of these machines had complex, well-rehearsed repairprocedures, and would be nonfunctional for hours because a tube burned-out, or a mothgot stuck in a relay. Modern transistorized integrated circuit logic gates have MTBFsgreater than 82 billion hours (8.2×1010) hours,[5] and need them because they have somany logic gates.3..Explain memories in term of digital logicdesign? DECODING LARGE MEMORIESLarge memories such as the 16 KB memory have row and column decoders that split theinput address into a row address and a column address and activate a row and columnselect lines respectively. The row and column select lines select a location in the memoryarray. The memory is arranged in a two-dimensional manner instead of the linear address
  13. 13. method discussed earlier. The reason for adopting a row and column decoder toindependently but simultaneously select a location by its unique row and column numberis to speed up the decoding process. As the memories get larger the decoders that decodeand select a unique memory location also become very large with large number of gates.Due to the increased level of gates of the decoding circuitry the delay in decoding theinput address increases, thereby slowing the memory access. A large address split intorow and column addresses and separately decoded by row and column decoders requirescomparatively smaller decoders with fewer number of gates resulting in fast decodingtimes and thereby faster memory access. The block diagram of a memory using row andcolumn decoders is shown. Figure 40.1.Detail circuitry of the Input/Output Buffer is shown which manages the control of theData In and Data Out lines. Figure 40.2. When the W, write signal is active and thememory chip is selected CS, the top AND gate is selected and the bottom AND gate isdisabled. The data applied at the Data In/Out bi-directional lines is stored in the selectedlatches. When the W signal is inactive and the CS and OE signals are active the bottomAND gate is selected which enables the tri-state buffers connected at the end of the dataout lines leading from the latch outputs. This allows data from the selected latches to beavailable on the Data In/Out lines.
  14. 14. The Reading and Writing of data is done by activating the various memory signals in aproper sequence. The Memory Read Cycle controls the memory for reading of data and aMemory Write Cycle controls the memory for writing of data.Memory Read CycleThe timing diagram of the read cycle is shown. Figure 40.3. To read data from thememory, the Read Cycle is initiated by applying the address signals. The valid addressneeds to be maintained stable for a specified duration tRC the read cycle time. Next, theCS andtheOEsignals are activated, after a delay of tGQ, the output enable access time measuredwithrespect to the high-to-low transition of the OE signal, valid data appears on the data lines.The tAQ, address access time is measured from the beginning of the valid address thatappears on the address lines to the appearance of valid data on the data lines. The timetEQ measures the chip enable access time which is the time for the valid data to appearafter thehigh-to-low transition of the chip select signalCS.Memory Write CycleThe timing diagram of the write cycle is shown. Figure 40.4. To write data to thememory, the Write Cycle is initiated by applying the address signals. The valid addressneedsto be maintained stable for a specified duration tWC the write cycle time. Next, theCSand
  15. 15. the WE signals are activated. The write enable signal WE is activated after a minimumtime of ts(A) the address setup time which is measured from the beginning of the validaddress. Thetime for which the WE signal remains active is known as the write pulse width. After theWE signal becomes active the data that is to be written in the memory at the addressedlocation is applied at the data lines. The WE signal must remain valid after data is appliedatthe data input lines and must remain valid for a minimum time duration tWD. The datamustremain valid for a time th(D), hold time after the WE signal is deactivated.Figure 40.4 Timing diagram of a Write CycleSynchronous Burst SRAMRAM chips are subdivided into Asynchronous RAM (ASRAM) and Synchronous BurstRAM (SB SRAM).The Static memory described is an Asynchronous SRAM, the
  16. 16. operation of which does not depend upon the clock signal. The read and write operationsare carried out asynchronously. Synchronous SRAM uses a clock signal which is used bythe microprocessor to synchronize its activities to synchronize the read and writeoperations for faster operation. The block diagram of a Synchronous Burst SRAM isshown. Figure 40.5.BURSTI/O0-I/O7 8 8 Data Input/OutputSynchronous RAM is very similar to the Asynchronous RAM, in terms of the memoryarray, the address decoders, read/write and enable inputs. In the Asynchronous memorythe various input signals are asynchronous and are not tied to the clock, whereas in theSynchronous memory all the inputs are synchronized with respect to the clock and arelatched into their various registers on an active clock pulse edge. In the diagram, theexternal address,the WE and the CS external signals are latched in on a positive clock transitionsimultaneously. The data that is to be written into the memory is also latched into theData Input Register at the same positive clock transition. For a read operation the data islatched in the Data Output register on the positive clock transition. There are twovariations of the Synchronous SRAM, the Flow-through and the Pipelined SRAM. In theFlow-through SRAM there is no Data Output Register so the data is asynchronously
  17. 17. available on the data lines during a read operation. In the Pipelined version there is a DataOutput Register which latches in the data read from the memory array.The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAMto read or write up to four locations using a single address. When an external address islatched in by the Address register, the lower two bits of the address are connected to theBurst logic circuitry which internally increments the addresses at each clock transitionproducing four different addresses 00, 01, 10 and 11. For example, if an external baseaddress of 37A0 H is stored in the Address Register, the Burst Logic circuitry producesaddresses 37A0, 37A1, 37A2 and 37A3. The detailed Burst Logic circuit is shown.Figure 40.6.Dynamic RAMA static RAM uses a latch to store a single bit of information. Four gates are used toimplement a latch. In terms of transistors, 4 to 6 transistors are required to implement asingle storage cell. In order to build memories with higher densities, a single transistor isused to store a binary value. A single transistor can not store a binary value however it isused to charge and discharge a capacitor. A single memory cell is thus implementedusing a single transistor and a capacitor which occupy lesser space as compared to the sixtransistors which are used to implement a single Static RAM cell. Thus the density of thecapacitor based memory is significantly increased. The capacitor based memory is knownas a Dynamic RAM (DRAM). The drawback of DRAM is the discharging of thecapacitor over a period of time. Unless the capacitor is periodically recharged all theinformation stored in terms of binary bits in a capacitor based memory array is lost. Theextra circuitry required to refresh the capacitor complicates the operation of the DRAM.
  18. 18. The circuit diagram of a single DRAM capacitor based memory cell is shown. Fig 40.7a.The capacitor is connected through a MOSFET which connects or disconnects thecolumn line at B to the capacitor at D. If the row is set at logic high the MOSFETconnects the column line to the capacitor. If the row line is set to logic low the MOSFETdisconnects the column line form the capacitor.Refresh ColumnRefreshRowCapacitorD OUTR/WD INFigure 40.7a Writing a 1 or 0 into the DRAM cellA write operation allows a logic 1 or 0 to be stored in a DRAM cell (capacitor). Theappropriate cell is selected by specifying the address of the memory location which isdecoded and the row connecting the desired cell is activated. The R / W signal is set tologic low indicating a write operation which enables the tri-state Input Buffer. The logic1 which is to be stored in the memory cell is applied at the DIN data line which isavailable at A on the column line. The row line is selected (set to logic high) whichallows the MOSFET to connect column B to capacitor D. The capacitor is charged tologic 1 voltage level via ABD. Figure 40.7a. A Write operation to store logic 0 in aDRAM cell is similar. The appropriate row is selected byspecifying the storage location address. The R / W signal is set to logic low whichenables the Input Buffer. The logic 0 to be stored in the DRAM cell is applied at the DINwhich is stored on the capacitor via ABD. Figure 40.7a. The thick line in the diagramindicates the data path from DIN to the storage capacitor.The read operation is accomplished by specifying the address of the location fromwhich data is to be read. The DRAM address decoder activates the appropriate row. TheR / W signal is set to logic high which enables the output buffer. The logic 1 or 0 storedon the capacitor is available at DOUT through path DBA. Figure 40.7b.The capacitor can not retain the charge, therefore it has to be periodically chargedthrough a refresh cycle. The Refresh Buffer is enabled by setting the Refresh signal tohigh. The input of the Refresh Buffer is connected to the output buffer/sense amplifier.
  19. 19. The R / W signal is set to logic high during the Refresh cycle allowing the informationstored on the capacitor to be available at the output of the Output Buffer/Sense amplifier.The information is feed back to the capacitor through the Refresh Buffer via path CBD.Figure 40.7c.Input BufferFigure 40.7b Reading a 0 or 1 from the DRAM cell
  20. 20. Figure 40.7c Refreshing a DRAM cellAddress MultiplexingDRAM chips use address multiplexing to reduce the number of address lines by half. Theaddress required to select a memory location is split into row and column addresses. Toaccess a DRAM location for reading or writing of information the row address is firstapplied at the address lines. The row address is latched by the Row Address Latch of theDRAM memory chip. The column address is applied next at the same address lines. Thecolumnaddress is latched by the Column Address Latch. Two signals RAS and CAS are used asstrobe signals to control the Row Address and Column Address latches respectively. Theexternal address lines are multiplexed as the same set of address lines are used to applythe row address and the column address at different time instances. The outputs of theRow Address Latch and the Column Address Latch are connected to the Row andColumn Decoders which select a single row and column line selecting the storage cell tobe accessed. Figure 40.8Refresh Control and TimingDecoderD OUTD IN
  21. 21. Figure 40.8 Circuit Diagram of a 1M x 1 DRAMThe R / W signal controls the Reading and Writing of data through the DOUT and DINlines. The E signal enables the DRAM chip. The refresh cycle is controlled by theRefresh Control and Timing circuit which configures the Data Selector to select rowaddressesgenerated by the refresh counter. During the refresh cycle all memory cells connected tothe selected row are refreshed simultaneously. Therefore, a 1M bit DRAM arranged as1024 rows and 1024 columns is refreshed by selecting all the 1024 rows in a sequence.

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