Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect SystemsDevelopment of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect Systems
Similar to Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect SystemsDevelopment of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect Systems
Similar to Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect SystemsDevelopment of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect Systems (20)
Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect SystemsDevelopment of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect Systems
1. Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High
Performance Interconnect Systems
J. Waeterloos1, S. Cummings1, Y. Ohmoto2, L. Archer3, R. Stevens4, S. Lucero1, K.
Yang1, J. Im1, M. Mills1, R. Strittmatter1 , E. Beach1, S. Rozeveld1
1. The Dow Chemical Company, Advanced Electronic Materials, Midland MI USA
2. Hitachi, Ltd. Kasado Administrative Division, 794, Higashitoyoi, Kudamatsu City,
Yamaguchi Prefecture, 744-8601 Japan
3. SEZ America Inc., 4829 S. 38th St. Phoenix, AZ 85040
4. ATMI, 617 River Oaks Pkwy., San Jose, CA 95134
(Email : jwaeterloos@dow.com )
Abstract porous SiLK films have lower k value, no
frequency dispersion, and high fracture
The use of hybrid integration schemes toughness but have a higher CTE value
provides an option on how to increase the compared to SiOC films. Examples of Hybrid
effects of CTE mismatch related the use of integration schemes has been shown by
organic polymers as ILD. Sequential finite Toshiba/Sony in [1,2].
element analysis is used to determine the
mechanics and subsequently a hybrid If a full SiLK stack is used, careful stack
damascene interconnect is build to design is required as the higher CTE values of
demonstrate the approach. SiLK films can create additional mechanical
stress in the via during thermal cycling events.
Key words Sequential finite element analysis (FEA) [3]
has shown that the successful integration is not
Porous SiLK, hybrid integration, damascene, determined by just the interlayer dielectric
etch, clean, parametric (ILD) but is determined by the combination of
materials used such as the type and thickness
INTRODUCTION
of the Cu capping film, stack height, via
profiles, intrinsic stress of the metallization
As device dimensions shrink, additional
films, etc. An example of a FEA analysis of a
performance is required from the interconnect
dual damascene structure is shown in Fig. 1.
system. The two most commonly employed
solutions are the use of copper to replace
aluminum as the metal conductor and low
dielectric constant materials (low-k) to replace
σy
silicon dioxide as the inter-level dielectric.
The migration to copper has become a (MPa)
standard in the manufacturing of high-end
products. The implementation and integration
of low-k materials, however, is not as
straightforward. In this work we will
specifically focus on how low-k materials can
be integrated to obtain a highly reliable
system.
Motivation for using a Hybrid Integration
Sequence
Fig.1 : FEA analysis of a full SiLK dual damascene
stack. Due to the CTE mismatch an increases stress
The proposed scheme is based on a so-called is observed at the via.
hybrid approach combining the best properties
of two different materials: a SiOC CVD film at A via however can be considered as a local 3-
the via level and porous SiLK* semiconductor dimensional structure and is typically the most
dielectric (*trademark of The Dow Chemical sensitive to CTE related stress. To alleviate
Company) at the trench level. Most low k this aspect of the integration reliability, a
CVD films have to compromise between compromise is made. A material with a higher
fracture toughness and dielectric constant but k value but with a lower CTE is used at the via
retain coefficient-of-thermal-expansion (CTE) level. A trench can be viewed as a 2-
values between 10 and 20 ppm/C. SiLK and
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2. dimension structure and is therefore much less If a dual damascene is pursued, a third choice
sensitive to CTE mismatch and related stress. needs to be made whether to etch the via in the
It is also at that level that the interline SiOC and then apply the porous SiLK film or
capacitance exerts the highest influence and the deposited the entire stack, i.e SiOC and
the lowest k value would be desired. porous SiLK film, followed by the patterning
sequence. The impact is that the material
performance criteria and required patterning
Integration process sequence development/performance is impacted by this
choice. In this work, the via was etched in the
For hybrid several integration approaches can SiOC film before deposition in the SiLK film.
be explored. In principle, a trench-first or via- A more detailed discussion can be found in
first approach could be selected. Both options [4].
have intrinsic advantages and disadvantages.
When misalignment of one level to the other
would occur, the trench-first approach has the Process modules
advantage that the via barrel size does not
change with the degree of lithographic The processing of the wafers was completed at
misalignment however the metal spacing does. different sites. All processing was done using
In the case of a via-first approach, the metal the wafer service division of ISMT with the
spacing not altered but there is a direct impact exception of coat and cure being performed in
on the metal to via overlap. A brief overview Dow’s Application Lab ; etch was done HHT,
of the integration sequence is shown in Fig. 2. Post etch clean was done using ATMI
chemistry on a SEZ tool. All formerly
mentioned companies are members of the
SiLKNet Alliance.
Coat/cure
A 250 nm porous SiLK Y film was spin coated
on the substrate using a TEL SOD ACT8 in
Dow’s Auburn facility. Subsequent to the
hotplate bake under N2, a 2 hour, 400C furnace
cure was given using an Eaton Compact II
furnace. Typical uniformities which are
obtained are below 0.3% 1 sigma. Porous
SiLK Y has an average pore size smaller than
2nm obtained by creating subtractive porosity.
With porous dielectrics the barrier continuity is
always of great concern. The properties in
Fig 2 : (left) Dual damascene via first approach ; general and specifically the barrier continuity
(right) Single damascene viafirst approach is discussed in [5]
A statistical RMS analysis incorporating Patterning
shows that a via-first approach is preferred as
the highest design rule accuracy can be The lithography was done using 248 nm
obtained. The root cause is that for a via-first lithography with a 200 nm line space target. A
sequence the via(n) is aligned to metal(n) and 60 nm BARC was used to suppress an
metal (n+1) is aligned to via(n). In the case of substrate reflectivity issues. For both
a trench-first scheme both via(n) and metal integration schemes the via- first sequence was
(n+1) are aligned to metal(n). used.
A second degree of freedom is to be found in In both cases of the single damascene or dual
whether a single or dual damascene approach damascene process sequence as show in Fig. 2,
is used. Both options are explored and results the via patterning is fairly straightforward. In
will be presented in the next sections. It the case of the SD strategy the metallized via
however needs few comments that a dual is capped with a SiC film which will act as a
damascene approach will have a lower cost-of- stopping layer for the trench etch. It is
ownership (CoO) compared to a single however for the dual damascene scheme that
damascene sequence. the patterning is much more difficult.
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3. All dielectric etches are done on a UHF-ECR analysis. The eventual process chosen was 60
Plasma Etching System U-622, which enables sec. at 25 °C. Representative SEM images are
a stable discharge is provided in low- shown in Figures 4 and 5. PT-15 shows good
pressure/middle-density plasma region UHF- compatibility with porous SiLK and is not
ECR system. The hardmask opening is again a deleterious to the exposed Cu metal.
well know process step. The challenge is
found in etching the p SiLK film as much as
possible before the resist is fully consumed.
The latter will result in the onset of CD gain.
The second issue related to profile control.
The p SiLK inside the plug needs to be
removed during the etch step. During this
event the p SiLK at the sidewalls will be
exposed to the etch chemistry for a prolonged
time and lateral etching may occur. As is seen
in Fig. 3, good profile control can be obtained
by using adequate process conditions.
Fig 4 : Dual Damascene trench structure prior to
wet cleaning. The filled via is clearly visible to the
left of the image.
Fig 3 : Trench patterning in the case of the single
damascene approach where hardmask, p SiLK film
and SiC are opened
The final step is the Cu cap opening step.
Fig 5 : Dual Damascene Trench structure after
Although seemly a trivial step, due to the
exposure to PT-15 at 25 °C for 60 sec..
selectivity of the Cu cap to other films, quite
some hardmask is removed. This loss of
Metallization
hardmask needs to be accounted for when
establishing the required. hardmask thickness
A Ta based PVD barrier is used as Cu barrier
followed by the seed deposition. Trench CU
Post etch clean
fill is performed using electrochemical plating.
Once the plating is completed the excess Cu is
The post dry strip residue removal step was
removed by chemical mechanical polishing
achieved by processing the wafers on an SEZ
using a two step polishing process dedicated to
Single Wafer Spin Processor using ATMI’s
Cu and subsequent barrier removal.
PT-15 residue removal chemistry at the SEZ
America process lab. The Spin Processor
Parametric evaluation
utilizes a Bernoulli chuck and Bernoulli edge-
contact-only (ECO) handling system to
A key parametric figure of merit is found in
minimize handling and defect exposure. PT-
interline leakage current. Since different etch
15 is a semi-aqueous fluoride-based chemistry
chemistries are used the pattern the low k films
typically used in post etch residue removal for
and barriers, the low k films are exposed to
dual damascene, copper/low K device
these chemistries in sequence. In Fig. 6 the
manufacturing and was developed particularly
interline leakage current is shown measured
for use in single wafer spray tool applications
using a finger-comb structure having 0.225 um
such as the SEZ platform. The baseline
line/space. As is seen the leakage current is
Process-of-Record (POR) was determined
low indicative that no first order film damage
using DOE procedures and examination of the
has occurred.
resultant degree of cleanliness using SEM
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