BT656 Video Capture Controller

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BT656 Video Capture Controller

  1. 1. BT656 Video Capture Controller Summary This document provides detailed reference information with respect to the BT656 peripheral device. Core Reference CR0159 (v1.0) August 21, 2006 There are many video decoder ICs on the market that take S-Video or Composite video signals as input, and convert these signals to the ITU-R BT.656 format. One example is the TVP5150A from Texas Instruments. Altium Designer's BT656 Video Capture Controller takes this standard video stream format, decodes it, and reformats it into a simple memory image – stored in external video memory. The content of this memory can then be read by, and output onto, a VGA monitor using one of Altium Designer's 32-bit VGA Controllers. Features • 8-bit parallel ITU-R BT.656-compatible interface • Supports 6 color modes: - Grey-scale: 8, 16, or 32 bits per pixel - RGB: 8, 16, or 32 bits per pixel • Writes directly to external memory without processor intervention • Supports zoom functionality: - Image width (X-scaling): reduce number of converted pixels in a line - Image height (Y-scaling): reduce number of converted lines in a frame • Ability to set frame rate – how many frames to discard for each one captured • Wishbone-compliant • Separate Wishbone Master interface for direct connection to external memory. Available Devices The BT656 Controller device can be found in the FPGA Peripherals integrated library (Program FilesAltium Designer 6LibraryFpgaFPGA Peripherals.IntLib). CR0159 (v1.0) August 21, 2006 1
  2. 2. BT656 Video Capture Controller ITU-R BT.656 Protocol Before discussing the actual BT656 Controller peripheral in detail – including its functional and hardware descriptions – it is worth spending some time to look at the origin of this standard video streaming format and how data is actually transmitted between devices using this protocol. Background The BT.656 video signal data format was introduced formally as a The most recent version of recommendation from the Radiocommunication sector of the International the recommendation is BT.656-4. Telecommunication Union (ITU-R). It describes a simple protocol for the interfaces and data stream format required to send uncompressed PAL (625-line), SECAM (625-line), or NTSC (525-line) television signals between digital television equipment. The protocol defines both bit-parallel and bit-serial interfaces, as well as the blanking, sync and multiplexing schemes uses in transmission of the video signal. Altium Designer's BT656 Controller implements an 8-bit parallel interface, for reception of video data in the BT.656 format. Where ITU-R BT.656 defines the interfaces for transmitting digital video between equipment, the actual digital video signal adheres to ITU-R 601. This recommendation defines the scheme for encoding interlaced analog video signals – for both 625 and 525 line systems – in digital form. For more information on both of these recommendations, refer to www.itu.int/ITU-R. Data Stream Format Figure 1 shows the composition of the BT.656 interface data stream for a single horizontal line of video data, the fields of which are described in the sections that follow. EAV BLANKING SAV Active Video Data Figure 1. Standard ITU-R BT.656 data stream format for a single horizontal line of digital video data. Although EAV, BLANKING and SAV are shown as three distinct fields within the stream, they are collectively the horizontal blanking interval, between active video data for successive lines in the stream. EAV and SAV The EAV (End of Active Video) and SAV (Start of Active Video) parts of the stream are timing codes. Their function can be summarized as follows: • EAV – marks the end of the active video data within the current line and therefore also the start of the subsequent line. • SAV – heralds the start of the active video data within the current line. These codes are embedded within the BT.656 video data stream, thereby eliminating the need for additional (and conventional) timing signals (HSYNC, VSYNC, BLANK) to be included as part of the interface. 2 CR0159 (v1.0) August 21, 2006
  3. 3. BT656 Video Capture Controller Both EAV and SAV codes are comprised of a sequence of four bytes. The first three bytes in the sequence constitute a fixed preamble: FFh – 00h – 00h. The fourth byte, often labeled 'XY' in literature, contains information about the field being transmitted (Field 1 or Field 2 in an interlaced video signal), the state of field blanking (Vertical) and the state of line blanking (Horizontal). The bit assignment for this byte of the code is shown in Figure 2, with the function of each bit described in Table 1. MSB LSB 1 F V H P3 P2 P1 P0 th Figure 2. Bit-assignment for the 4 byte of EAV and SAV codes. th Table 1. Bit functions for the 4 byte of EAV and SAV codes Bit Symbol Function 7 1 Always set to '1'. 6 F Field bit. 0 = Field 1 1 = Field 2 5 V Vertical Blanking Status bit. This bit goes High during a vertical field blanking interval, otherwise it remains Low. 4 H Horizontal Blanking Status bit. 0 – byte is part of SAV code (i.e. stream is entering an active video data region for the current line) 1 – byte is part of EAV code (i.e. stream has entered a horizontal blanking interval – start of a new line) 3 P3 Protection bit 3 2 P2 Protection bit 2 1 P1 Protection bit 1 0 P0 Protection bit 0 The protection bits allow for detection and correction of 1-bit errors and the detection of 2-bit errors. The status of P3, P2, P1 and P0 depend on the states of bits F, V and H. This dependency is shown in Table 2. CR0159 (v1.0) August 21, 2006 3
  4. 4. BT656 Video Capture Controller Table 2. Status of protection bits as F, V and H vary. F V H P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 When receiving the video stream, the BT656 Controller ignores the Protection bits (bits 3..0) of each EAV and SAV code's fourth byte. Active Video Data In accordance with ITU-R BT.601, individual pixels in a line are encoded using the YCbCr color space and, more precisely, the 4:2:2 YCbCr sampling organization. For standard 525/625-line systems, in each line of video the Active Video Data consists of 720 active samples of Y (the luminance – or brightness – component) and 360 samples each of Cb (blue chrominance – or color – component) and Cr (red chrominance – or color – component). The overall number of samples in an Active Video Data region of a stream is therefore 1440. After the SAV code has been transmitted for the current line of video, the active video data is sent in the following standard multiplexed sequence, as defined by the ITU-R BT.656 protocol: Cb0Y0Cr0Y1Cb1Y2Cr1Y3............Cb359Y718Cr359Y719 Each successive grouping of CbYCr within the stream corresponds to a single point on the transmitted picture – i.e. a single pixel. The three samples in such a grouping are referred to as being co-sited. As part of reformatting the ITU-R BT.656 video signal into a VGA-friendly memory image, the BT656 Controller converts the YCbCr color format for each pixel into either corresponding Red, Green and Blue values (RGB) or a Grey value, depending on the color mode set for the Controller. BLANKING During the transmission of the video signal, the portion of the stream in-between active video data segments is known as the horizontal blanking interval. Strictly speaking this entire region is the blanking interval, but this interval also includes the EAV and SAV codes. The remaining bytes of information in a digital blanking interval are filled with values corresponding to the blanking levels of the Cb, Y and Cr signals respectively, and in accordance with the standard multiplex sequence for the stream (CbYCrY..). The blanking levels are as follows: 4 CR0159 (v1.0) August 21, 2006
  5. 5. BT656 Video Capture Controller • Cb = 80h • Y = 10h • Cr = 80h. The sequence in the BLANKING region of the data stream is therefore: 80h, 10h, 80h, 10h.....80h, 10h For standard 525-line systems, the number of bytes of information in the BLANKING region of the stream will be 268. For a standard 625-line system, this number will be 280. Ancillary Data Ancillary data (digital audio, closed-captioning, teletext) can be inserted into the data stream during the horizontal blanking interval, between EAV and SAV codes. It can also be transmitted at any time during vertical blanking intervals. Ancillary data in the video stream will be ignored by the BT656 Controller. CR0159 (v1.0) August 21, 2006 5
  6. 6. BT656 Video Capture Controller Functional Description Symbol Figure 3. BT656 Controller Symbol. Pin description Table 3. BT656 pin description Name Type Polarity/ Description Bus size Control Signals CLK_I I Rise External (system) clock signal RST_I I High External (system) reset Host Processor Interface Signals WBS_STB_I I High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle WBS_CYC_I I High Cycle signal. When asserted, indicates the start of a valid Wishbone cycle 6 CR0159 (v1.0) August 21, 2006
  7. 7. BT656 Video Capture Controller Name Type Polarity/ Description Bus size WBS_ACK_O O High Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated WBS_ADR_I I 3 Address bus, used to select an internal register of the device for writing to/reading from WBS_DAT_O O 32 Data to be sent to host processor WBS_DAT_I I 32 Data received from host processor WBS_SEL_I I 4/High Select input, used to determine where data is placed on the WBS_DAT_O line during a Read cycle and from where on the WBS_DAT_I line data is accessed during a Write cycle. For the BT656 Controller, only 32-bit data transfers are supported, meaning that all the lines go High during a Read/Write cycle. WBS_WE_I I Level Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write INT_O O 2/High Interrupt output lines. Two interrupts are sent to the connected processor on this 2-bit bus: bit 0 = Frame Interrupt. Goes High when the next frame is being written to the external memory. bit 1 = Line Interrupt. Goes High when the next line is being written to the external memory. External Video Memory Interface Signals WBM_STB_O O High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle WBM_CYC_O O High Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers WBM_ACK_I I High Standard Wishbone device acknowledge signal. When this signal goes high, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated WBM_ADR_O O 32 Standard Wishbone Address bus. Used to select an address in the connected Wishbone slave device for writing to CR0159 (v1.0) August 21, 2006 7
  8. 8. BT656 Video Capture Controller Name Type Polarity/ Description Bus size WBM_DAT_O O 32 Data to be sent to the connected Wishbone Slave device WBM_SEL_O O 4/High Select output, used to determine where data is placed on the WBM_DAT_O line during a Write cycle. For the BT656 Controller, only 32-bit data transfers are supported, meaning that all the lines go High during a Write cycle WBM_WE_O O Level Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write Video Data Input Signals vid_data I 8 ITU-R BT.656-compliant video data stream received from the connected Video Decoder device. pclk I Rise Pixel clock, used to clock the video data stream. The frequency of this clock is fixed at 27MHz. vblk I High Video blanking signal. When this signal goes High, the video data stream is not converted. This signal is sampled at byte 4 of the embedded sync data (EAV code) in the video data stream. 8 CR0159 (v1.0) August 21, 2006
  9. 9. BT656 Video Capture Controller Hardware Description Block Diagram BT656 Video Capture Controller Memory Address Generation Input Stream FSM vid_data Scaling pclk START SIZE vblk CbYCrY BUF SCALE BPL VBPL WBS_STB_I WBM_STB_O WBS_CYC_I WBM_CYC_O WBS_ACK_O WBM_ACK_I WBS_ADR_I Color Data FSM WBM_ADR_O WBS_DAT_O WBS_DAT_I Byte Swapping WBM_DAT_O WBS_SEL_I GREY WBM_SEL_O WBS_WE_I WBM_WE_O INT_O[1..0] RGB FIFO_IN FIFO DSWAP YCbCr_BUF Operational Configuration MODE CLK_I RST_I STATUS Figure 4. BT656 Controller block diagram. Internal Registers The following sections detail the internal registers for the BT656 Controller that can be accessed from the host processor. Mode register (MODE) Address: 0h Access: Read and Write CR0159 (v1.0) August 21, 2006 9
  10. 10. BT656 Video Capture Controller Value after Reset: 0000_0014h This register is used to set the operational mode of the Controller. Table 4. The MODE register MSB LSB 31 5 4 3 2 1 0 - cm3 cm2 cm1 sfc run Table 5. The MODE register bit functions Bit Symbol Function MODE.31..MODE.5 - Not Used. MODE.4 cm3 Color Mode selection bits. Used to define the color scheme to be used when converting the YCbCr color space of the BT.656 MODE.3 cm2 stream into RGB or Grey scale. See Table 6 for a full MODE.2 cm1 description of the modes and the corresponding assignment of these bits. MODE.1 sfc Single Frame Capture bit. A single frame will be captured after this bit is set. This bit will be reset by hardware once capture of the frame has completed. MODE.0 run Run mode. 1 = Run continuously, starting with the next complete frame after this bit is set. 0 = Stop. If the Controller is in the process of acquiring a frame, it will proceed with conversion of the frame and then stop. Bits cm3..cm0 are used to select the color mode as follows: Table 6. Color Mode selection cm3:cm2:cm1 Color Mode 001 Grey – 8 bits per pixel (1 byte per pixel) 010 Grey – 16 bits per pixel (2 bytes per pixel) 110 Grey – 32 bits per pixel (4 bytes per pixel) 100 Color – 8 bits per pixel (1 byte per pixel) 101 Color – 16 bits per pixel (2 bytes per pixel) 110 Color – 32 bits per pixel (4 bytes per pixel) Note: Bit assignments 000 and 111 are invalid and will result in the output being disabled. 10 CR0159 (v1.0) August 21, 2006
  11. 11. BT656 Video Capture Controller The sfc and run bits together define the four operating modes in which the Controller can be placed, as listed in Table 7. Table 7. Controller operating modes. sfc:run Operating Mode 00 Disabled 01 Run 10 Single Frame 11 Run (Run mode overrides Single Frame mode) Status register (STATUS) Address: 1h Access: Read only Value after Reset: 0000_0014h This register is used to determine the current state of the Controller. Table 8. The STATUS register MSB LSB 31 5 4 3 2 1 0 - cm3 cm2 cm1 sft run Table 9. The STATUS register bit functions Bit Symbol Function STATUS.31..STATUS.5 - Not Used. STATUS.4 cm3 Color Mode setting. These bits reflect the color scheme chosen to be used when converting the YCbCr color space STATUS.3 cm2 of the BT.656 stream into RGB or Grey scale. See Table 6 STATUS.2 cm1 for a full description of the modes and the corresponding assignment of these bits. STATUS.1 sft Single Frame Triggered flag. This bit is set if the sfc bit in the MODE register (MODE.1) is High, the run bit in the MODE register (MODE.0) is Low, and a single frame of video data is being captured. STATUS.0 run Controller Running flag. This bit is set if the run bit in the MODE register (MODE.0) is High. This bit is updated at the start of a new frame. CR0159 (v1.0) August 21, 2006 11
  12. 12. BT656 Video Capture Controller Start register (START) Address: 2h Access: Read and Write Value after Reset: 0000_0000h This register is used to store the start address for the video buffer in external memory – i.e. the memory address of the first pixel (0, 0) – which is accessed through the Controller's Wishbone Master interface. The start address must be a multiple of 4. The width of the memory used for the video buffer is actually 32 bits. When addressing locations in this memory, the 30-bit address value is sent on the WBM_ADR_O line as bits 31..2, with bits 1..0 always zeros. Size register (SIZE) Address: 3h Access: Read and Write Value after Reset: 0000_0000h This register is used to store the 21-bit value for the size of the video buffer in which the decoded (and reformatted) video image will be stored. Although the value for the actual size can be up to 2Mb (21 bits), only bits 20..2 are used, with bits 1..0 set to '0'. The BT656 Controller never writes outside of the available memory 'window' defined by the START and SIZE registers. The size must be a multiple of 4. Bytes Per Line register (BPL) Address: 4h Access: Read and Write Value after Reset: 0000_05A0h This 13-bit register is used to set the number of bytes per line for the output device onto which the video memory image will be displayed. The value stored is defined by the following expression: BPL register value = Line_Size * BPP, where, Line_Size is the line size of the output device, in pixels. BPP = number of bytes per pixel, in accordance with the color If the width of the output device (e.g. mode chosen for the output. VGA) differs from the width of the With regard to the memory layout of the captured image, the incoming video, there must be a gap between each line, to get each address of each new line will be at a multiple of the value stored in subsequent line of the incoming this register. If we represent the value of the START register by video underneath the last. start_address, and the value of the BPL register with bytes_per_line, then the addresses in memory would be: Line 1 at start_address Line 2 at start_address + bytes_per_line Line 3 at start_address + 2*bytes_per_line, and so on.. 12 CR0159 (v1.0) August 21, 2006
  13. 13. BT656 Video Capture Controller Visible Bytes Per Line register (VBPL) Address: 5h Access: Read and Write Value after Reset: 0000_05A0h This register is used to store the 12-bit value for the number of bytes per line actually written into memory, after any horizontal scaling. The value is calculated as follows: VBPL register value = (Line_Size * BPP) / (x_zoom + 1), where, Line_Size is the line size of the output device, in pixels. BPP = number of bytes per pixel, in accordance with the color mode chosen for the output. x_zoom is the integer representation of the 4-bit x-scaling value set in the SCALE register (SCALE3..0). Scaling register (SCALE) Address: 6h Access: Read and Write Value after Reset: 0000_0000h This register is used to store scaling information, to be applied to the captured image. Table 10. The SCALE register MSB LSB 31 12 11 8 7 4 3 0 - frame_rate y_zoom x_zoom Table 11. The SCALE register bit functions Bit Symbol Function SCALE.31..SCALE.12 - Not Used. SCALE.11..SCALE.8 frame_rate Sets the number of frames to be skipped after each captured frame: 0000 = each frame captured nd 0001 = capture each 2 frame rd 0010 = capture each 3 frame ... th 1111 = capture each 16 frame. SCALE.7..SCALE.4 y_zoom Sets the Y-direction zoom factor: 0000 = no zoom 0001 = discard 1 line after each captured line (1/2 height) 0010 = discard 2 lines after each captured line (1/3 height) CR0159 (v1.0) August 21, 2006 13
  14. 14. BT656 Video Capture Controller Bit Symbol Function ... 1111 = discard 15 lines after each captured line (1/16 height). SCALE.3..SCALE.0 x_zoom Sets the X-direction zoom factor: 0000 = no zoom 0001 = discard 1 pixel after each captured pixel (1/2 width) 0010 = discard 2 pixels after each captured pixel (1/3 width) ... 1111 = discard 15 pixels after each captured pixel (1/16 width). Controller State Machines The BT656 Controller has two Finite State Machines, the tasks of which can be summarized as follows: • Input Stream FSM – this FSM involves a number of states, with its purpose essentially divided into two tasks. In the first task, it waits for an EAV code, which signals the start of a new line in the video stream. It then proceeds through a number of states, relating to the FFh-00h-00-XYh EAV code, the 80h-10h-80h-10h horizontal blanking interval, and finally the FFh-00h-00h-XYh sequence of the SAV code. Once a valid SAV code is detected, the FSM enters its second task – that of reading in the active video data from the input stream in 4-byte Cb-Y-Cr-Y groupings. • Color Data FSM – this FSM has two states; SYNC and PIXEL. In the former, active video data for the line is not yet received. The Controller's Input Stream FSM is still in a state associated with the horizontal blanking interval (including the EAV and SAV codes). During the SYNC state, the Color Data FSM prepares for horizontal scaling by loading the 4-bit value for x_zoom, stored in the SCALE register, into an internal counter. When active video pixel data is received, the required number of pixels will be skipped until the counter decrements to zero. At this stage a pixel must be converted and its value constructed in accordance with the color mode defined in the MODE register (MODE4..2). This value is then written to the FIFO (see Pixel Data Sent to FIFO). Color Conversion The color space used for the digital video data is YCbCr (4:2:2 sampling). As part of the reformatting of the BT.656 stream into the simple memory image, this color space must be converted into RGB or Grey-scale. When the active video data from the stream is read in, each consecutive Cb-Y-Cr-Y grouping of data bytes is stored in a 32-bit buffer register – CbYCrY_BUF. Table 12 illustrates where within this register each byte in the grouping is stored, for pixels 0-1 (i.e. Cb0Y0Cr0Y1). 14 CR0159 (v1.0) August 21, 2006
  15. 15. BT656 Video Capture Controller Table 12. The CbYCrY_BUF register MSB LSB 31 24 23 16 15 8 7 0 Y1 Cr0 Y0 Cb0 From the value in this buffer two YCbCr values are derived, dependant on the value of the internal flag pxl_sel, which is used to distinguish between the odd and even pixels: • pxl_sel = 0 for even pixels • pxl_sel = 1 for odd pixels. Using the example entry in Table 12 above, calculation of the RGB/Grey value for the even pixel – pixel 0 – requires Y0, Cb0 and Cr0. In this case pxl_sel is cleared to '0' and the required Y0Cb0Cr0 value is stored in another buffer register – YCbCr_BUF (Table 13). Table 13. The YCbCr_BUF register holding the YCbCr value for pixel 0 (pxl_sel = 0) MSB LSB 23 16 15 8 7 0 Y0 Cb0 Cr0 Calculation of the RGB/Grey value for the odd pixel – pixel 1 – requires Y1, Cb0 and Cr0. In this case pxl_sel is set to '1' and the required Y1Cb0Cr0 value stored in YCbCr_BUF (Table 14). Table 14. The YCbCr_BUF register holding the YCbCr value for pixel 1 (pxl_sel = 1) MSB LSB 23 16 15 8 7 0 Y1 Cb0 Cr0 Conversion to Grey The 8-bit Grey value of a given YCbCr value – sourced from the By design, the value for the YCbCr_BUF register – is obtained by taking the most significant byte of that luminance (Y) defines the grey YCbCr value. The value is stored in the 8-bit register GREY: value, with the color information in Cb and Cr ignored. GREY = YCbCr_BUF(23..16) Conversion to RGB The Red, Green and Blue values (each 8 bits) of a given YCbCr value – again sourced from the YCbCr_BUF register – are obtained using the following equations: R = Y + 1.402Cr G = Y - 0.344Cb - 0.714Cr B = Y + 1.772Cb The resulting RGB value is stored in the 24-bit RGB register as shown in Table 15. CR0159 (v1.0) August 21, 2006 15
  16. 16. BT656 Video Capture Controller Table 15. The RGB register MSB LSB 23 16 15 8 7 0 R G B Pixel Data Sent to FIFO The value that is sent to the FIFO is constructed using the value in the RGB or GREY register, in accordance with the color mode defined in the MODE register (MODE4..2). The value is stored in an intermediate register – FIFO_IN. Table 16 summarizes the pixel data sent for each of the color modes supported by the Controller. Table 16. Constructed pixel value for each color mode. Color Mode Pixel Data Grey 8 8-bit grey value: GREY(7..0). Grey 16 RGB16-color information which represents the grey value: GREY(7..3) & Grey(7..2) & GREY(7..3). Grey 32 RGB32-color information which represents the grey value. R, G and B each have the same intensity, which is the value GREY(7..0). RGB 8 "00" & RGB(23..22) & RGB(15..14) & RGB(7..6) RGB 16 RGB(23..19) & RGB(15..10) & RGB(7..3) RGB 32 "00000000" & RGB(23..16) &RGB(15..8) & RGB(7..0) Once the pixel value is ready, it is written to the FIFO. The process then repeats, with the next pixel converted after the required X-scaling is observed, until the end of the current line in the video stream. From FIFO to External Memory As soon as pixel data has been written to, and made available in, the FIFO, it is written to the external memory. The address in memory where the next pixel is to be written is calculated based on the content of the BPL and VBPL registers – the latter being used only if scaling/zooming has been applied. The external memory will be written to starting from the address defined by the START register. Pixels will continue to be written to memory until the memory size defined by the SIZE register has been reached. The BT656 Controller will never write to a memory address outside of the 'memory window' defined by the START and SIZE registers. Before data is sent out to external memory on the Controller's WBM_DAT_O line, its endianness needs to be correct. For 32-bit color modes this is already the case. For 16- and 8-bit color modes, this essentially means swapping the data so that the MSB becomes the LSB. An intermediate buffer register – DSWAP – is used to receive the 32-bit pixel value from the FIFO. The bytes of this register are then placed on the WBM_DAT_O line in accordance with the color mode used, as summarized in Table 17. 16 CR0159 (v1.0) August 21, 2006
  17. 17. BT656 Video Capture Controller Table 17. Pixel data sent to external memory. Color Mode 32-bit value sent to External Memory Grey 8/RGB 8 DSWAP(7..0) & DSWAP(15..8) & DSWAP(23..16) & DSWAP(31..24) Grey 16/RGB 16 DSWAP(15..0) & DSWAP(31..16) Grey 32/RGB 32 Content of the DSWAP register as is Interrupts Two interrupt lines are sent from the BT656 Controller to the host processor on the INT_O[1..0] bus. Bit 0 of this bus is used for the Frame Interrupt, used to notify the processor that a new frame is being written to the external memory. The frame interrupt is taken High when the sync signal for the start of Field 1 of a frame goes High, provided also that the previous field in the stream was not the last field and that this frame is not being ignored/skipped (as part of T-scaling). The interrupt is cleared automatically after a single cycle of CLK_I, when the sync signal for Field 1goes Low. Bit 1 of the bus is used for the Line Interrupt, used to notify the processor that a new line is being written to external memory. The Line interrupt is taken High if the following conditions are all met: • The sync signal for the start of the new line is High • The new line is not being ignored/skipped (due to Y-scaling) • The current frame is not being ignored/skipped (due to T-scaling) • The sync signals for the start of Field 1 and Field 2 are both Low. th The interrupt is cleared automatically during the 4 byte of the SAV code for the current line. CR0159 (v1.0) August 21, 2006 17
  18. 18. BT656 Video Capture Controller Interfacing to a 32-bit Processor Figure 5 shows an example of how a BT656 device can be wired into a design that uses a 32-bit processor – in this case a TSK3000A. A configurable Wishbone Interconnect device (WB_INTERCON) is used to simplify connection and also handle the word addressing – taking the 24-bit address line from the processor and mapping it to the 3-bit address line used to drive the BT656. Figure 5. Example interfacing between a 32-bit processor (TSK3000A) and a BT656 Controller. When configuring the WB_INTERCON device – in particular the BT656 slave interface – ensure that the Address Bus Mode is set to Word Addressing – ADR_O(0) <= ADR_I(1 or 2). As the BT656's data bus width is 32-bit, the two lowest address bits are not connected to the slave device. ADR_I(2) of the master is mapped to ADR_O(0) of the slave, providing sequential word addresses (or 18 CR0159 (v1.0) August 21, 2006
  19. 19. BT656 Video Capture Controller addresses at every 4 bytes). Bits 4..2 of the output address line from the host processor (IO_ADR_O) are therefore mapped, through the WB_INTERCON, to bits 2..0 of the BT656's input address line (WBS_ADR_I). The actual 24-bit address sent out from the processor on its IO_ADR_O line is therefore constructed as follows: BT656 Base Address + (Internal Register Address & "00") The Base Address for the BT656 Controller is specified as part of the peripheral’s definition when adding it as a slave to the Wishbone Interconnect. For example, if the base address entered for the device is 100000h (mapping it to address FF10_0000h in the processor’s address space), and you want to write to the Scaling register (SCALE) with address 6h, the value entered on the processor’s IO_ADR_O line would be: 100000h + 18h = 100018h For further information on the Wishbone Interconnect, refer to the WB_INTERCON Configurable Wishbone Interconnect core reference. For further information on the TSK3000A processor, refer to the TSK3000A 32-bit RISC Processor core reference. Similar references can be found for other 32-bit processors supported by Altium Designer, by using the lower section of the Knowledge Center panel and navigating to the Documentation Library » Embedded Processors and Software Development » FPGA Based and Discrete Processors section. For further information regarding the use of the Controller's Wishbone Master interface and connection to external memory, refer to the example project: Program FilesAltium Designer 6ExamplesReference DesignsTSK3000 Spartan3 DoorBelldoorbell_main.PrjFpg. Host to Controller Communications Communications between a 32-bit host processor and the BT656 Controller are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved between Host and Controller for writing to/reading from the internal registers. Writing to an Internal Register Data is written from the host processor to an internal register in the BT656 Controller, in accordance with the standard Wishbone data transfer handshaking protocol. The write operation occurs on the rising edge of the CLK_I signal and can be summarized as follows: • The host presents the required 24-bit address based on the register to be written on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle • The BT656 receives the 3-bit address on its WBS_ADR_I input and, identifying the addressed register, prepares to receive data into that register • The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The BT656, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the WBS_CLK_I signal, reacts to this assertion by latching the data appearing at its WBS_DAT_I input CR0159 (v1.0) August 21, 2006 19
  20. 20. BT656 Video Capture Controller into the target register and asserting its WBS_ACK_O signal – to indicate to the host that the data has been received • The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the BT656 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated. Table 18 summarizes how the 32-bit data word from the host processor is used by each of the internal registers. Table 18. Values loaded into internal registers during a write. Internal Register Value loaded into register MODE WBS_DAT_I(4..0) START WBS_DAT_I(31..2) SIZE WBS_DAT_I(20..2) BPL WBS_DAT_I(12..0) VBPL WBS_DAT_I(11..0) SCALE WBS_DAT_I(11..0) Reading from an Internal Register Data is read from an internal register in accordance with the standard Wishbone data transfer handshaking protocol. The read operation, which occurs on the rising edge of the CLK_I signal, can be summarized as follows: • The host presents the required 24-bit address based on the register to be read on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle • The BT656 receives the 3-bit address on its WBS_ADR_I input and, identifying the addressed register, prepares to transmit data from the selected register • The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The BT656, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the WBS_CLK_I signal, reacts to this assertion by presenting the valid data on its WBS_DAT_O output and asserting its WBS_ACK_O signal – to indicate to the host that valid data is present • The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the BT656 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated. Table 19 summarizes the 'make-up' of the 32-bit data word that is read back from each register. 20 CR0159 (v1.0) August 21, 2006
  21. 21. BT656 Video Capture Controller Table 19. Values read from internal registers during a read. Internal Register Value presented to host processor MODE "000000000000000000000000000" & MODE(4..0) STATUS "000000000000000000000000000" & STATUS(4..0) START START(29..0) & "00" SIZE "00000000000" & SIZE(18..0) & "00" BPL "00000000000000000000" & BPL(11..0) VBPL "00000000000000000000" & VBPL(11..0) SCALE "00000000000000000000" & SCALE(11..0) Operational Overview After an external reset, you will need to initialize the BT656 Controller. This involves: • Writing the value for the start address in external memory to the Controller's START register. • Writing the value for the size of the external memory space to be used, to the Controller's SIZE register. • Write the value for the number of bytes (pixels) per line to the Controller's BPL register, in accordance with the number of pixels on a line and the color format required. • Write the value for the number of visible bytes (pixels) per line to the Controller's VPBL register. • Write the required value to the Controller's SCALE register to achieve the frame rate, and X and Y scaling desired. • Write the required value to the Controller's MODE register to set the color mode required and also set the Controller running in either continuous mode or single frame mode. CR0159 (v1.0) August 21, 2006 21
  22. 22. BT656 Video Capture Controller Revision History Date Version No. Revision 21-Aug-2006 1.0 Initial release Software, hardware, documentation and related materials: Copyright © 2006 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, Board Insight, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. 22 CR0159 (v1.0) August 21, 2006

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