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  • 1. Lattice IPTV solution Jeffery Pu/Senior FAE
  • 2. LatticeECP2 – Low Cost & High Performance ♦ Low Cost, LUT-based FPGA – 6K to 70K LUT4s – 12K to 136K bits distributed memory – 95 to 628 I/O – High volume prices as low as $0.50 per 1K LUTs ♦ Flexible sysIOTM Buffers – LVCMOS 33/25/18/15/12, PCI – SSTL3/2/18 & HSTL15 & HSTL18 – LVDS, RSDS, Bus-LVDS, MLVDS & LVPECL ♦ Pre-engineered Source Synchronous I/Os – DDR1/2 (400 Mbps) Low Cost – Generic Source Synchronous (840 Mbps) 840 Mbps Parallel I/O ♦ sysDSPTM High Performance DSP Support – 12 to 88 18x18 multipliers Bitstream Encryption ♦ sysMEMTM Block Memory 28 GMAC DSP – 55K to 1M bits 400Mbps DDR2 ♦ sysCLOCKTM PLL and DLL ♦ Enhanced Configuration Support – Configuration bitstream encryption – Transparent updates – Dual boot support Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-2
  • 3. Extensive High Performance Clocking ♦ High Performance Clock Distribution – Eight global clock networks – Eight regional secondary clocks – Two low-skew edge clocks per side ♦ sysCLOCK PLL and DLL Technology – 2 to 6 PLLs per device » External capacitor allows operation as low as 1MHz » Dynamic phase shift capability – 2 DLLs per device ♦ On-Chip Oscillator (2.5 to 130MHz) ♦ Edge Clock Divider – X2, X4, X8 – For high speed source synchronous implementations Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-3
  • 4. High Performance sysDSP Block sysDSP Block ♦ Programmable Multiplier – One 36x36, or four 18x18 or X eight 9x9 ♦ Programmable Addition, +-Σ Subtraction & Accumulate X ♦ Programmable Pipelining – Input / Intermediate / Output + ♦ 325MHz Performance X – Provides up to 28.6 GMAC/second per device +-Σ ♦ Suitable For Wide Range of X DSP Functions Including – FIR Filters, FFTs and complex arithmetic Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-4
  • 5. Pre-Engineered Source Synchronous I/O DDR to SDR Conversion ♦ Implement High Speed PIC PIO A Memory Interfaces Tri-state Register Block – DDR1/2 (2 Flip/flops) ♦ Implement High Speed Output Source Synchronous Register Block Interfaces 2:1 (2 Flip/flops) Gearbox – SPI4.2 (Optional) – ADC/DAC Shared Input With PIO B Register Block ♦ Pre-Engineered I/O Logic (5 Flip/flops) Input Support – DDR to SDR conversion DQS/Strobe Delay and Transition Detect* – Gearbox logic – DQS/Strobe alignment PIO B (Detail Not Shown) * Selected blocks 2:1 Gearbox For Precision operation Up to Strobe/DQS Copyright © Lattice Semiconductor 2003 840Mbps Alignment Bringing the Best Together Slide Ref LO-5
  • 6. Advanced Configuration Support ♦ Flexible Configuration Options – Low cost SPI boot memory, microprocessor, JTAG ♦ Bit Stream Encryption – On-chip 128-bit AES decryption – Encryption key securely stored on-chip ♦ Automatic SPI Dual Boot – Allows recovery if power or communication fails during field update ♦ Simple Field Configuration – Define I/O state during field configuration – Reconfigure FPGA while system operates Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-6
  • 7. Encryption Decrypted Data LatticeECP2 Configures FPGA Configuration Decryption Memory Engine 128-bit Key In OTP 128-bit AES 128-bit Key Non-Volatile Encrypted Memory Bitstream ♦ Design Security Increasingly Important – Overbuilding, reverse engineering and cloning all too common ♦ Encrypt Bitstreams With 128-bit AES Using ispVM ♦ On-Chip OTP 128-bit Decryption Key Storage – Choose your own unique key ♦ On-Chip 128-bit AES Decryption Engine Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-7
  • 8. Dual Boot Mode SPI Configuration LatticeECP2 Memory Read Data Sector 0 Golden (A) Configuration Sector 1 Active (B) Control Configuration LatticeECP2 Loads Active Configuration (B) at Power Up. If This Fails Configuration A is Used ♦ Store Active and Backup (Golden) Configurations In SPI Configuration Memory ♦ LatticeECP2 Will Automatically Use Golden Configuration If Active Configuration is Invalid ♦ Increase System Reliability When Configurations are Field Updated Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-8
  • 9. Performance Element Performance (MHz) PFU 375MHz* sysCLOCK PLL 1 – 420MHz Input Range Global Clock 500MHz sysMEM EBR 350MHz sysDSP Block 325MHz 400Mbps (DDR1/2 memory) sysIO Buffer 840Mbps (Generic DDR) * Simple functions (For example 16-bit decoder, 16-bit counter) Performance Supports Designs In Excess of 325MHz Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-9
  • 10. TransFR I/O For Live Field Updates Step 1 Step 2 Step 3 Step 4 Load New Config. To Lock The I/Os In Apply New FPGA Regains Configuration Memory The Desired State Configuration Control of I/O Config. Memory Config. Memory Config. Memory Config. Memory (Config. 2) (Config. 2) (Config. 2) (Config. 2) LatticeECP2 LatticeECP2 LatticeECP2 LatticeECP2 Config. 1 Config. 1 Config.2 Config.2 Field Update FPGAs and Maintain High System Uptime Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-10
  • 11. Soft Error Detect (SED) Logic ♦ LatticeECP2 Devices Contain Hard SED Logic LatticeECP2 ♦ Checks Configuration Bits In Background – Compares to CRC – Ignores EBR and distributed Configuration memory Bits ♦ In Case of Error Optionally: – Generates an error flag – Background reconfigures logic Configuration Hard SED – Initiates a full reconfiguration Logic Logic Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-11
  • 12. I/O Support sysIO Buffer Support Chip Level Support Standard Clock Clock Standard Speed Speed Speed LVTTL, LVCMOS 166MHz 333Mbps DDR1/2 Memory 400Mbps 3.3/2.5/1.8/1.5/1.2 V 66MHz PCI PCI* 66MHz 66MHz Generic Source Synch. 840Mbps SSTL 18/2/3 (I, II) 200MHz 400Mbps HSTL 18/15 (I, II**) 200MHz 400Mbps LVDS*** 420MHz 840Mbps Differential HSTL 200MHz 400Mbps Differential SSTL 200MHz 400Mbps * Includes PCI clamping diode. Bottom I/Os only ** HSTL II outputs only supported for 1.8-volts *** Drivers on 50% of pairs left and right side of the device only **** LVPECL and BLVDS can be supported through emulation Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-12
  • 13. LatticeECP2 Family Device ECP2 6 ECP2 12 ECP2 20 ECP2 35 ECP2 50 ECP2 70 LUTs (K) 6.0 12 21 32 48 68 sysMEM Blocks 3 12 15 18 21 56 sysMEM (Kbits) 55 221 276 331 387 1,032 Distributed RAM (Kbits) 12 24 42 65 96 136 # 18x18 Multipliers 12 24 28 32 72 88 PLLs/DLLs 2/2 2/2 2/2 2/2 4/2 6/2 Package & IO Combinations 144-pin TQFP (20x20mm) 95 95 208-pin PQFP (28x28mm) 127 127 256-ball fpBGA (17x17mm) 192 192 192 484-ball fpBGA (23x23mm) 297 332 332 339 672-ball fpBGA (27x27mm) 363 452 500 500 900-ball fpBGA (31x31mm) 628 Samples Q4 Q2 Q3 Q3 Q1 Q4 Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-13
  • 14. Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-14
  • 15. LatticeSC Architecture High Performance FPGA Fabric 4 to 32 SERDES 2Gbps (Up to 3.4Gbps) PURESPEED I/O with Physical Coding Sublayer (PCS) 15K to 115K LUT4s Up to 7.8 Mbits of Embedded System-Level Memory Blocks Features: Embedded System Bus / Dedicated MACO: Embedded Structured ASIC Microprocessor Blocks Interface / SPI (LatticeSCM Devices) Flash Configuration 8 Analog PLLs / 1.0V-1.2V Operating Voltage 12 DLLs per Device Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-15
  • 16. LatticeSC Extreme Performance Fabric Versatile Logic Blocks Running at 500MHz! • Logic • RAM/ROM • Ripple • MUX • Shift Register Hierarchical Clock Networks To Distribute High Speed Clocks Throughout The Device. • Primary Clock At 700MHz • I/O Tuned Edge Clock At 1GHz Large memory capacity to support fast, flexible RAM. Configure memory as Single- Port RAM, True Dual-Port RAM, Pseudo Dual-Port RAM, ROM, or FIFO. Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-16
  • 17. LatticeSC — Advanced Clocking Options The LatticeSC Devices Have Three Distinct Clock Networks for Use in Distributing High- performance Clocks Within the Device: Primary Clocks; Secondary Clocks; And, I/O Tuned Edge Clocks. Primary Clocks: Edge Clocks: • Designed for Extremely High-performance • High-speed, Fast Injection and VERY Low Skew Clocks Designed for I/O Purposes. • 12 Primary Clocks Per Quadrant • Distributed Around the Edge of the Chip • Can Be Driven by Local Routing (40 Total) • Up to 24 SERDES Clocks Drive Primary Clocks Secondary Clocks: • Ideal for Routing Slower Speed Clock and Control Signals Throughout the Device • Preserves Primary Clock Network for Timing Critical Requirements • All SERDES Clocks Can Drive Secondary Clocks Directly Clock Options to Logic/RAM Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-17
  • 18. PURESPEED I/O Technology Overview I/O Technology Evolution Industry Standard Lattice Enhancement Lattice Innovation The Best Parallel I/O In The Industry: ♦ 15 Single-ended and 7 Differential Buffer Standards Supported With Speeds up to 2Gbps! ♦ Dedicated Source Synchronous Interface Logic With Built-in Dynamic Alignment Capability (Available on Every Pin) ♦ Dedicated DQS Circuitry and DDR-II On-Die Termination for Best-in- class Memory Controller Support ♦ Digitally Controlled On-chip Output Impedance/input Termination for Consistent Performance Over PVT Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-18
  • 19. PURESPEED I/O Logic Output register block contains Programmable I/O Cell (PIC) dedicated high-speed MUX/DEMUX gearing circuitry to PIO A support: Tri-state • DDR/SDR Register Block • Shift x2 • Shift x4 Output Bond Pad Register Block Input register block contains dedicated high-speed MUX/DEMUX gearing circuitry to Input support… High performance Register Block sysIO Buffer • DDR/SDR + Dynamic Input (up to 2 Gbps) • Shift x2 Control Alignment • Supports multiple • Shift x4 Select standards + Dynamic Alignment Logic that • Includes on-chip enables Source Synchronous I/O via termination dedicated: • Input Delay block (INDEL) • Adaptive Input Logic (AIL) Clock domain transfers Edge clocks guaranteed over PVT 1GHz Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-19
  • 20. PURESPEED Innovations: INDEL & AIL • DDR to SDR Conversion • Logic Operates on Both Edges of the Clock INput DELay Block • Dedicated FIFO for Automatic Clock Transfer between Provides 144 Delay High Speed I/O and Lower Speed Internal Clock Tap Settings (40ps Typical Step Size) FPGA System Clock INput DELay Adaptive Input Logic MUX/deMUX Logic (SDR/DDR) Data D Q FPGA Fabric Delay Adjust Setup & Hold AIL Locked Time Monitor Edge DIV2 or DIV4 CLK Dedicated Phase- Adaptive Input Logic (AIL) Examines Setup / Hold Times Matched Clock of Every Input Data Pin and Adjusts the Delay Until the Divider Eliminates Data Edge Falls Outside The Setup/Hold Time Margin Need For PLL The Most Robust Solution - Bit-based Alignment: Data Rates Up to 2Gbps - Automatic Voltage/Temperature Compensation Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-20
  • 21. PURESPEED DDR Memory Solutions Set to match DQS edge clock injection delay, static DQS Mux/demux n INput DELay DQ DQ At the Controller (FPGA) INput DELay DQS postamble gate, DQS shuts off DQS at end of READ We Must Delay the cycle Incoming DQS Signal and Center–align It to the 9 Incoming Data in Order DLL 90° phase shift, compensated over CLK to Capture It PVT and speed of operation DDR CONTROLLER REQUIREMENT LatticeSC PURESPEED I/O IMPLEMENTATION DDR SDRAM DDR II SDRAM QDR II SRAM RLDRAM I/II Feature Controller Controller Controller Controller 300 MHz/600 Mbps Speed of Operation 200 MHz/400 Mbps 267 MHz/534 Mbps 300 MHz/600 Mbps 400 MHz/800 Mbps 8,16,32,40,64,72- Data Width 8,16,32,40,64,72-bit 8,9,18,36-bit 9,18,36-bit bits Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-21
  • 22. LatticeSC — System Standards Support I/O Standard Buffer Type Bus Width Data Rate Clock Frequency Pin Throughput Generic LVDS, LVDS Variable DDR 1GHz Up to 2Gbps Mini-LVDS, RSDS RapidIO Differential 8, 16 DDR 125 — 500MHz 250 Mb — 1Gbps HyperTransport LVDS 32 DDR 200 — 400MHz 400 — 800Mbps SPI-4 (PL4) LVDS 16 DDR 311 — 450MHz 622 — 900Mbps SFI-4 / XSBI LVDS 16 SDR 622/645MHz 622/645Mbps XGMII HSTL 32 DDR 156MHz 311Mbps CSIX L1 HSTL 32 — 128 SDR 250MHz 250Mbps QDR2 SRAM HSTL Variable DDR 300MHz 600Mbps DDR1 / 2 SDRAM SSTL Variable DDR 300MHz 600Mbps PCI / PCI-x LVTTL 32/64 SDR 66/133MHz 66/133/266Mbps RLDRAM 1 / 2 HSTL Variable DDR 300/400MHz 600/800Mbps Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-22
  • 23. LatticeSC PURESPEED I/O — Best in Class ♦ Performance up to 1GHz / 2Gbps ♦ Dedicated Input Delay Block Provides 144 Taps With 40ps Typical Steps ♦ Bit-based Dynamic Alignment for Guaranteed Performance ♦ Dedicated High Speed Mux/demux ♦ Programmable On-chip Termination Simplifies Board Layout ♦ DQS Postamble Detect Logic for High Speed Memory Interfaces ♦ DDR II Dynamic Bus Control ♦ Dedicated Clock Dividers Eliminate Need for PLLs Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-23
  • 24. LatticeSC Industry-Leading SERDES/PCS ♦ Up to 32 Channels Per Device ♦ Speeds From 600 Mbps up to 3.4 Gbps ♦ High Rx Jitter Tolerance (0.8UI) ♦ Low Tx Jitter (0.29UI) ♦ Receiver Programmable Coupling (AC or DC) – Supports SMPTE292M With External Cap and Cable Equalizer ♦ Tx Pre-emphasis and Rx Equalization for Improved BER Over Long (>60”) and Legacy Backplanes – PE of 16%, 32%, 48%, 64%, 80% and 96% – Equalization Settings of 6dB and 12dB ♦ Very Low Power (100mW Per Channel Typical @ 3.125 Gbps) ♦ flexiPCS Compliant to a Number of Current and Emerging Standards – PCS Is Bypass-able in 8/10/16/20 Bit Modes Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-24
  • 25. Masked Array for Cost Optimization ♦ Multiple 90nm Embedded 50K ASIC Blocks ♦ Ample FPGA-to-ASIC Signal Connectivity ♦ Ample ASIC-to-IO Connectivity ♦ High-speed Clock Connectivity Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-25
  • 26. MACO: Standard Offerings SERDES SERDES SERDES SERDES Quad Quad Quad Quad MACO EMB MACO A A EMB B A C C EMB C F B E EMB B D PLC Array LatticeSCM25 KLUTs KLUTs for Blocks Blocks Blocks Blocks Blocks for MACO on on on on on Block IP Type Soft IP Design SCM15 SCM25 SCM40 SCM80 SCM115 A flexiMAC 1GbE 2.7 0 1 2 2 2 4 flexiMAC 10GbE 6 0 flexiMAC PCIe 11 4 to 7 B Memory Controller 2 0 1 2 2 2 2 DDR1/2 Memory Controller 2 0 QDR2 Memory Controller 3 0 RLDRAM C SPI4.2 6 0.8 1 2 2 2 2 Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-26
  • 27. MACO Value Proposition: Lower Cost Per Function ♦ MACO Provides Cost- and Power-efficient, High Performance “Extra” Gates ♦ Commonly-used Functionality Embedded As Hard IP ♦ Advantages: 10x Area Savings, 2x the Performance, and ½ the Power of Equivalent FPGA Based Functions ♦ Development Cost Savings Due to Efficient Die Use and Use of Pre- engineered Blocks Soft IP comes at a 90-100% of IP is significant cost to designed into MACO customer and can be resulting in large LUT SC vs. Generic FPGA difficult to implement savings IP Core SC FPGA Soft IP Fee PCIe x 4 7000 11000 $20,000 Memory Controller 0 2500 $20,000 Customer needs to SPI4.2 1600 8000 $25,000 struggle to get standard Customer LUT s 20,000 20,000 functions working in FPGA logic. Total LUTs 28600 41500 Lattice supplied MACO IP is “pre-engineered” MACO allows very efficient use of resources Bottom Line: LatticeSC+MACO is Less Expensive and Easier to Design Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-27
  • 28. LatticeSC Family Device SC15 SC25 SC40 SC80 SC115 LUT4s (K) 15.2 25.4 40.4 80.1 115.2 sysMEM Blocks (18Kb) 56 104 216 308 424 Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8 Max. Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84 Number of 3.4G SERDES (Max) 8 16 16 32 32 DLLs 12 12 12 12 12 Analog PLLs 8 8 8 8 8 MACO Blocks 4 6 10 10 12 Package I/O + SERDES Channel Combinations (1mm ball pitch) 256-ball fpBGA (17x17) 139 + 4 900-ball fpBGA (31x31) 300 + 8 378 + 8 1020-ball ffBGA (33x33) 484 + 16 562 + 16 1152-ball fcBGA (35x35) 660 + 16 660 + 16 1704-ball fcBGA (42.5x42.5) 904 + 32 942 + 32 OPNs LFSC xx- NO MACO LFSCM xx- MACO ENABLED Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-28
  • 29. LatticeXP FPGA Key Features ♦ Non-Volatile Reconfigurable – Instant-on – Single-chip – High-security ♦ TransFR™ (TFR) Technology – Simplifies in-field logic updates ♦ Wide Density & I/O Selection – 3k to 20k LUTs – 62 to 340 I/Os ♦ Embedded & Distributed Memory ♦ High Performance (225MHz+) ♦ sysIO™ Interface Support – LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL ♦ 333Mbps DDR Memory Interfaces Non-Volatile ♦ sysCLOCK™ PLLs Reconfigurable ♦ Low Power Sleep Mode Flexible LUT-Based ♦ Two Core Power Supply Versions – C = 1.8, 2.5, 3.3V Support “No Compromise” – E = 1.2V Support Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-29
  • 30. LatticeXP Integrates Multiple Components Processor Address and Data Busses Processor Address and Data Busses Microprocessor Microprocessor CPLD Power up logic Data Path FPGA boot logic Power up and bus decode Bus Decode FPGA Data Path function Voltage Regulator Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-30
  • 31. LatticeXP Provides “Instant-On” 140 Altera XP Advantage 120 Wake-up Time (mS) 100 80 60 Xilinx 40 20 Lattice 0 EP1C12 XC3S1000 XP10 Fastest serial configuration LatticeXP Logic is Available <1mS After Power Good -- Supports “Instant-On” Application Requirements -- Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-31
  • 32. Sleep Mode Reduces Power by Factor of 1000 SLEEPN Pin LatticeXP Device Normal Sleep Mode Normal State Typical 100nS Typical 2mS Mode Characteristic Normal Off Sleep SLEEPN Pin High X Low Static Icc Typical <100mA 0 Typical <100uA Power Supplies Normal Range Off Normal Range Logic Operation User Defined Non Operational Non Operational I/O Operation User Defined Tri-State Tri-State Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-32
  • 33. LatticeXP FPGAs Secure Your Design ♦ FPGA Security Important Due To Multiple Threats – Reverse engineering – Cloning – Overbuilding – Theft of service ♦ LatticeXP Security LatticeXP FPGAs Secure Your Scheme Allows Devices Design To Be Locked – Secures SRAM and FLASH – Erasing memory is only allowable operation 0100101 – 0.13um technology and 9 01101101001 metal layers makes probing next to impossible 0110110100111010010101 ♦ Specify Secure Mode in ispLever or ispVM SRAM FPGAs Expose Your Intellectual Property At Power Up Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-33
  • 34. LatticeXP Benefits Self-Configuration in Under A Millisecond • Ideal for system “heartbeat” control logic • Supports configuration “scrubbing” for SEU control • Supports rapid power cycling Single Chip High Security • Simplify design • Security bits prevent readback • Reduced PCB footprint • No exposed power-up bitstream • Save boot PROM costs 3.3, 2.5, 1.8 or 1.2V SRAM + FLASH On-Chip Regulation • Support legacy applications • TransFR (TFR) technology with latest technology enables in field updates - Reduce costs while system operates - Improve performance Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-34
  • 35. LatticeXP Family Device XP3 XP6 XP10 XP15 XP20 LUTs (K) 3.1 5.8 9.7 15.4 19.7 sysMEM Blocks 6 8 24 36 44 sysMEM (Kbits) 54 72 216 324 396 Distributed RAM (Kbits) 12 23 39 61 79 Voltage (V) 1.2/1.8/2.5/3.3V PLLs 2 2 4 4 4 Package I/O Combinations 100-pin TQFP (14x14mm) 62 RoHS 144-pin TQFP (20x20mm) 100 100 208-pin PQFP (28x28mm) 136 142 256-ball fpBGA (17x17mm) 188 188 188 188 388-ball fpBGA (23x23mm) 244 268 268 484-ball fpBGA (23x23mm) 300 340 Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-35
  • 36. Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-36
  • 37. MachXO Key Features ♦ Non-Volatile Solution – Single chip, instant-on, high security ♦ TransFR for Simple Logic Updates ♦ High Performance – 3.5ns pin-to-pin ♦ LUT Based Flexibility – 256 to 2,280 LUT4s – 2K to 8K bits distributed memory ♦ I/O Intensive – 78 to 271 I/O ♦ Flexible sysIOTM Buffers – LVCMOS 33/25/18/15/12, LVDS, PCI ♦ sysMEMTM Block Memory – Up to 28K bits of memory ♦ sysCLOCKTM PLLs LUT Flexibility ♦ On-Chip Oscillator ~20MHz Non-Volatility ♦ Low Power Sleep Mode Embedded Memory ♦ 1.2/1.8/2.5/3.3V Power Supply Options Performance Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-37
  • 38. MachXO Family Members Device MachXO 256 MachXO 640 MachXO 1200 MachXO 2280 LUTs 256 640 1200 2280 Distributed RAM (KBits) 2 6.1 6.4 7.7 EBR SRAM (KBits) 0 0 9.2 27.6 # EBR SRAM Blocks (9Kb) 0 0 1 3 VCC Voltage 1.2/1.8/2.5/3.3V Number of PLLs 0 0 1 2 Max I/O 78 159 211 271 LVDS Pairs -- -- 27 33 Packages: 100-TQ (14X14) 78 74 73 73 144-TQ (20X20) 113 113 113 csBGA 100 (8X8) 78 74 csBGA 132 (8X8) 101 101 101 ftBGA 256 (17X17) 159* 211 211 ftBGA 324 (19X19) 271 csBGAs Ideal RoHS RoHS Compliant / for Space- Lead Free Versions Constrained Applications Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-38
  • 39. ispGDX2 Features • High Performance Switching In-system programmable (ISP) 38Gbps* switch and associated control logic optimized for bus switching. • 3.0ns pin-to-pin, 360MHz fMAX (Toggle) • sysCLOCKTM PLL Up to four PLLs to modify timing to match system for optimum performance. • High Performance Interfacing Advance sysIOTM capability supports multiple advance I/O standards • Up to 8 sysHSITM providing 16 800 Mbps Duplex SERDES channels *256 I/O (128 Rx, 128 Tx) with data lines running at 300MHz Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-39
  • 40. ispGDX Concept Buffers & SERDES Buffers & SERDES Programmable I/O Programmable I/O Flexible Interconnect ispGDX – Programmable Interface and Interconnect ♦ Allows Integration of Multiple Buffers and Interface Chips – Cost and board space savings ♦ Provides Time to Market Benefits of Programmability – No board re-spins to modify connections or change I/O characteristics Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-40
  • 41. ispGDX2 Block Diagram: Top Level 1532 JTAG, 1532 sysIOs for sysIO Block sysIO Block JTAG isp isp Interface Advance Interface SERDES sysHSI SERDES sysIO Block sysIO Block FIFO FIFO 10-320MHz GDX BLOCK GDX BLOCK GDX Block sysCLOCK includes Control PLL Logic and Global Routing Multiplexors PLL PLL Pool (GRP) Flexible routing Optimized for sysIO Block sysIO Block Bus Switching GDX BLOCK GDX BLOCK FIFO FIFO sysHSI Block Duplex SERDES SERDES sysHSI SERDES FIFOs for 800Mbps LVDS Buffering Support Data streams sysIO Block sysIO Block 15X10 bits ispGDX2-64 shown Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-41
  • 42. Power Manager II Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-42
  • 43. What is Power Management? Power Management Is the Implementation of One or More Of These Functions in a Circuit Board Hot-swap / Soft Start - Add-in Circuit Boards Sequencing/ Tracking - Power Up / Down - Boards Using MultiVoltage ICs Microprocessor Reset - Boards Using Microprocessor Generation Supervisor (Supply Fault Detection), Interrupt - Boards Using Microprocessor Processor Trimming / Margining - High Reliabilty Equipment Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-43
  • 44. Power Manager II Offers Integrated Solution! Hot-swap / Soft Start All Power Management Functions on One Chip! Sequencing/ Tracking - Power Up / Down Microprocessor Reset Generation Supervisor (Supply Fault Detection), Interrupt Processor Trimming / Margining Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-44
  • 45. … Replaces Competing Power Management Devices ♦ Advantages – Increased Flexibility – Higher Accuracy – Software Based Power Management Design – Reduced Part Count Improves… » Inventory Management » Reliability Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-45
  • 46. Power Manager II Beats Competition Analog Summit Lattice Lattice Devices Advantages of Lattice Over Manufacturer SMM6XX, Power1220AT8 Power1014/A ADM1062, Competition SMM7XX 1066, 1067 Analog Inputs 12 10 10 6 More Analog Inputs Window Compares Programmable Programmable Programmable Sampled Type Monitoring Comparator Comparator Comparator Through ADC Fastest Fault Identification (16 us) (16 us) (20 us) (2-12 ms) Monitoring Accuracy Across 0.7% 0.7% 1% 0.75% Highest Precision Temperature and Process Digital Inputs 6 - Programmable 4 - Programmable 0 0 Most Digital Inputs Number of MOSFET Drivers 4 - Programmable 2 - Programmable 6-fixed NO Multiple MOSFET Control Number of Digital Outputs 20 14 10 6 Most Digital Outputs Power Management Algorithm 48 M/C CPLD 24 M/C CPLD 10 Macrocells NO Most Flexible (CPLD) Number of Trimming and 8 None 6 6 Maximum Number of Trimming Outputs Margining Controls SMBus Factory Programming interface JTAG JTAG 2 JTAG is the Preferred Method of Programming (I C Compatible) Programmed I2C Interface Yes Yes Yes Yes Most Flexible Support of Microprocessors Advanced PAC Advanced PAC PAC-Designer Provides the Best Software Software Designer with Designer with Primitive Primitive Interface LogiBuilder LogiBuilder Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-46
  • 47. Lattice solution - Cable Modem Functions Performed Lattice Advantages •Memory controller performance of •Low-cost solution for cost-sensitive greater than 200MHz (400Mbps application DDR) •Reconfigurability results in rapid •Memory controller supports data development and reduced time-to-market widths of 16, 32 and 64 Bits •Programmable flexibility to support •Interface to USB/Fast Ethernet on changing standards user side, DOCSIS MAC on line •Existing IP speeds deployment to market side Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-47
  • 48. Lattice solution - Set-Top Boxes Functions Performed Lattice Advantages •Memory Controller •5-volt tolerant with high-performance: 2.5 •Clock distribution and system timing ns Tpd, 400 MHz Fmax •IrDA Controller function receives data •Low-cost and reduced time to market for from the remote control initial and follow-on derivative products •Peripheral Controller to control •Flexibility to support changing standards interfaces like Ethernet, UBS, RS232, and feature upgrades/additions through etc. field reprogrammability •System bug fixes •Larger devices support higher system integration Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-48
  • 49. Lattice solution - Set-Top Boxes Functions Performed I/O Controller Lattice Advantages •High performance interfacing and switching •Connect to virtually any system interface •I/O intensive: 64 to 256 I/Os •I/O Control using standard interfaces such as LVCMOS, HSTL, SSTL, etc. Functions Performed •Forward Error Correction (FEC) decoding •MPEG-2 Decoding •NTSC/ PAL Encoding Lattice Advantages •Reduced time to market for initial and follow on products •Add features remotely to box installed in home •Larger devices (>10K logic elements) support higher integration Functions Performed Power and smart battery management Lattice Advantages •CPLD provides efficient implementation of sequencing, monitoring and supervisory signal logic •Programmable analog input thresholds monitor power supply voltages •Programmable delay timers (32µs to 512ms) provide flexible timing control •Internal 250 kHz oscillator provides on-chip clock generation Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-49
  • 50. Lattice solution - VoIP and WLAN DSL Modem Residential Gateway Functions Performed Lattice Advantages •10/100 MAC •Lowest Cost FPGA Solution •Memory Controller •Density and Packages Targeted for High Volume Applications •Power Management •Embedded and Distributed Memory •Network Interface •Popular IO Interfaces Support, Including LVDS and DDR •Clock Generator •Embedded PLLs Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-50
  • 51. Lattice solution - Smart Card Reader Functions Performed •Keypad and Fingerprint Interface and decoding •Smart Card Reader •LCD Display Control •Security Decoding •Network Interface Lattice Advantages •Instant-On: Powers up in microseconds via on-chip E2CMOS based memory •Excellent design security, no bit stream to intercept •Reduced time to market for initial and follow-on derivative products •Flexibility to support changing standards through field reprogrammability Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-51
  • 52. Lattice IPTV solution – Summary Devices Used XP ECP2 Power Manager ispGDX2 MachXO Functions Performed Clock distribution and system timing IrDA Controller function receives data from the remote control Peripheral Controller to control interfaces like Ethernet, UBS, RS232, etc. System bug fixes Keypad and Fingerprint Interface and decoding Smart Card Reader LCD Display Control Security Decoding Network Interface 10/100 MAC Power Management Memory controller performance of greater than 200MHz (400Mbps DDR) Memory controller supports data widths of 16, 32 and 64 Bits Interface to USB/Fast Ethernet on user side, DOCSIS MAC on line side Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-52
  • 53. Lattice IPTV solution – Summary Lattice Advantages •Reconfigurability results in rapid development and reduced time-to-market •Existing IP speeds deployment to market •Low-cost and reduced time to market for initial and follow-on derivative products •Larger devices support higher system integration •High performance interfacing and switching •Connect to virtually any system interface •I/O Control using standard interfaces such as LVCMOS, HSTL, SSTL, etc. •Add features remotely to box installed in home •Larger devices (>10K logic elements) support higher integration •Programmable analog input thresholds monitor power supply voltages •Density and Packages Targeted for High Volume Applications •Embedded and Distributed Memory •Embedded PLLs •Instant-On: Powers up in microseconds via on-chip E2CMOS based memory •Excellent design security, no bit stream to intercept Copyright © Lattice Semiconductor 2003 Bringing the Best Together Slide Ref LO-53