Programs of VHDL

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This file is according to the syllabus of VHDL lab manual of Kurukshetra University, Kurukshetra.

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Programs of VHDL

  1. 1. 1Program No. 1Aim: Write a VHDL program to implement a 3:8 decoder.Truth Table:A B C EN D0 D1 D2 D3 D4 D5 D6 D70 0 0 1 1 0 0 0 0 0 0 01 0 0 1 0 0 0 0 1 0 0 10 1 0 1 0 0 1 0 0 0 0 01 1 0 1 0 0 0 0 0 0 1 00 0 1 1 1 0 0 0 0 0 0 01 0 1 0 0 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0 10 0 0 1 1 0 0 0 0 0 0 0Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity decoder isPort ( A : in STD_LOGIC;B : in STD_LOGIC;C : in STD_LOGIC;EN : in STD_LOGIC;D : out STD_LOGIC_VECTOR (0 to 7));end decoder;
  2. 2. 2architecture Behavioral of decoder isbeginprocess(A,B,C,EN)variable ABAR,BBAR,CBAR:STD_LOGIC;beginABAR :=NOT A;BBAR :=NOT B;CBAR :=NOT C;if EN=1 thenD(0)<= ABAR AND BBAR AND CBAR;D(1)<= ABAR AND BBAR AND C;D(2)<= ABAR AND B AND CBAR;D(3)<= ABAR AND B AND C;D(4)<= A AND BBAR AND CBAR;D(5)<= A AND BBAR AND C;D(6)<= A AND B AND CBAR;D(7)<= A AND B AND C;elseD <= "00000000";end if;end process;end Behavioral;
  3. 3. 3RTL Logic:Output Waveform:Result: VHDL Program of a 3 :8 decoder has been implemented
  4. 4. 4Program No. 2Aim: Write a VHDL program to implement an 8:1 multiplexer.Truth Table:S0 S1 S2 A0 A1 A2 A3 A4 A5 A6 A7 Z0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 1 00 1 0 1 0 0 0 1 0 1 0 01 1 0 1 1 1 1 1 1 1 0 10 0 1 1 0 1 1 0 1 1 1 01 0 1 0 0 1 0 1 1 1 0 10 1 1 1 1 1 0 1 0 1 0 01 1 1 1 0 1 1 1 0 0 1 10 0 0 1 0 1 1 0 1 0 1 1Program:-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating
  5. 5. 5---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Ramkrishna_MUX isPort ( A : in STD_LOGIC_VECTOR (0 to 7);S : in STD_LOGIC_VECTOR (0 to 2);Z : out STD_LOGIC);end Ramkrishna_MUX;architecture Behavioral of Ramkrishna_MUX isbeginprocess (S,A) isbegincase S iswhen "000" => Z<=A(0);when "001" => Z<=A(1);when "010" => Z<=A(2);when "011" => Z<=A(3);when "100" => Z<=A(4);when "101" => Z<=A(5);when "110" => Z<=A(6);when "111" => Z<=A(7);when others => Z<=X;end case;end process;end Behavioral;
  6. 6. 6RTL Logic:Output Waveform:Result: VHDL Program of 8:1 multiplexer has been implemented using behavioralmodeling.
  7. 7. 7Program No: 3Aim:- To write a VHDL program to implement a 1:8 demultiplexer.Truth Table:-A S2 S1 S0 Z0 Z4 Z2 Z6 Z1 Z5 Z3 Z70 0 0 0 0 0 0 0 0 0 0 01 1 0 0 - 1 1 1 1 1 1 10 0 1 0 - - 0 0 0 0 0 01 1 1 0 - - - 1 1 1 1 10 0 0 1 - - - - 0 0 0 01 1 0 1 - - - - - 1 1 10 0 1 1 - - - - - - 0 01 1 1 1 - - - - - - - 1Program:-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity DEMUX isPort ( A : in STD_LOGIC;S : in STD_LOGIC_VECTOR(0 TO 2);Z : out STD_LOGIC_VECTOR(0 TO 7));end DEMUX;architecture Behavioral of DEMUX isBEGIN
  8. 8. 8PROCESS(A,S)BEGINCASE S ISWHEN "000"=>Z(0)<=A;WHEN "001"=>Z(1)<=A;WHEN "010"=>Z(2)<=A;WHEN "011"=>Z(3)<=A;WHEN "100"=>Z(4)<=A;WHEN "101"=>Z(5)<=A;WHEN "110"=>Z(6)<=A;WHEN "111"=>Z(7)<=A;WHEN OTHERS=>Z<="XXXXXXXX";END CASE;END PROCESS;end Behavioral;
  9. 9. 9RTL Diagram:-Output Waveform:-Result: A VHDL Program of 1 :8 demultiplexer has been implemented by behavioralmodeling.
  10. 10. 10Program No. 4Aim: Write a VHDL program to implement 4-bit addition/subtraction.Truth Table:Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity BIT_ADDER_SUB isPort ( A : in STD_LOGIC_VECTOR (3 downto 0);B : in STD_LOGIC_VECTOR (3 downto 0);M : in STD_LOGIC;C_IN : inout STD_LOGIC;C_OUT : out STD_LOGIC;S : out STD_LOGIC_VECTOR (3 downto 0));end BIT_ADDER_SUB;A0 A1 A2 A3 B0 B1 B2 B3 M CIN COUT S0 S1 S2 S30 1 0 0 0 0 0 0 1 1 1 0 1 0 00 0 1 0 1 0 0 0 0 0 0 1 1 0 00 1 1 0 1 1 0 0 1 1 1 1 0 0 00 0 0 1 1 0 1 0 0 0 0 1 1 1 00 1 0 1 1 1 1 0 1 1 1 1 0 0 00 0 1 1 1 0 0 1 0 0 0 1 1 1 1
  11. 11. 11architecture Behavioral of BIT_ADDER_SUB isbeginPROCESS(A,B,M,C_IN)VARIABLE C:STD_LOGIC_vector(0 to 3);VARIABLE B0BAR,B1BAR,B2BAR,B3BAR:STD_LOGIC;BEGINC_IN<=M;B0BAR:=NOT B(0);B1BAR:=NOT B(1);B2BAR:=NOT B(2);B3BAR:=NOT B(3);IF M=0 THENC(0):=((A(0)AND B(0))OR (A(0)AND C_IN)OR (B(0) AND C_IN));C(1):=((A(1) AND B(1)) OR (A(1) AND C(0)) OR (B(1) AND C(0)));C(2):=((A(2) AND B(2)) OR (A(2) AND C(1)) OR (B(2) AND C(1)));S(0)<=(A(0)XOR B(0) XOR C_IN);S(1)<=(A(1) XOR B(1) XOR C(0));S(2)<=(A(2) XOR B(2) XOR C(1));S(3)<=(A(3) XOR B(3) XOR C(2));C_OUT<=((A(3) AND B(3))OR (A(3) AND C(2)) OR (B(3) AND C(2)));ELSEC(0):=((A(0) AND B0BAR)OR (B0BAR AND C_IN)OR (A(0) AND C_IN));C(1):=((A(1) AND B1BAR)OR (B1BAR AND C(0))OR (A(1) AND C(0)));C(2):=((A(2) AND B2BAR) OR (B2BAR AND C(1)) OR (A(2) AND C(1)));S(0)<=(A(0) XOR B0BAR XOR C_IN);S(1)<=(A(1) XOR B1BAR XOR C(0));S(2)<=(A(2) XOR B2BAR XOR C(1));S(3)<=(A(3) XOR B3BAR XOR C(2));
  12. 12. 12C_OUT<=((A(3)AND B3BAR) OR (B3BAR AND C(2)) OR (A(3) AND C(2)));END IF;END PROCESS;end Behavioral;
  13. 13. 13RTL Logic:Output Waveform:Result: VHDL Program to implement 4 bit addition/subtraction have been studied.
  14. 14. 14Program No: 5Aim: Write a VHDL program to implement a 4-bit comparator.Truth Table:A0 A1 A2 A3 B0 B1 B2 B3 AGB AEB ALB0 0 0 0 0 0 0 0 0 1 01 1 1 0 1 0 0 1 1 0 00 1 0 0 0 0 0 1 1 0 01 0 0 1 1 0 0 1 0 1 00 1 0 1 1 0 1 0 0 0 10 0 1 1 1 1 1 0 0 0 11 0 1 0 1 0 1 0 0 1 01 1 1 0 1 0 0 1 1 0 00 1 1 0 1 0 0 0 0 0 1Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity COMPARATOR isPort ( A : in STD_LOGIC_VECTOR (0 to 3);B : in STD_LOGIC_VECTOR (0 to 3);AGB : out STD_LOGIC;AEB : out STD_LOGIC;ALB : out STD_LOGIC);end COMPARATOR;
  15. 15. 15architecture Behavioral of COMPARATOR isbeginPROCESS(A,B)BEGINIF A>B THENAGB <=1;AEB <=0;ALB <=0;ELSIF A=B THENAGB<=0;AEB<=1;ALB<=0;ELSIF A<B THENAGB<=0;AEB<=0;ALB<=1;END IF;END PROCESS;END BEHAVIORAL;
  16. 16. 16RTL Logic:Output Waveform:Result: A VHDL Program of 4 bit comparator has been implemented.
  17. 17. 17Program No: 6Aim: Write a VHDL program to implement MOD-10 counter.Truth Table:SLOAD CLR Q0 Q1 Q2 Q31 1 0 0 0 01 0 0 0 0 11 0 0 0 1 01 0 0 0 1 11 0 0 1 0 01 0 0 1 0 11 0 0 1 1 01 0 0 1 1 11 0 1 0 0 01 0 1 0 0 11 0 0 0 0 01 0 0 0 0 1Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
  18. 18. 18---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity MOD_10 isPort ( CLK : in STD_LOGIC;SLOAD : in STD_LOGIC;CLR : in STD_LOGIC;Q : out STD_LOGIC_VECTOR (0 to 3));end MOD_10;architecture Behavioral of MOD_10 isSIGNAL TEMP:STD_LOGIC_VECTOR(0 TO 3);beginPROCESS (CLK) ISBEGINIF (CLKEVENT AND CLK=1) THENIF CLR=1 THENTEMP <= "0000";ELSIF SLOAD =1 THENIF TEMP="1001" THENTEMP<= "0000";ELSE TEMP<=TEMP+"0001";END IF;END IF;END IF;END PROCESS;Q<=TEMP;END BEHAVIORAL;
  19. 19. 19RTL Logic:Output Waveform:Result: A VHDL Program to generate Mod- 10 up counter has been implemented.
  20. 20. 20Program No. 7Aim: To write a VHDL program to generate the 1010 sequence detector.Truth Table:X Z0 00 00 00 01 00 01 00 10 00 00 0Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity SEQ_DETECTOR isPort ( X : in STD_LOGIC;
  21. 21. 21CLK : in STD_LOGIC;Z : out STD_LOGIC);end SEQ_DETECTOR;architecture Behavioral of SEQ_DETECTOR isTYPE STATE_TYPE IS (S0,S1,S2,S3);SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;BEGINPROCESS(CURRENT_STATE,X)beginCASE CURRENT_STATE ISWHEN S0=>IF X=0 THENZ<=0;NEXT_STATE<= S0;ELSIF X=1 THENZ<=0;NEXT_STATE <=S1;ELSEZ<=0;NEXT_STATE <=S0;END IF;WHEN S1=>IF X=0 THENZ<=0;NEXT_STATE <= S2;ELSIF X=1 THENZ<=0;NEXT_STATE <=S1;ELSE Z<= 0;
  22. 22. 22NEXT_STATE <=S0;END IF;WHEN S2=>IF X=0 THENZ<=0;NEXT_STATE<= S0;ELSIF X=1 THENZ<=0;NEXT_STATE<=S3;ELSEZ<=0;NEXT_STATE <=S0;END IF;WHEN S3=>IF X=0 THENZ<=1;NEXT_STATE<= S1;ELSIF X=1 THENZ<=1;NEXT_STATE<=S0;ELSE Z<=0;NEXT_STATE<=S0;END IF;END CASE;WAIT UNTIL CLK=1AND CLKEVENT;CURRENT_STATE<=NEXT_STATE;END PROCESS;end Behavioral;
  23. 23. 23RTL Logic:Output Waveform:Result: A VHDL Program to generate the 1010 sequence detector has been studied.
  24. 24. 24Program No. 8Aim: To write a VHDL program to perform serial to parallel transfer of 4-bit binary number.Truth Table:CLR PR DIN Y(0) Y(1) Y(2) Y(3)1 1 1 - - - -1 1 0 1 - - -1 1 1 0 1 - -1 1 0 1 0 1 -1 1 1 0 1 0 11 1 0 1 0 1 01 1 1 0 1 0 11 1 0 1 0 1 01 1 1 0 1 0 1Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity SIPO isPort ( D : in STD_LOGIC;CLR : in STD_LOGIC;CLK : in STD_LOGIC;
  25. 25. 25PR : in STD_LOGIC;Y : out STD_LOGIC_VECTOR(0 TO 3));end SIPO;architecture Behavioral of SIPO isSIGNAL A:STD_LOGIC_VECTOR(0 TO 3);beginPROCESS(CLR,CLK,PR,D)BEGINIF(CLR=1 AND PR=1 AND CLK=1 AND CLKEVENT)THENA(0)<=D;A(1)<=A(0);A(2)<=A(1);A(3)<=A(2);Y<=A;ELSIF(CLR=1 AND PR=0)THENY<="1111";ELSIF (CLR=0 AND PR=1)THENY<="0000";END IF;END PROCESS;end Behavioral;
  26. 26. 26RTL LOGIC:Output Waveform:Result: A VHDL program of serial to parallel transfer of 4 bit binary number has beenverified.
  27. 27. 27Program No. 9Aim: To write a program to perform parallel to serial transfer of 4-bit binarynumber.Truth Table:Din Clk Load Dout0 1 1 -0 0 0 01 1 1 01 0 0 12 1 1 02 0 0 23 1 1 03 0 0 3Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity PISO isPort ( din : in STD_LOGIC_VECTOR (3 downto 0);load_shtbar : in STD_LOGIC;clk : in STD_LOGIC;dout : out STD_LOGIC);
  28. 28. 28end PISO;architecture Behavioral of PISO issignal sr_bit:std_logic_vector(3 downto 0):="0000";beginprocess(clk)beginif (clk=1 and clkevent)thenif(load_shtbar =1)thensr_bit <=din;elsesr_bit<=0& sr_bit(3 downto 1);end if;dout<=sr_bit(0);end if;end process;end Behavioral;
  29. 29. 29RTL Logic:Output WaveformResult: A VHDL program of parallel to serial transfer of 4 bit binary number has beenverified.
  30. 30. 30Program No: 10Aim: Write a VHDL program to implement BCD to Seven segmentsDecoder.Truth Table:BCD0BCD1BCD2BCD3LED0LED1LED2LED3LED4LED5LED60 0 0 0 0 1 1 1 1 1 11 0 0 0 1 1 1 1 1 1 10 1 0 0 1 1 0 0 1 1 01 1 0 0 0 0 0 0 0 0 00 0 1 0 1 0 1 1 0 1 11 0 1 0 0 0 0 0 0 0 00 1 1 0 1 1 1 1 1 0 11 1 1 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 1 0Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity BCD_7SEGMENT isPort ( BCD : in STD_LOGIC_VECTOR (3 downto 0);LED : out STD_LOGIC_VECTOR (6 downto 0));
  31. 31. 31end BCD_7SEGMENT;architecture Behavioral of BCD_7SEGMENT isBEGINPROCESS(BCD)ISbeginCASE BCD ISWHEN "0000"=>LED<="1111110";WHEN "0001"=>LED<="0110000";WHEN "0010"=>LED<="1101101";WHEN "0011"=>LED<="1111001";WHEN "0100"=>LED<="0110011";WHEN "0101"=>LED<="1011011";WHEN "0110"=>LED<="1011111";WHEN "0111"=>LED<="1110000";WHEN "1000"=>LED<="1111111";WHEN "1001"=>LED<="1111011";WHEN OTHERS=>LED<="0000000";END CASE;END PROCESS;end Behavioral;
  32. 32. 32RTL Logic:Output Waveform:Result: A VHDL Program of BCD to SEVEN SEGMENT display has beenimplemented.
  33. 33. 33Program No. 11Aim: Write a program to convert 8 bit vector into an integer.Truth Table:Program:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity CONVERTOR isPort ( A : in BIT_VECTOR (0 to 7);OP : out INTEGER RANGE 0 to 255);end CONVERTOR;A3 A2 A1 A0 S0 S1 S2 S3 S4 S5 S60 0 0 0 0 1 1 1 1 1 10 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 0 0 1 1* * * * 0 1 1 1 1 1 1
  34. 34. 34architecture Behavioral of CONVERTOR isIMPURE FUNCTION CONV(X:BIT_VECTOR(0 TO 7))RETURN INTEGER ISVARIABLE T:INTEGER;beginT:=0;FOR I IN 0 TO 7 LOOPIF A(I)=1 THENT:=T+2**I;END IF;END LOOP;RETURN T;END FUNCTION CONV;BEGINOP<=CONV(A);end Behavioral;
  35. 35. 35RTL Logic:WAVEFORM:RESULT: A program to convert 8 bit vector into an integer have been studied.

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