CMOS VLSI Design Technology, and Future Trends Piyush kumar Final yr.(ece dept.)
Cmos technology overview
Basic MOSFET operation
Basic n-well process
A study of VLSI impact on nanotechnology
Advanced depleted substrates
Integrated cmos tansisters
Limitation of trigate transisters
CMOS TECHNOLOGY OVERVIEW Complementary-symmetry / metal-oxide-semiconductor (CMOS) is a major class of integrated circuits. CMOS chips include microprocessor, microcontroller, static RAM, and other digital logic circuits. The words “complementary-symmetry” refers to the fact that the design uses symmetrical pairs of p-type and n-type MOSFET transistors for logic functions, only one of which is switched on at any time (Figure 1.)
V g > V t : I d = ∞ “on-current”
V g < V t : I d = 0 “off-current”
Basic N Well CMOS technology
A Study of VLSI Technology and Impact on Nanotechnology
This study of the introduces to VLSI technological aspects, importance and their replacement or combination with the Nanotechnology in the VLSI world of silicon semiconductors. Here authors bring out the nanotechnology in Silicon world which invariably means shrinking geometry of CMOS devices to nano scale .
I . Nanotechnology and CAEN Chemically assembled electronic Nanotechnology (CAEN), a form of electronic nanotechnology (EN), that uses Self-alignment to construct electronic circuits out of Nanometer-scale devices. CAEN devices are a promising alternative to CMOS-based devices; particularly CMOS based reconfigurable devices . Following International Technology Roadmaps for Semiconductor (ITRS), advanced silicon foundries are manufacturing a full spectrum of integrated-circuit products down to 90-nm technology node today. A few companies like IBM and INTEL have launched a few chips using 65 nm technologies, eg. Quad core processor using 65nm  . At this stage, many of the device characteristics are no longer a straightforward extension of past generations. Scaling is beyond simple shrinking of 3D physical dimensions of devices.
II. WAFERS in Nano CHIPS A study of the documents from the research labs and marketing organization around the world reveal that concept of Silicon wafers is undergoing a change slowly with the SOI and other chips. If CMOS Nanotechnology is to be replaced by CAEN, the availability of wafer spectrum for research wi; be aswide as follows: A. SOI Wafers SOI: silicon on insulator 2” SOIP(100) 500anstrom Si layer 4” SOINor P (100) Device 2-4 m SOI layer diameter: 200mm crystal orientation: <100> 4 deg off-axis Dopant: N type (Phosphor) SOI layer thickness: 3.0um III. Nano wires and Interconnects Stochastically assembled nanoscale architectures have the potential to achieve device densities 100 times greater than today's CMOS. A key challenge facing nanotechnologies is controlling parallel sets of nanowires (NWs)
IV. NANOTRANSISORS:- It is required to unerstand and study on the carrier transport theory to understand the electron conduction behavior in transistors smaller than 20-nm. In nano-scale transistors, the number of atoms in the active region is finite; the nature of random distribution of atoms in the active region causes fluctuation in device property and deteriorates the design margins for integration. Nonetheless, scientists and engineers in Foundry master the variability in device
Continuing Transistor Performance and Scaling Trends While Controlling Parasitic Leakages :-
The semiconductor industry continues to push technological innovation to keep pace with Moore’s Law, shrinking transistors so that ever more can be packed on a chip. However, at future technology nodes, the ability to shrink transistors becomes more and more problematic, in part due to worsening short channel effects and an increase in parasitic leakages with scaling of the gate-length dimension. Both transistor off-state leakage (which increases with reducing gate length dimension) and gate oxide leakage (which increases with decreasing gate dielectric thickness) are contributing to the increase in power dissipation.
1. Introduction: Moore’s Law
Elevating CMOS Transistor Design to Three Dimensions
Enhancing design through innovative integration For faster and cooler operation of the non-planar transistors, Intel further enhanced the tri-gate design by integrating it with several advanced semiconductor technologies . High-k/metal gate stack .. The tri-gate CMOS transistors use a high-k (dielectric constant) material to replace the transistor’s traditional silicon dioxide dielectric, and also replace the conventional polysilicon gate electrode with metal gate electrodes with workfunction close to the midgap. The use of the high-k/metal-gate stack reduces the gate oxide leakage compared to the standard SiO2/polysilicon gate stack . The use of metal electrodes eliminates polysilicon depletion and enhances transistor performance. In addition, the use of metal electrodes with close-to-midgap workfunctions also allows the reduction of substrate doping concentrations, thus enhancing transistor mobilities and hence overall transistor performance .
Improving Performance with Integrated Tri-Gate Transistors Intel demonstrated that integrated tri-gate NMOS and PMOS transistors showed excellent control of short channel effects (SCE), leading to reduced parasitic leakages and decreased power consumption.The tri-gate transistors also demonstrated higher performance, in terms of drive current, compared to an optimized, state-of-the-art planar 65nm-node transistor (see Figure 2 ). For a given transistor off-state leakage current (IOFF), the integrated tri-gate NMOS transistor had 30 percent higher drive current (IDSAT) than the planar transistor. This effect is even more pronounced for the integrated tri-gate PMOS transistor, which produced 60 percent higher IDSAT than the planar transistor at a given IOFF.
Limitations of Trigate Transisters:
V = u E ( E is small enough)
V = Vsat ( E is strong enough)
As Vgs increases , the drain current saturates well before pinch-off occurs
Biasing a nmos in subthreshold resgion, Vgs < Vth, Vds is large enough
To turn off the transistor, How much reduction of (Vgs-Vth) could lead to a small enough Id.
Subthreshold Swing S = d(Vgs)/d(log(Id))
Bad Subthreshold Swing will result in higher off-state current if the Vgs applied to turn off the transistor is the same.
DIBL: drain induced barrier lowering
DIBL =d(Vth)/d(Vds) Barrier lowering increases as channel length is reduced, even at zero applied drain bias.
To reduce short channel effects, we need to reduce Xd(channel depletion layer thickness), Xj( Junction depletion width),Tox (oxide layer thickness under gate) So we will use an special type of FET called FINFET
Application: A New High Speed CMOS Camera for Real-Time Tracking Applications : There are many potential applications for very high-speed vision sensors in robotics. Maybe tracking is the most obvious one. The main idea of this paper is to combine existing standard technology (CMOS imaging sensors The performance of this new camera is on one hand limited by the maximum pixel clock of the sensor, on the other hand by the USB 2.0 micro frame timing and bandwidth constraints.
CONCLUSION The goal was to study the various materials used in VLSI technology. The study reveals that present scaling of the CMOS technology to nano dimensions will have to limit at some point and make further scaling may be impossible while retaining all the electrical characteristics of the devices .