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Ece projects2011
 

Ece projects2011

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    Ece projects2011 Ece projects2011 Document Transcript

    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098 FINAL Year IEEE and Non- IEEE Projects List VLSI & MATLABFor any Enquires or Detailed Descriptions Just Contact us @E-mail id : hdproject.you@gmail.comMobile No : 9445 962 098 If you have any own ideas to implement in VLSI or MATLAB forward your paper or Specifications to our mail. We will describe you about the possibilities of your idea.
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098INNOVATIVE PROJECTS: • Design and VLSI implementation of hardware used for animating the real time video signal. Video Signal FPGA Board Display (Camera or (Animated DVD Player) video) • FPGA implementation of Real time edge extraction. Edge Video Signal FPGA Board detected Video Signal (Camera or DVD Player) • FPGA implementation of piano based on PS/2 interface PS/2 interface FPGA Board Speaker COMPUTER KEYBOARD
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• VLSI implementation of music synthesizer. Microphone (Voice input) FPGA Board Karaoke Audio input Machine Speaker• NIOS II processor based guitar player Hardware Verilog Code FPGA Board Nios II soft-core processor ( C Speaker code)• Sixth generation camera for next generation painting. Camera FPGA Board VGA Display (Image segmentation) Painting Finger Movement
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• Real Time Tracking motion of Light using FPGA Camera FPGA Board VGA Display Light source Speaker• Generation of 2D fractal landscape and its 3D projection using FPGA. 2D-image FPGA Board VGA Display Image Angle of Rotation ( 3D rotation view)
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• Design and Implementation of NIOS-II Processer based SD card Wav Player.• Implementation of Real time operating System (RTOS) (μC/OS-II) on NIOS -II processer using FPGA.• Real time adoptive noise cancellation of voice input through Microphone.• FPGA Implementation of Picture-in-Picture(PIP). Video Signal-1 FPGA Board Display (PIP) Video Signal-2• Design and Implementation of LCD Touch screen panel using Nios-II processer.
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098IEEE PROJECT TITLES -VLSI & MATLAB • Muti-Carrier CDMA Overview with BPSK Modulation In Rayleigh Channel • Analysis and comparison of RLS adaptive filter in signal De- noising • Vlsi implementation of nonlinear variable cutoff high pass filter algorithm • Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm • Efficient Pattern Matching Algorithm for Memory Architecture • A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems • FPGA Implementation Of A Pipelined 2D-DCT And Simplified Quantization For Real-Time Applications • Implementation of Convolutional Encoder and Viterbi Decoder using Verilog HDL • Interference Cancellation and Detection for More than Two Users • A High-Throughput LDPC Decoder Architecture With Rate Compatibility • A Fast Reed-Solomon Decoder Using Step-by-Step Algorithm • Design of CORDIC IP Compiler
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• Memory based architecture to implement simplified block LMS algorithm on FPGA• Simulation and implementation of a BPSK modulator on FPGA• Implementation of 1024-Point FFT Algorithm Based on FPGA• FPGA-based MIMO testbed for LTE applications• A FPGA IEEE-754-2008 decimal64 Floating-Point adder/sub tractor.• High-Performance FPGA Implementation of Discrete Wavelet Transform for Image Processing• MEMOCODE 2011 Hardware/Software CoDesign Contest:NoC Simulator• Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers• FFT implementation on a streaming architecture• Word-length Optimization of A Pipelined FFT Processor• Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing• FPGA Implementation of AES Algorithm for secured data transfer• High-Speed & Memory Efficient 2-D DWT on Xilinx Spartan3A DSP using scalable Polyphase Structure with DA for JPEG2000 Standard
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• FPGA-Implementation of Wavelet-based Denoising Technique to Remove Power-Line Interference from ECG Signal• ECG signals denoising using neighbouring coefficients• Fast Double-Parallel image processing based on FPGA• Method of removing noise from EEG signals based on HHT method1• Wavelet-Based Eeg Denoising For Automatic Sleep Stage Classification• Design and Verification of Distributed RAM Using Look-Up Tables in an SOI-Based FPGA• VHDL Implementation of High Performance RC6 Algorithm Using Ancient Indian Vedic Mathematics• A Method of Real-time Edge Detection using FPGA• A New Hardware Efficient Reconfigurable FIR Filter Architecture Suitable For FPGA Applications• Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers• A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• A Novel Method for Converting the N-point Complex Sequence of Frequency-Domain to 2N-Point Real Sequence of Time-Domain with N-Point IFFT Computation• Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms• FPGA Implementation of JPEG-LS Compression Algorithm for Real Time Applications• An Efficient Distributed Arithmetic based VLSI Architecture for DCT• An Optimized Architecture To Perform Image Compression And Encryption Simultaneously Using Modified DCT Algorithm• Area-Efficient Multipliers Based on Multiple-Radix Representations• On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers• Implementation of a Reconfigurable Architecture of Discrete Wavelet Packet Transform with Three Types of Multipliers on FPGA• Design Of Low Power And High Speed Configurable Booth Multiplier• A Novel High-Speed Parallel Sorting Algorithm Based on FPGA• Fast Technique for Noninvasive Fetal ECG Extraction
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• The Performance of Turbo codes for Wireless Communication Systems• an automated vessel segmentation of retinal images using multiscale vesselness• Peak to Average Power Ratio (PAPR) Reduction in OFDM for a WLAN network Using SLM Technique• A Novel Method for Person Authentication using Retinal Images• SEA, a Scalable Encryption Algorithm for Small Embedded Applications• Hardware/Software Co-Design of NLMS Adaptive Filters on FPGA• Distributed Arithmetic for FIR Filter implementation on FPGA• Design and Simulation of 60-order Filter Based on FPGA• Speech processing for makhraj recognition• A fully pipelined implementation of Monte Carlo based SSTA on FPGAs• General-Purpose FPGA Platform for Efficient Encryption and Hashing• Implementation of the AES Algorithm Using a Rfig urable Functional Unit• A New Modified Version of Advanced Encryption Standard Based Algorithm for Image Encryption
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• Matrix based Cryptographic Procedure for Efficient Image Encryption• High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications• FPGA Implementation of AES Algorithm• A 1.6GHz 16 16-bit Low-Latency Pipelined Booth Multiplier• Power Aware and High Speed Reconfigurable Modified Booth Multiplier• A Simple Radix-4 Booth Encoded Modulo 2n +1 Multiplier• Simulation and Implementation of a BPSK Modulator on FPGA• The Design of NCO based on CORDIC Algorithm and Implementation in FPGA• FPGA Implementation of a CORDIC-based Radix-4 FFT Processor for Real-Time Harmonic Analyzer• Low Power and Fast DCT Architecture Using Multiplier-Less Method• An Efficient Distributed Arithmetic based VLSI Architecture for DCT
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• FPGA Implementation Of A Pipelined 2D-DCT And Simplified Quantization For Real-Time Applications• Implementation of an Efficient DWT Using a FPGA on a Real- time Platform• An Efficient Implementation of a 2D DWT on FPGA• Multiprocessor real time edge detection using FPGA IP cores• Lane Detection using Steerable Filters and FPGA-based Implementation• Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms• Design and Implement of FFT Processor for OFDMA System Using FPGA• A Low Area FIR Filter For FPGA Implementation• A New Hardware Efficient Reconfigurable FIR Filter Architecture Suitable For FPGA Applications• Design of a Novel Adaptive FIR Filter Based on FPGA• Generalized Secure Hash Algorithm: SHA-X• An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
    • For any queries Contact us @ e-mail id : hdproject.you@gmail.com Mobile No : 9445 962 098• Implementation of distributed FIR digital filter on FPGA• Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA• Self-Programmable Multipurpose Digital Filter Design Based on FPGA• Multichannel SDRAM Controller Design For H.264/AVC Video Decoder• Implementing Rainbow Tables in High-end FPGAs for Super-fast Password Cracking• Prototyping Platform for Performance Evaluation of SHA-3 Candidates• General-Purpose FPGA Platform forficifent Encryption and Hashing• A Flexible Hardware Implementation of SHA-1 and SHA-2 Hash Functions• A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA blocks