Microcontroller Instruction Set
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  • 1. Instruction SetMicrocontroller Instruction SetFor interrupt response time information, refer to the hardware description chapter. (1)Instructions that Affect Flag Settings Instruction Flag Instruction Flag C OV AC C OV AC ADD X X X CLR C O ADDC X X X CPL C X Instruction Set SUBB X X X ANL C,bit X MUL O X ANL C,/bit X DIV O X ORL C,bit X DA X ORL C, bit X RRC X MOV C,bit X RLC X CJNE X SETB C 1Note 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.The Instruction Set and Addressing Modes Rn Register R7-R0 of the currently selected Register Bank. direct 8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)]. @Ri 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0. #data 8-bit constant included in instruction. #data 16 16-bit constant included in instruction. addr 16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64 Kbyte Program Memory address space. addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 Kbyte page of program memory as the first byte of the following instruction. rel Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. bit Direct Addressed bit in Internal Data RAM or Special Function Register. 0509A 2-71
  • 2. Instruction Set Summary 0 1 2 3 4 5 6 7 JBC JB JNB JC JNC JZ JNZ 0 NOP bit,rel bit, rel bit, rel rel rel rel rel [3B, 2C] [3B, 2C] [3B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] AJMP ACALL AJMP ACALL AJMP ACALL AJMP ACALL 1 (P0) (P0) (P1) (P1) (P2) (P2) (P3) (P3) [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] LJMP LCALL ORL ANL XRL ORL RET RETI 2 addr16 addr16 dir, A dir, A dir, a C, bit [2C] [2C] [3B, 2C] [3B, 2C] [2B] [2B] [2B] [2B, 2C] ORL ANL XRL JMP RR RRC RL RLC 3 dir, #data dir, #data dir, #data @A + DPTR A A A A [3B, 2C] [3B, 2C] [3B, 2C] [2C] ADD ADDC ORL ANL XRL MOV INC DEC 4 A, #data A, #data A, #data A, #data A, #data A, #data A A [2B] [2B] [2B] [2B] [2B] [2B] INC DEC ADD ADDC ORL ANL XRL MOV 5 dir dir A, dir A, dir A, dir A, dir A, dir dir, #data [2B] [2B] [2B] [2B] [2B] [2B] [2B] [3B, 2C] MOV INC DEC ADD ADDC ORL ANL XRL 6 @R0, @data @R0 @R0 A, @R0 A, @R0 A, @R0 A, @R0 A, @R0 [2B] MOV INC DEC ADD ADDC ORL ANL XRL 7 @R1, #data @R1 @R1 A, @R1 A, @R1 A, @R1 A, @R1 A, @R1 [2B] MOV INC DEC ADD ADDC ORL ANL XRL 8 R0, #data R0 R0 A, R0 A, R0 A, R0 A, R0 A, R0 [2B] MOV INC DEC ADD ADDC ORL ANL XRL 9 R1, #data R1 R1 A, R1 A, R1 A, R1 A, R1 A, R1 [2B] MOV INC DEC ADD ADDC ORL ANL XRL A R2, #data R2 R2 A, R2 A, R2 A, R2 A, R2 A, R2 [2B] MOV INC DEC ADD ADDC ORL ANL XRL B R3, #data R3 R3 A, R3 A, R3 A, R3 A, R3 A, R3 [2B] MOV INC DEC ADD ADDC ORL ANL XRL C R4, #data R4 R4 A, R4 A, R4 A, R4 A, R4 A, R4 [2B] MOV INC DEC ADD ADDC ORL ANL XRL D R5, #data R5 R5 A, R5 A, R5 A, R5 A, R5 A, R5 [2B] MOV INC DEC ADD ADDC ORL ANL XRL E R6, #data R6 R6 A, R6 A, R6 A, R6 A, R6 A, R6 [2B] MOV INC DEC ADD ADDC ORL ANL XRL F R7, #data R7 R7 A, R7 A, R7 A, R7 A, R7 A, R7 [2B]Key:[2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle2-72 Instruction Set
  • 3. Instruction SetInstruction Set Summary (Continued) 8 9 A B C D E F MOV SJMP ORL ANL PUSH POP MOVX A, MOVX DPTR,# 0 REL C, /bit C, /bit dir dir @DPTR @DPTR, A data 16 [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2C] [2C] [3B, 2C] AJMP ACALL AJMP ACALL AJMP ACALL AJMP ACALL 1 (P4) (P4) (P5) (P5) (P6) (P6) (P7) (P7) [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] [2B, 2C] ANL MOV MOV CPL CLR SETB MOVX MOVX 2 C, bit bit, C C, bit bit bit bit A, @R0 wR0, A [2B, 2C] [2B, 2C] [2B] [2B] [2B] [2B] [2C] [2C] MOVC A, MOVC A, INC MOVX MOVX CPL CLR SETB 3 @A + PC @A + DPTR DPTR A, @RI @RI, A C C C [2C] [2C] [2C] [2C] [2C] DIV SUBB MUL CJNE A, SWAP DA CLR CPL 4 AB A, #data AB #data, rel A A A A [2B, 4C] [2B] [4C] [3B, 2C] MOV SUBB CJNE XCH DJNZ MOV MOV 5 dir, dir A, dir A, dir, rel A, dir dir, rel A, dir dir, A [3B, 2C] [2B] [3B, 2C] [2B] [3B, 2C] [2B] [2B] CJNE MOV MOV SUBB @R0, #data, XCH XCHD MOV MOV 6 dir, @R0 @R0, dir A, @R0 rel A, @R0 A, @R0 A, @R0 @R0, A [2B, 2C] [2B, 2C] [3B, 2C] CJNE MOV MOV SUBB @R1, #data, XCH XCHD MOV MOV 7 dir, @R1 @R1, dir A, @R1 rel A, @R1 A, @R1 A, @R1 @R1, A [2B, 2C] [2B, 2C] [3B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV 8 dir, R0 R0, dir R0, #data, rel R0, rel A, R0 A, R0 A, R0 R0, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV 9 dir, R1 R1, dir R1, #data, rel R1, rel A, R1 A, R1 A, R1 R1, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV A dir, R2 R2, dir R2, #data, rel R2, rel A, R2 A, R2 A, R2 R2, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV B dir, R3 R3, dir R3, #data, rel R3, rel A, R3 A, R3 A, R3 R3, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV C dir, R4 R4, dir R4, #data, rel R4, rel A, R4 A, R4 A, R4 R4, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV D dir, R5 R5, dir R5, #data, rel R5, rel A, R5 A, R5 A, R5 R5, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV E dir, R6 R6, dir R6, #data, rel R6, rel A, R6 A, R6 A, R6 R6. A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C] MOV MOV CJNE DJNZ SUBB XCH MOV MOV F dir, R7 R7, dir R7, #data, rel R7, rel A, R7 A, R7 A, R7 R7, A [2B, 2C] [2B, 2C] [3B, 2C] [2B, 2C]Key:[2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle 2-73
  • 4. Table 1. AT89 Instruction Set Summary(1) Oscillator Oscillator Mnemonic Description Byte Mnemonic Description Byte Period Period ARITHMETIC OPERATIONS ARITHMETIC OPERATIONS (continued) ADD A,Rn Add register to 1 12 INC DPTR Increment Data 1 24 Accumulator Pointer ADD A,direct Add direct byte to 2 12 MUL AB Multiply A & B 1 48 Accumulator DIV AB Divide A by B 1 48 ADD A,@Ri Add indirect RAM 1 12 to Accumulator DA A Decimal Adjust 1 12 Accumulator ADD A,#data Add immediate 2 12 data to LOGICAL OPERATIONS Accumulator ANL A,Rn AND Register to 1 12 ADDC A,Rn Add register to 1 12 Accumulator Accumulator with ANL A,direct AND direct byte to 2 12 Carry Accumulator ADDC A,direct Add direct byte to 2 12 ANL A,@Ri AND indirect RAM 1 12 Accumulator with to Accumulator Carry ANL A,#data AND immediate 2 12 ADDC A,@Ri Add indirect RAM 1 12 data to to Accumulator Accumulator with Carry ANL direct,A AND Accumulator 2 12 ADDC A,#data Add immediate 2 12 to direct byte data to Acc with Carry ANL direct,#data AND immediate 3 24 data to direct byte SUBB A,Rn Subtract Register 1 12 from Acc with ORL A,Rn OR register to 1 12 borrow Accumulator SUBB A,direct Subtract direct 2 12 ORL A,direct OR direct byte to 2 12 byte from Acc with Accumulator borrow ORL A,@Ri OR indirect RAM 1 12 SUBB A,@Ri Subtract indirect 1 12 to Accumulator RAM from ACC with borrow ORL A,#data OR immediate 2 12 data to SUBB A,#data Subtract 2 12 Accumulator immediate data from Acc with ORL direct,A OR Accumulator to 2 12 borrow direct byte INC A Increment 1 12 ORL direct,#data OR immediate 3 24 Accumulator data to direct byte INC Rn Increment register 1 12 XRL A,Rn Exclusive-OR 1 12 register to INC direct Increment direct 2 12 Accumulator byte XRL A,direct Exclusive-OR 2 12 INC @Ri Increment direct 1 12 direct byte to RAM Accumulator DEC A Decrement 1 12 XRL A,@Ri Exclusive-OR 1 12 Accumulator indirect RAM to Accumulator DEC Rn Decrement 1 12 Register XRL A,#data Exclusive-OR 2 12 immediate data to DEC direct Decrement direct 2 12 Accumulator byte DEC @Ri Decrement 1 12 indirect RAMNote: 1. All mnemonics copyrighted © Intel Corp., 1980.2-74 Instruction Set
  • 5. Instruction SetTable 1. AT89 Instruction Set Summary (continued) Oscillator Oscillator Mnemonic Description Byte Period Mnemonic Description Byte Period LOGICAL OPERATIONS (continued) DATA TRANSFER (continued) XRL direct,A Exclusive-OR 2 12 MOV direct,@Ri Move indirect 2 24 Accumulator to RAM to direct byte direct byte MOV direct,#data Move immediate 3 24 XRL direct,#data Exclusive-OR 3 24 data to direct byte immediate data to direct byte MOV @Ri,A Move Accumulator 1 12 to indirect RAM CLR A Clear Accumulator 1 12 MOV @Ri,direct Move direct byte 2 24 CPL A Complement 1 12 to indirect RAM Accumulator MOV @Ri,#data Move immediate 2 12 RL A Rotate 1 12 data to indirect Accumulator Left RAM RLC A Rotate 1 12 MOV DPTR,#data16 Load Data Pointer 3 24 Accumulator Left with a 16-bit through the Carry constant RR A Rotate 1 12 MOVC A,@A+DPTR Move Code byte 1 24 Accumulator Right relative to DPTR to Acc RRC A Rotate 1 12 Accumulator Right MOVC A,@A+PC Move Code byte 1 24 through the Carry relative to PC to Acc SWAP A Swap nibbles 1 12 within the MOVX A,@Ri Move External 1 24 Accumulator RAM (8-bit addr) to Acc DATA TRANSFER MOVX A,@DPTR Move Exernal 1 24 MOV A,Rn Move register to 1 12 RAM (16-bit addr) Accumulator to Acc MOV A,direct Move direct byte 2 12 MOVX @Ri,A Move Acc to 1 24 to Accumulator External RAM (8- bit addr) MOV A,@Ri Move indirect 1 12 RAM to MOVX @DPTR,A Move Acc to 1 24 Accumulator External RAM (16- bit addr) MOV A,#data Move immediate 2 12 data to PUSH direct Push direct byte 2 24 Accumulator onto stack MOV Rn,A Move Accumulator 1 12 POP direct Pop direct byte 2 24 to register from stack MOV Rn,direct Move direct byte 2 24 XCH A,Rn Exchange register 1 12 to register with Accumulator MOV Rn,#data Move immediate 2 12 XCH A,direct Exchange direct 2 12 data to register byte with Accumulator MOV direct,A Move Accumulator 2 12 to direct byte XCH A,@Ri Exchange indirect 1 12 RAM with MOV direct,Rn Move register to 2 24 Accumulator direct byte XCHD A,@Ri Exchange low- 1 12 MOV direct,direct Move direct byte 3 24 order Digit indirect to direct RAM with Acc 2-75
  • 6. Table 1. AT89 Instruction Set Summary (continued) Oscillator Oscillator Mnemonic Description Byte Period Mnemonic Description Byte PeriodBOOLEAN VARIABLE MANIPULATION PROGRAM BRANCHING (continued)CLR C Clear Carry 1 12 JMP @A+DPTR Jump indirect 1 24 relative to theCLR bit Clear direct bit 2 12 DPTRSETB C Set Carry 1 12 JZ rel Jump if 2 24 Accumulator isSETB bit Set direct bit 2 12 ZeroCPL C Complement Carry 1 12 JNZ rel Jump if 2 24CPL bit Complement direct 2 12 Accumulator is Not bit ZeroANL C,bit AND direct bit to 2 24 CJNE A,direct,rel Compare direct 3 24 CARRY byte to Acc and Jump if Not EqualANL C,/bit AND complement 2 24 of direct bit to CJNE A,#data,rel Compare 3 24 Carry immediate to Acc and Jump if NotORL C,bit OR direct bit to 2 24 Equal Carry CJNE Rn,#data,rel Compare 3 24ORL C,/bit OR complement of 2 24 immediate to direct bit to Carry register and Jump if Not EqualMOV C,bit Move direct bit to 2 12 Carry CJNE @Ri,#data,rel Compare 3 24 immediate toMOV bit,C Move Carry to 2 24 indirect and Jump direct bit if Not EqualJC rel Jump if Carry is set 2 24 DJNZ Rn,rel Decrement 2 24 register and JumpJNC rel Jump if Carry not 2 24 if Not Zero set DJNZ direct,rel Decrement direct 3 24JB bit,rel Jump if direct Bit is 3 24 byte and Jump if set Not ZeroJNB bit,rel Jump if direct Bit is 3 24 NOP No Operation 1 12 Not setJBC bit,rel Jump if direct Bit is 3 24 set & clear bitPROGRAM BRANCHINGACALL addr11 Absolute 2 24 Subroutine CallLCALL addr16 Long Subroutine 3 24 CallRET Return from 1 24 SubroutineRETI Return from 1 24 interruptAJMP addr11 Absolute Jump 2 24LJMP addr16 Long Jump 3 24SJMP rel Short Jump 2 24 (relative addr)2-76 Instruction Set
  • 7. Instruction SetTable 2. Instruction Opcodes in Hexadecimal Order Hex Number Hex Number Code of Bytes Mnemonic Operands Code of Bytes Mnemonic Operands 00 1 NOP 22 1 RET 01 2 AJMP code addr 23 1 RL A 02 3 LJMP code addr 24 2 ADD A,#data 03 1 RR A 25 2 ADD A,data addr 04 1 INC A 26 1 ADD A,@R0 05 2 INC data addr 27 1 ADD A,@R1 06 1 INC @R0 28 1 ADD A,R0 07 1 INC @R1 29 1 ADD A,R1 08 1 INC R0 2A 1 ADD A,R2 09 1 INC R1 2B 1 ADD A,R3 0A 1 INC R2 2C 1 ADD A,R4 0B 1 INC R3 2D 1 ADD A,R5 0C 1 INC R4 2E 1 ADD A,R6 0D 1 INC R5 2F 1 ADD A,R7 0E 1 INC R6 30 3 JNB bit addr,code addr 0F 1 INC R7 31 2 ACALL code addr 10 3 JBC bit addr, code addr 32 1 RETI 11 2 ACALL code addr 33 1 RLC A 12 3 LCALL code addr 34 2 ADDC A,#data 13 1 RRC A 35 2 ADDC A,data addr 14 1 DEC A 36 1 ADDC A,@R0 15 2 DEC data addr 37 1 ADDC A,@R1 16 1 DEC @R0 38 1 ADDC A,R0 17 1 DEC @R1 39 1 ADDC A,R1 18 1 DEC R0 3A 1 ADDC A,R2 19 1 DEC R1 3B 1 ADDC A,R3 1A 1 DEC R2 3C 1 ADDC A,R4 1B 1 DEC R3 3D 1 ADDC A,R5 1C 1 DEC R4 3E 1 ADDC A,R6 1D 1 DEC R5 3F 1 ADDC A,R7 1E 1 DEC R6 40 2 JC code addr 1F 1 DEC R7 20 3 JB bit addr,code addr 21 2 AJMP code addr 2-77
  • 8. Table 2. Instruction Opcodes in Hexadecimal Order (continued) Hex Number Hex Number Code of Bytes Mnemonic Operands Code of Bytes Mnemonic Operands 41 2 AJMP code addr 60 2 JZ code addr 42 2 ORL data addr,A 61 2 AJMP code addr 43 3 ORL data addr,#data 62 2 XRL data addr,A 44 2 ORL A,#data 63 3 XRL data addr,#data 45 2 ORL A,data addr 64 2 XRL A,#data 46 1 ORL A,@R0 65 2 XRL A,data addr 47 1 ORL A,@R1 66 1 XRL A,@R0 48 1 ORL A,R0 67 1 XRL A,@R1 49 1 ORL A,R1 68 1 XRL A,R0 4A 1 ORL A,R2 69 1 XRL A,R1 4B 1 ORL A,R3 6A 1 XRL A,R2 4C 1 ORL A,R4 6B 1 XRL A,R3 4D 1 ORL A,R5 6C 1 XRL A,R4 4E 1 ORL A,R6 6D 1 XRL A,R5 4F 1 ORL A,R7 6E 1 XRL A,R6 50 2 JNC code addr 6F 1 XRL A,R7 51 2 ACALL code addr 70 2 JNZ code addr 52 2 ANL data addr,A 71 2 ACALL code addr 53 3 ANL data addr,#data 72 2 ORL C,bit addr 54 2 ANL A,#data 73 1 JMP @A+DPTR 55 2 ANL A, data addr 74 2 MOV A,#data 56 1 ANL A,@R0 75 3 MOV data addr,#data 57 1 ANL A,@R1 76 2 MOV @R0,#data 58 1 ANL A,R0 77 2 MOV @R1,#data 59 1 ANL A,R1 78 2 MOV R0,#data 5A 1 ANL A,R2 79 2 MOV R1,#data 5B 1 ANL A,R3 7A 2 MOV R2,#data 5C 1 ANL A,R4 7B 2 MOV R3,#data 5D 1 ANL A,R5 7C 2 MOV R4,#data 5E 1 ANL A,R6 7D 2 MOV R5,#data 5F 1 ANL A,R7 7E 2 MOV R6,#data2-78 Instruction Set
  • 9. Instruction SetTable 2. Instruction Opcodes in Hexadecimal Order (continued) Hex Number Hex Number Code of Bytes Mnemonic Operands Code of Bytes Mnemonic Operands7F 2 MOV R7,#data A0 2 ORL C,/bit addr80 2 SJMP code addr A1 2 AJMP code addr81 2 AJMP code addr A2 2 MOV C,bit addr82 2 ANL C,bit addr A3 1 INC DPTR83 1 MOVC A,@A+PC A4 1 MUL AB84 1 DIV AB A5 reserved85 3 MOV data addr,data addr A6 2 MOV @R0,data addr86 2 MOV data addr,@R0 A7 2 MOV @R1,data addr87 2 MOV data addr,@R1 A8 2 MOV R0,data addr88 2 MOV data addr,R0 A9 2 MOV R1,data addr89 2 MOV data addr,R1 AA 2 MOV R2,data addr8A 2 MOV data addr,R2 AB 2 MOV R3,data addr8B 2 MOV data addr,R3 AC 2 MOV R4,data addr8C 2 MOV data addr,R4 AD 2 MOV R5,data addr8D 2 MOV data addr,R5 AE 2 MOV R6,data addr8E 2 MOV data addr,R6 AF 2 MOV R7,data addr8F 2 MOV data addr,R7 B0 2 ANL C,/bit addr90 3 MOV DPTR,#data B1 2 ACALL code addr91 2 ACALL code addr B2 2 CPL bit addr92 2 MOV bit addr,C B3 1 CPL C93 1 MOVC A,@A+DPTR B4 3 CJNE A,#data,code addr94 2 SUBB A,#data B5 3 CJNE A,data addr,code addr95 2 SUBB A,data addr B6 3 CJNE @R0,#data,code96 1 SUBB A,@R0 addr97 1 SUBB A,@R1 B7 3 CJNE @R1,#data,code addr98 1 SUBB A,R0 B8 3 CJNE R0,#data,code addr99 1 SUBB A,R1 B9 3 CJNE R1,#data,code addr9A 1 SUBB A,R2 BA 3 CJNE R2,#data,code addr9B 1 SUBB A,R3 BB 3 CJNE R3,#data,code addr9C 1 SUBB A,R4 BC 3 CJNE R4,#data,code addr9D 1 SUBB A,R5 BD 3 CJNE R5,#data,code addr9E 1 SUBB A,R6 BE 3 CJNE R6,#data,code addr9F 1 SUBB A,R7 BF 3 CJNE R7,#data,code addr 2-79
  • 10. Table 2. Instruction Opcodes in Hexadecimal Order (continued) Hex Number Hex Number Code of Bytes Mnemonic Operands Code of Bytes Mnemonic Operands C0 2 PUSH data addr E0 1 MOVX A,@DPTR C1 2 AJMP code addr E1 2 AJMP code addr C2 2 CLR bit addr E2 1 MOVX A,@R0 C3 1 CLR C E3 1 MOVX A,@R1 C4 1 SWAP A E4 1 CLR A C5 2 XCH A,data addr E5 2 MOV A,data addr C6 1 XCH A,@R0 E6 1 MOV A,@R0 C7 1 XCH A,@R1 E7 1 MOV A,@R1 C8 1 XCH A,R0 E8 1 MOV A,R0 C9 1 XCH A,R1 E9 1 MOV A,R1 CA 1 XCH A,R2 EA 1 MOV A,R2 CB 1 XCH A,R3 EB 1 MOV A,R3 CC 1 XCH A,R4 EC 1 MOV A,R4 CD 1 XCH A,R5 ED 1 MOV A,R5 CE 1 XCH A,R6 EE 1 MOV A,R6 CF 1 XCH A,R7 EF 1 MOV A,R7 D0 2 POP data addr F0 1 MOVX @DPTR,A D1 2 ACALL code addr F1 2 ACALL code addr D2 2 SETB bit addr F2 1 MOVX @R0,A D3 1 SETB C F3 1 MOVX @R1,A D4 1 DA A F4 1 CPL A D5 3 DJNZ data addr,code F5 2 MOV data addr,A addr F6 1 MOV @R0,A D6 1 XCHD A,@R0 F7 1 MOV @R1,A D7 1 XCHD A,@R1 F8 1 MOV R0,A D8 2 DJNZ R0,code addr F9 1 MOV R1,A D9 2 DJNZ R1,code addr FA 1 MOV R2,A DA 2 DJNZ R2,code addr FB 1 MOV R3,A DB 2 DJNZ R3,code addr FC 1 MOV R4,A DC 2 DJNZ R4,code addr FD 1 MOV R5,A DD 2 DJNZ R5,code addr FE 1 MOV R6,A DE 2 DJNZ R6,code addr FF 1 MOV R7,A DF 2 DJNZ R7,code addr2-80 Instruction Set