3 D Packaging 2007 For Emc3d

1,868 views

Published on

3D-packaging technology is a cost-competitive solution to manage the increasingly limited \'real estate\' available in consumer applications. One major challenge is through silicon via (TSV) formation using the Bosch process. The alternating and repeated use of etching and passivation chemistries poses various challenges to photoresist design, such as excellent resolution, vertical profiles, high etch resistance, and simple removal. We discuss lithographic properties and performance of a new negative resist concept designed for full compatibility with the Bosch process with excellent coating uniformity over a film thickness range from < 10 to &gt; 120 um and aspect ratios exceeding 5:1. The material combines short process times with excellent etch resistance and residue-free removal with standard strippers, thus facilitating the most challenging process of advanced 3D-packaging concepts.

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
1,868
On SlideShare
0
From Embeds
0
Number of Embeds
10
Actions
Shares
0
Downloads
45
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

3 D Packaging 2007 For Emc3d

  1. 1. Photoresists for 3D Packaging Challenges And Solutions Robert Plass[1], Chunwei Chen[1], Rozalia Beica[2] Stephen Meyer[1],Georg Pawlowski[1] [1] AZ Electronic Materials Corp. USA, Branchburg NJ [2] Semitool, Kalispell, MT www.emc3d.org Device Packaging March 2007 Page1
  2. 2. Outline  Introduction  Technology Background  Bosch Process  Photoresist Technology  Comparison of Positive vs Negative Resists  AZ® EXP 125nXT  Performance Comparison  Lithography  Plating  Conclusions IMAPS Device Packaging March 2007 2 Page 2
  3. 3. Introduction Dramatic evolution of portable consumer electronics, such as  cellular phones  audio players  cameras  video recorder require non-traditional packaging technologies to enable  further miniaturization  expanding functionality  new feature sets  faster communication  increasing integration of features as required by a rapidly growing consumer base. Consumer applications account for more than 50% of all electronic devices. IMAPS Device Packaging March 2007 3 Page 3
  4. 4. Technology Background 3D packaging and integration schemes will typically rely on the following base-line technologies:  Through Silicon Vias (TSV) using variations of the Bosch process  Redistribution and metallization using copper plating  Solder bumping using lead-free solders Target → Provide one photoresist material compatible with all technology requirements IMAPS Device Packaging March 2007 4 Page 4
  5. 5. 3D Packaging Process front (device side) Substrate CMP (optional) Plating (Cu and Solder)/ Stripping/Etching Lithography Chip to Wafer Wafer to Wafer Carrier Bonding Dicing Via Etch Stripping/Cleaning Stacking Sequential Thinning Insulator/Barrier/Seed Deposition Pick and Place/Stacking Insulator/Barrier/Seed Deposition Dicing Lithography Lithography Debonding Dicing Plating/Stripping/Etching Debonding IMAPS Device Packaging March 2007 5 Page 5
  6. 6. TSV: Technology Background Highly anisotropic deep reactive ion etching (DRIE) is routinely used for MEMS mass products (‘silicon micromachining’). -> Etch process concepts can be applied for advanced packaging. Bosch Process – US 5,501,893 (F. Laermer, 1992). Alternating, short period process steps of somewhat isotropic silicon removal and protective polymer deposition using high-density, inductively coupled plasma (ICP) etching systems. Etch step ‘bites’ into silicon (0.5 – 5 µm), while polymer deposition minimizes lateral etch creating vertical, high aspect ratio trenches and holes. IMAPS Device Packaging March 2007 6 Page 6
  7. 7. The Bosch Process Source: L. Lea and D. Hynes MEMS Manufacturing M9, 2005 IMAPS Device Packaging March 2007 7 Page 7
  8. 8. Through Silicon Vias / 3D Packaging: Photoresist Requirements  Fast resist processing (coat, development, strip)  High photospeed, no holding time  Vertical profiles  Excellent resolution / aspect ratio to minimize ‘real estate’  Wide process latitude and reliability  TMAH development  Universal plating compatibility (Cu, Ni, Au, SnAg, Pb-Free, Soak Tests)  High etch selectivity (> 70:1)  Inertness versus etch gas compositions (Bosch Process)  No ‘cracking’ or ‘pull-back’ (underetch) during extended etch processes  Residue-free, simple strip after etch or via fill IMAPS Device Packaging March 2007 8 Page 8
  9. 9. Lithographic Methods Negative Resist Positive Resist A physical increase in the molecular weight of the A chemical change that renders polymer that renders the exposed area insoluble the exposed area of the polymer soluble IMAPS Device Packaging March 2007 9 Page 9
  10. 10. Photoresist Properties Comparison Process Negative [PP] Positive [DNQ] Remarks Max FT [µm] > 110 < 60 N >> P Substrate Compatibility Excellent Good N >= P Process 3 Steps >= 4 Steps N>P Coating Uniformity < 2% RSD >= 2 % RSD N>P Process Latitude Large Smaller N >> P Gap Margin [µm] Wide Narrow N>P Development Latitude Large Smaller N>P Developer Type Organic Organic / Inorganic N<P Plating Stability Excellent Good N>P Stripping Special Standard Standard N << P N= P IMAPS Device Packaging March 2007 10 Page 10
  11. 11. Co Time at Co an at d an Ex Ba ke d po Pr Ba se e -E e k x po De se v el o De p la y Pr e- P l at eP re p Typical Positive Tone Process Ready to Plate Typical Negative Tone Process Page 11 Ex March 2007 po se IMAPS Device Packaging Po st Ex po De se ve Ba lo ke p Po st De ve lo Pr p e- Ba Pl ke at Lithographic Processing Time Line e Pr ep Ready to Plate 11
  12. 12. Total Processing Time – 50 µm FT Process 50 µm Films Positive [DNQ] Negative [PP] Coat 3 min 3 min Bake 10 min 10 min Hydration Delay 60 min None Exposure 4000 mJ/cm2 2000 mJ/cm2 Post Exposure Bake* 30 sec None Development 10 min 2 min Post Develop Bake* 2-5 min Not required Total Time (not counting tool About 85 min About 15 min transfer time) * Optional IMAPS Device Packaging March 2007 12 Page 12
  13. 13. Photoresists for Through Silicon Vias Positive Tone Negative Tone AZ® EXP 40XT-11 AZ® EXP 125nXT-10 Exposure Latitude Resolution 400 – 800 mJ/cm2 50 – 15 µm FT = 40 µm FT = 70 µm CD = 40 µm CD = 50 – 15 µm SB = 95oC/240s SB = 120oC/600s 115oC/240s Suss MA 200 UltraTech AP 300 Dose Range: Dose: 2000 mJ/cm2 400 – 800 mJ/cm2 PEB = 100oC/60s Development: Development: MIF300 3x60s puddle MIF300 2x60s puddle IMAPS Device Packaging March 2007 13 Page 13
  14. 14. 8” Coating Uniformity Maps for AZ® EXP 125nXT Mean FT: 75.3 µm Uniformity: 1.07%RSD IMAPS Device Packaging March 2007 14 Page 14
  15. 15. Film Thickness Coverage with AZ® EXP 125nXT Single Coat Capability from 10 µm to 120 µm FT Dependant Dose Range: 500 – 3000 mJ/cm2 10 µm FT 20 µm FT 40 µm FT 70 µm FT 90 µm FT 120 µm FT IMAPS Device Packaging March 2007 15 Page 15
  16. 16. AZ® EXP 125nXT-10 on Si & Cu @ FT = 70 µm 100 µm 70 µm 60 µm 50 µm 40 µm Si Cu 35 µm 30 µm 25 µm 20 µm 15 µm Si Aspect Ratio > 5:1 Cu IMAPS Device Packaging March 2007 16 Page 16
  17. 17. Plating Bath Compatibility Tests H2SO4 test (Cu Plating) Concentration: 189 g (98% H2SO4) in 1000 mL DI water Temperature: 25°C Soaking time: 100 min; 150 min; 180 min H3BO3 test (Ni Plating) Concentration: 45 g in 1000 mL DI water Temperature: 55°C Soaking time: 10 min; 15 min; 20 min IMAPS Device Packaging March ٢٠٠٧ ١٧ Page ١٧
  18. 18. Cu Plating Process Compatibility - Soaking Test in H2SO4 90 µm C/H, 1:1 Positive Tone Resist (40 µm) Negative Tone Resist (90 µm) Before soaking 180 min H2SO4 at 25°C IMAPS Device Packaging March ٢٠٠٧ ١٨ Page ١٨
  19. 19. Ni Plating Process Compatibility - Soaking Test in H3BO3 90 µm C/H, 1:1 Positive Tone Resist (40 µm) Negative Tone Resist (90 µm) Before soaking 10 min H3BO3 at 55°C 15 min H3BO3 at 55°C 20 min H3BO3 at 55°C IMAPS Device Packaging March ٢٠٠٧ ١٩ Page ١٩
  20. 20. AZ® EXP 125nXT after Bosch DRIE Photoresist Silicon IMAPS Device Packaging March ٢٠٠٧ ٢٠ Page ٢٠
  21. 21. AZ® Exp 125nXT-10 Litho and Cu Plating Process Conditions Exposure tool: Suss Aligner MA-200 Dose: 1200 to 3400 mJ/cm2 Developer: AZ 300 MIF, 30 sec to 138 sec, multiple puddle Resist Thickness: 25µm, 50µm, 75µm, 100µm Descum: 02 Plasma, Plasma Start AXIC Equipment Cu solution: Intervia 8540 Tool: Semitool CFD 2 Reactor 30°C, flow rate = 5 gpm; wafer rotation = 60 rpm Deposition rate = 0.4 - 0.8 µm/min Stripper: AZ® 400T at 75°C for 20 min IMAPS Device Packaging March 2007 21 Page 21
  22. 22. Plating Performance (C/H) at 25µm FT, 1200 mJ/cm2 60 µm 50 µm 40 µm 30 µm Resist C/H Cu Plate 20 µm 10 µm 9 µm 8 µm Resist C/H Cu Plate IMAPS Device Packaging March 2007 22 Page 22
  23. 23. Resist and Cu Plate Images 75 µm Vias 8 µm Vias 100 µm 75 µm 50 µm 25 µm FT FT FT FT Resist Pattern Cu Plate Dose: 3400 mJ/cm2 Dose: 2200 mJ/cm2 Dose: 1200 mJ/cm2 Dose: 1200 mJ/cm2 Develop: 3 x 46 Sec Puddles Develop: 3 x 35 Sec Puddles Develop: 3 x 25 Sec Puddles Develop: 2 x 15 Sec Puddles IMAPS Device Packaging March 2007 23 Page 23
  24. 24. Cu Plating & Soldering with AZ® EXP 125nXT-10 FT 65µm on Cu (single coat) Before Plating 90 µm C/H 40 µm C/H 70 µm L/S 90 µm 40 µm 90 µm 40 µm After Cu plating After solder plating IMAPS Device Packaging March 2007 24 Page 24
  25. 25. How Does the Current Generation of Negative Tone TFR’s Match up  Fast resist processing (coat, development, strip)  High photospeed, no holding time  Vertical profiles  Excellent resolution / aspect ratio to minimize ‘real estate’  Wide process latitude and reliability  TMAH development  Universal Plating compatibility (Cu, Ni, Au, SnAg, Pb-Free, Soak Tests)  High etch selectivity (> 70:1)  Inertness versus etch gas compositions (Bosch Process)  No ‘cracking’ ‘pull-back’ (underetch) during extended etch processes  Residue-free, simple strip after etch or via fill IMAPS Device Packaging March 2007 25 Page 25
  26. 26. Conclusions ▶ Thick Film Resist Technology covers a wide range of packaging needs – Through Silicon Vias (TVS) via the Bosch Process – Redistribution and metallization using copper plating – Solder bumping using lead-free solders – Au bumping (both non-cyanic and cyanic) ▶ Negative resists show advantages in processing latitude and stability ▶ Exceptional coating properties – 10 – 120 µm via single coat – Excellent uniformity ( <2% RSD) ▶ Exceptional aspect ratios (up to or beyond 5:1) ▶ Exceptional exposure latitude ▶ Exceptional chemical stability ▶ Good strippability IMAPS Device Packaging March 2007 26 Page 26
  27. 27. Acknowledgements ▶ The authors would like to thank Robert Smith for SEM support and LEM Group at AZ Branchburg for excellent maintenance. IMAPS Device Packaging March 2007 27 Page 27
  28. 28. 1
  29. 29. 2
  30. 30. As we have heard this week everyone is talking about the dramatic growth in consumer electronics. This means that as demands for increased integration of functionality on one device accelerate we need to find ways through packaging to get more functionality in less space. 3
  31. 31. This will have to be done through increased efficiency of packaging. This is a limiting function for how small a device can be. We can make smaller circuits, but they cost more (and in consumer electronics price is the driving factor to get volume) But we still have to connect them and connectors will not get a lot smaller. Solution: Better packaging. 4
  32. 32. If we look at the packaging process we see 3 litho steps. TSV Redistribution Bumping All with different requirements. It would be great if we could find one resist technology that has the potential to do all three levels 5
  33. 33. 6
  34. 34. One of the more challenging steps will be TSV Problem with adhesion and resistance to Etch 7
  35. 35. 8
  36. 36. 9
  37. 37. New generations of Negative Resist do not require special (reactive) strippers 10
  38. 38. Less delay and shorter total time= Lower Cost of Ownership 11
  39. 39. 12
  40. 40. 13
  41. 41. How do I get such good coatings with manual hand dispense?? 14
  42. 42. First generation showed high potential for 100+ um coatings if we could increase the solids loading Work was done to accomplish this. After fixing the coating issue we made some formulation modifications to allow for faster photospeed and better development of the deep trenches and vias. 15
  43. 43. Normally with DNQ and Chemically amplified resist you run into profile, adhesion and photospeed issues when going form Si substrates (typically used in early evaluations due to cost) to Cu wafers No significant changes with new generation negatives 16
  44. 44. 17
  45. 45. Positive shows slight erosion of profile at surface 18
  46. 46. Positive shows attack of surface Attack of side walls WHY?? It is not Crosslinked like a Negative resist 19
  47. 47. No under cutting Slight scalloping No “Charcoaling” of surface High selectivity 20
  48. 48. These pictures were generated while testing out our new tool set and we have not fully optimized the process. Ridges on the contacts are due to optical issue with the mask not being optimized for this tool. Other masks do not show this if set up correctly. 21
  49. 49. 22
  50. 50. 23
  51. 51. Shows SEMS from a different mask and exposure tool 24
  52. 52. 25
  53. 53. 26
  54. 54. 27

×