Overview of RTaW SysML-Companion
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Overview of RTaW SysML-Companion

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RTaW SysML Companion transforms SysML models into VHDL/AMS so that it becomes possible to simulate SysML models. SysML Companion enables to perform virtual prototyping and derive tests very early in ...

RTaW SysML Companion transforms SysML models into VHDL/AMS so that it becomes possible to simulate SysML models. SysML Companion enables to perform virtual prototyping and derive tests very early in the design phase directly from SysML specification. To the best of our knowledge, SysML Companion is the first tool of its kind.

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Overview of RTaW SysML-Companion Presentation Transcript

  • 1. SysML-Companion: Virtual prototyping from SysML models RealTime-at-Work http://www.realtimeatwork.com Better technical solutions for complex systems
  • 2. How to... ● have a common repository for both manager and engineers? ● do early testing of project feasibility and check hypotheses soundness? ● verify functional and non-functional properties on the model? ● easily explore design space? ● test the conformance of final product? ● ease the maintainability of the system?
  • 3. Virtual prototyping from SysML ● Write a unique specification in SysML, the lingua franca of system engineers ● Do virtual-prototyping from it ● Derive tests from the specification ● Test and optimize with hardware-in-the-loop RTaW SysML-Companion automatically generates from SysML specification simulable and formally analysable models.
  • 4. Simulate your SysML model! The SysML model A simulation trace
  • 5. Top reasons to virtual- prototype your model ● Keep documentation and model up-to-date ● Enable early testing of hypotheses and feasibility ● Enable to verify hardware and software at the same time (hardware in the loop) ➔ Cut prototype cost ➔ Shorten time-to-market
  • 6. Why SysML? ● “Lingua franca” between managers and engineers from different background ● Capture all important facets of your product ● Tools independent ● Standardized by OMG ● Technology independent ● Powerful extensible modelling language
  • 7. How it works The SysML model Simulation trace RTaW Sysml-Companion Vhdl-Ams Vhdl-Ams simulator
  • 8. Why Vhdl-Ams? ● Vendor independent: IEEE Standard (1076.1) ● Multi-domain: continuous and discrete ● Many tools available ● Plan for Modelica and more
  • 9. SysML-Companion at work The following slides illustrate the process on a simple circuit that mixes electronic and logic.
  • 10. Description of a test circuit
  • 11. Definition of the digital-analogic converter Description of the “real” thing The behaviour of the DAConvertor
  • 12. Parametric diagram describes the input/output relation The two electrical pin respect the Kirschhoff law. This is how the behaviour constraint the voltage to the input.
  • 13. Vhdl-Ams conversion ---------- ENTITY DECLARATION DAConvertor ---------- ENTITY DAConvertor IS PORT(TERMINAL p : Electrical; TERMINAL m : Electrical; SIGNAL input : IN BIT); END ENTITY DAConvertor; ---------- ARCHITECTURE DECLARATION behav ---------- ARCHITECTURE behav OF DAConvertor IS QUANTITY v_out ACROSS i_out THROUGH p TO m; BEGIN IF (input='0') USE v_out == -2.0; ELSE v_out == 2.0; END USE; BREAK ON input; END ARCHITECTURE behav;
  • 14. Simulation trace of the circuit Input of the DAC Output of the DAC converter Voltage at the resistor Voltage at the self- inductance
  • 15. RealTime-at-Work http://www.realtimeatwork.com Better technical solutions for complex systems