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Synchronisation Synchronisation Document Transcript

  • Synchronisation Training Presenter: Colin Argent CECP On behalf of: Horsebridge Network Systems Ltd.
  • ContentsDay 1 Introductions Chapter 01 - Time, Frequency and Phase Chapter 02 - Synchronisation Chapter 03 - Sync Distribution layer Chapter 04 - Sync Distribution Layer – Clocks Chapter 05 - Sync Distribution Layer – EquipmentDay 2 Chapter 06 - Sync Distribution Layer – Links Chapter 07 - SDH Network Topology Chapter 08 - Synchronisation Network Architecture Chapter 09 - Synchronisation Standards Chapter 10 - Sync E (Synchronous Ethernet)Day 3 Chapter 11 - IEEE 1588v2 - PTP (Precision Timing Protocol) Chapter 12 - Boundary and Transparent Clocks Chapter 13 - Clock Measurements Chapter 14 - CALNEX Testing On-screen demo
  • Chapter 01Time, Frequency and Phase 1
  • Time and Frequency 2
  • Time, Time Scales & Dates• There are Two meanings of the word time: - The date of an event on a time scale - As a time interval between two events• Time scales : - A time scale is defined by : A time unit A time origin• Dates : A date is a number of units on the time scale 3
  • The Second• The second is the time unit of the International System of Units (SI)• It just so happens that the second is relative to that of Caesium atom transition• This means that modern time accuracy is based around time derived from a Caesium device• This is commonly known as an Atomic Clock 4
  • Clocks• A clock consists of: - A period which can be observed e.g. Secs, Mins & Hrs - A counter which counts the number of periods - A means for setting the counter to a preset value - A display of the registered count u(t) n(t) T(t) Oscillator Counter Display N0 start 5
  • Atomic Time Scales• Origin of Atomic Time Scales : 1 January 1958, at 0hr 0min 0sec - UT2• International Atomic Time (TAI) : Based on atomic time scales and implemented by a network of atomic clocks located all over the earth and operated by the Bureau International de l’Heure (BIH) in Paris• Coordinated Universal Time (UTC) : Timescale based on the time unit of TAI, transmitted on air from the GPS system• In 1967 a new SI definition of a second was created based on the radiation from the caesium-133 atom• It is correctly defined as "the duration of 9,192,631,770 periods of the radiation corresponding to the transition between two hyperfine levels of the ground state of the caesium-133 atom" 6
  • BIPM• The International Bureau of Weights and Measures (Bureau International des Poids et Mesures)• The realization and dissemination of the international time scales is the responsibility of the Time Section of the BIPM. International Atomic Time (TAI) is the uniform time scale; it is kept as close as possible to the second of the SI. Coordinated Universal Time (UTC) is an atomic time scale derived from TAI, to provide a reference scale in step with the irregular rotation of the earth• Local realizations of UTC exist at the national time laboratories. These laboratories participate in the calculation of the international time scales by sending their clock data to the BIPM. Most of them are equipped with commercial caesium beams that provide a practical realization of the second sufficiently accurate for most applications. More accurate caesium standards exist in a small number of laboratories; for them, the uncertainties are estimated to be a few parts in 1015. New developments in clocks using trapped or cooled atoms or ions are leading to improvements well beyond this• The atomic time scales TAI and UTC are disseminated monthly through the BIPM Circular T. The Annual Report of the BIPM Time Section provides all relevant information, data and results for the year previous to its publication. Reports on time-transfer techniques are also issued regularly• Other activities related to the time scales are developed in the section; these contribute to improving the calculation algorithms and increasing knowledge about time transfer techniques 7
  • FrequencyDefinition:• the number of occurrences within a given time periodUnit:• Frequency is expressed in [ Hertz = 1cycle/second ] 1 amplitude 0 1 0 1x10-7 2x10-7 3x10-7 4x10-7 5x10-7 6x10-7 time 8
  • Phase• Phase is the difference in time relationship between two same frequency waveforms• It is usually measured in degrees• It can be a comparison with an earlier instance of the same waveform - known as Differential Phase 90° 180° 360° 0° 270° 90 °Phase Shift 270°Differential Phase Shift 9
  • Round Up• What are the 2 main time standards?• What is periodic value of a Caesium atom?• What are the 3 main components of a clock?• What unit is frequency expressed as? 10
  • Chapter 02Synchronisation 1
  • Introduction to Synchronisation 2
  • What is Synchronisation ?Definition of Synchronisation• The timing of all nodes within digital networks to a common highly accurate and stable clocking source• To ensure they all use the same data rates to transmit and receive information 3
  • Why do we need Synchronisation ? • If synchronisation is not used node clocks operate asynchronously and the their transmit and receive data rates would be different. • This would cause slips or pointer adjustments to occur frequently, seriously degrading the quality of services transported by the network 4
  • Types of Synchronisation3 types of Synchronisation:1 - Frequency synchronisation2 - Phase synchronisation3 - Time synchronisation 5
  • Frequency Synchronisation System A System BClock signalof system A tClock signalof system B t 6
  • Frequency Synchronisation• Transmission data is ‘loaded’ and ‘recovered’ from transmission linesby data processing circuits• These use a clock edge to denote the transition of one bit to the next Transmission Link Data Data Data Clock 1 Clock 2 If Clock 1 & 2 are at different speeds then slips between equipments will occur at the input buffers 7
  • Frequency Sync – Too Fast Transmission Link Data Data Data Clock 1 Clock 2• If the frequency of Clock 1 is higher than that of Clock 2 - – Data will be clocked into the transmission link at a higher rate than it is clocked out – The result will be that data is lost at the receiving end 8
  • Frequency Sync - Too Slow Transmission Link Data Data Data Clock 1 Clock 2• If the frequency of Clock 1 is lower than that of Clock 2 - – Data will be clocked into the transmission link at a lower rate than it is clocked out – The result will be that data is lost at the receiving end 9
  • Phase Synchronisation System A System BClock signalof system A tClock signalof system B t 10
  • Time synchronisation System A System BTime signal of system A 14/01/00 14/01/00 14/01/00 08:34:55 08:34:56 08:34:57 tTime signal of system B 14/01/00 14/01/00 14/01/00 08:34:55 08:34:56 08:34:57 t 11
  • Nwks/Services that require Sync• Public Switched Telephone Networks• SONET and SDH transport networks• Cellular mobile telecom networks - GSM, UMTS etc• Location Services over Mobile Networks - E911, GSM 03.71, etc• Ground stations of satellite networks• Digital Audio Broadcasting (DAB)• Digital Video Broadcasting (DVB)• Time distribution for charging & event time stamping• Next Generation Networks – Wi-Max, MPLS 12
  • Slips• Slips are the main consequence of poor synchronisation within SDH / SONET networks• Slips can have a detrimental effect on quality of service 13
  • What Are Slips ?• A slip occurs when an equipment input buffer over or underflows due to differences in timing Slip Incoming data rate Outgoing data rate • This results in information being lost 14
  • Mobile Networks – 2G & 3GSuccessful handover requires synchronisationbetween base transceiver stations (BTS) BTS BTS BTS BTS 15
  • Cellular Mobile Telecom Networks Radio carrier frequencies must be synchronised precisely in order to prevent cross-talk Radio spectrum Frequency 16
  • Effects of Frequency ErrorsSlip – PDH Environment FIFO buffer overflows and dumps its contentsPointer Adjustment – SDH Environment 2Mbit/s transmission VC12 pointer adjustments cause phase hits of 3.47µs 34 & 140 Mbit/s transmissionPointer Movement at SDH-PDH boundaries PDH takes sync from 2 Mbit/s and needs excellent phase performancePointer adjustments will create phase hits 17
  • Services effected by slips Voice Uncompressed - only 5% of slips lead to clicks Compressed - a slip will cause an audible click Fax A slip can wipe out several lines Modem A slip can cause several seconds of drop out Compressed video A slip can wipe out several lines More slips can freeze frames for several seconds Encrypted/compressed data protocol Slips will reduce transmission throughput Cellular Dropped calls and poor cell handover 18
  • Implications on Performance• Poor network synchronisation means that network performance is not optimized, quality of service is reduced and customers are lost• Implementation of synchronisation in network design enhances Quality of Service for your customers• Protection of your customers traffic means confidence, loyalty and ultimately improved business relationships 19
  • Round Up• So why do we need synchronisation?• What are the 3 main types of synchronisation?• What is a slip?• What can slips cause? 20
  • Chapter 03Sync Distribution Layer 1
  • Network synchronisation• The objective of network synchronisation is to ensure that all the telecommunication systems use the same transmit and receive data rates to avoid slips• So the clocks in the telecommunication systems must be synchronised to the same master network clock, or synchronised to a number of very closely matched master clocks 2
  • Distribution Layer function• To generate a primary reference timing signal• To distribute timing signals from the primary reference source to nodes and equipment• To provide protection against failures in the generation and distribution of timing 3
  • Logical Synchronisation Network Master Clock Telecom equipment clocks 4
  • Master-Slave Mechanism • The clock is injected into the master unit • The slave unit locks to the incoming clock rate and is now synchronised to the master • No slips occur between these elements Transmission LinkData Master Master Slave Slave Data + Clock PRC 1 5
  • Physical synchronisation network• Not every system in the network can have a direct connection to the master network clock• Therefore the telecommunication systems are synchronised in chains or trees• Each system clock is the master clock of the subordinate system clocks slaved to it• The slave system continually adjusts its own clock to the incoming signal• Therefore both the master and slave systems have the same transmit and receive rates• There are no slips (WE HOPE!!!!) 6
  • Clock typesThe clock elements of the synchronisation distributionlayer are categorised in three ways: 1. Primary Reference Clock (PRC) - This is defined by ITU-T recommendation G.811 2. Synchronisation Supply Unit (SSU) - The purpose of these elements is to provide filtering and regeneration - Defined by ITU-T recommendation G.812 3. SDH Equipment Clock (SEC) - These devices have an internal SDH Equipment Clock (SEC) that is normally synchronised to a traffic or an external timing input signal - Defined by ITU-T recommendation G.813 7
  • Master-slave principle PRC = master SEC SEC = slave SEC SEC = slave SSU SSU = slave SEC SEC SEC SEC = slave SEC SEC SEC SEC = slaveSSU SSU SSU = slave 8
  • Sync Distribution (SD) Trails - 1• The clock frequency along an SD trail is the SAME as the head-end, i.e. PRC, SSU or SEC• SD trails can be very long or very short• There can be hundreds of SD trails in a synchronisation network 9
  • Sync Distribution (SD) Trails - 2• There are several types of SD trails: – PRC SD trail - when the head-end is a PRC – SSU SD trail - when the head-end is a SSU – SEC SD trail - when the head-end is a SEC• SSU and SEC SD trails are created only when the PRC SD trail is broken 10
  • Physical synchronisation networknetwork Physical synchronisation clock quality clock quality traceable back traceable back to the SEC to the SSU SEC SSU SEC SD trail PRC SSU SD trail PRC SD trail clock quality traceable back to the PRC 11
  • Slip Rate due to Freq Deviation For 2 Mbit/s signals, frame duration = 125 microseconds: – 10-11 = 1 slip in 4.8 months PRC G.811 – 10-10 = 1 slip in 14.5 days SSU G.812 – 10-9 = 1 slip in 1.45 days SSU G.812 – 10-8 = 6.9 slips per day SEC G.813 – 10-7 = 2.9 slips per hour SEC G.813 – 10-6 = 28.8 slips per hour SEC G.813 – 10-5 = 4.8 slips per minute SEC G.813 12
  • Calculating Slip RatesNormal Calculation for Slip Rates per observation period is: Slip Rate = F x T x D LF= Frequency OffsetT= Observation TimeD= Data RateL= Frame Length 13
  • Calculating Slip Rates – Exercise! Calculate the Slip Rate for the following conditions: F= Frequency Offset = 1 x 10E-08 T= Observation Time = 86400 Seconds (1 day) D= Data Rate = 2.048Mbps x 10E+06 L= Frame Length = 256 What clock quality would this slip rate equal? 14
  • Calculating Slip Rates – ResultThe Solution:F (1x10E-08) x T(86400) x D(2.048x10E+06) L(256)= 6.912 or 7 slips per day!F= Frequency Offset = 1 x 10E-08T= Observation Time = 86400 SecondsD= Data Rate = 2.048E+06L= Frame Length = 256So 7 slips per day is G.813 or SEC in HOLDOVER 15
  • Sync Distribution (SD) Trails - 3 • The synchronisation distribution trails are not perfect: what comes out is not exactly what went in • This is due to: - Equipment and cables generate jitter and wander - Excessive jitter or wander causes slips - Equipment or cables can fail 16
  • Jitter• Pattern, or pattern-dependent, jitter is sometimes called "flanging". This type of jitter is not random; it generally results from sub-harmonics• Viewed in the time domain, this type of jitter appears as multiple modes. Pattern jitter is deterministic jitter that can be attributed to a unique source. All other jitter is stochastic (random) in natureJitter can be quantitatively expressed in the following ways: – In unit intervals (UIs). One UI is one cycle of the clock frequency. Jitter expressed in UIs describes the magnitude of the jitter as a decimal fraction of one UI – In degrees. Jitter expressed in degrees describes the magnitude of the jitter in units of degree for which one cycle equals 360° – In absolute time. Jitter expressed in units of time describes the magnitude of the jitter in appropriate orders of magnitude, usually picoseconds. – As a power measurement in units of radians or unit intervals squared, which is often expressed in decibels relative to one cycle squared 17
  • Wander• Because it involves low frequencies for long periods, wander data can consist of hours of phase information.• Because phase transients are of importance, high temporal resolution is also needed. So to provide a concise measure of synchronisation quality, three wander parameters have been defined and are used to specify performance limits: - TIE Time Interval Error (wander in ns) - MTIE Maximum Time Interval Error (related to Peak- to-Peak wander) - TDEV Time Deviation (related to RMS wander) 18
  • Definition of Jitter Definition of Jitter : ITU- Rec G.810 • The short term variations of the significant instances of a digital signal from their reference positions in time • Greater than 10Hz in modulation frequency • Jitter is caused by the sync trail equipmentIdealJittered Sampling (reading) points 19
  • Definition of Wander• The long term variations of the significant instances of a digital signal from their reference positions in time• Less than 10Hz in modulation frequency• Wander is caused by the interaction of technologies in a network IdealWander Sampling points Sampling points 20
  • Main Causes of Jitter/WanderJitter/Wander is caused by the sync trail equipment For Example: – MUX / Switch equipment PLL – Poor equipment component quality – Proximity of components to EMI – Microprocessor noise – Equipment Transfer functions – Length of transmission paths due to cable expansion and contractions – Inter-reaction of different technologies e.g. SDH, PDH, ATM 21
  • PLL Effects on Reference Signals • PLL can overcompensate and oscillate above and below the reference • PLL can under-compensate and take too long to get to the reference • Changes in Temperature effect the stability of the OCXO • Jitter is generated by granularity (steps) in correction voltage applied to the OCXO 22
  • Jitter/Wander summary 23
  • Cable Expansion/Contraction Wc = 80ps/Km/oC, for fibre optical cable Wc = 725ps/Km/oC, for copper cable20oC 101011100101010100000110010100010001040oC Cable has expanded - the bits come out later 1010111001010101000001100101000100010 0oC Cable has contracted - the bits come out earlier 1010111001010101000001100101000100010 24
  • ITU-T G.823 Model of Wander• Specifies the maximum network limits for jitter and wander that should not be exceeded• Specifies the minimum equipment tolerance to jitter and wander based on the 2048 kbit/s hierarchy• The jitter control philosophy is based on the need: - to recommend a maximum network limit that should not be exceeded at any hierarchical interface - to recommend a consistent framework for the specification of individual digital equipments - to provide sufficient information and guidelines for organizations to measure and study jitter accumulation in any network configuration 25
  • ITU-T G.823 Wander formula• The maximum relative wander between the slave clock and the data input at a node is: Dwpk = WequipPk + WconnectionsPk + < / = 18µs• The formula allows the planner to calculate the accumulated Wander by simply adding the sum of each element within the network• This total must be less than 18µs to adhere to G.823 26
  • ITU-T G.823 Network Wander PRC PRC Cable A Cable C Wa = 6 Microseconds Wc = 6 Microseconds Total Wander = 18microsecondsEquipment Wander = Slave Slave Equipment Wander = Slave Slave1 microsecond 1 microsecond Cable B Wb = 4 MicrosecondsThis diagram demonstrates the effect of accumulative wander 27
  • The control of jitter and wander• SDH requires that jitter and wander be kept below tight network limits.• This is achieved by inserting narrow-bandwidth SSUs in the synchronisation chain (SEC bandwidth is relatively wide).• Narrow-bandwidth SSUs attenuate jitter and wander components that lie outside the SSU bandwidth. 28
  • Sync Distribution in SDH - Rules PRC SEC SEC SEC N x SECs SEC SEC SEC N = 20 Max Level 1 SASE SASE SASE Level = 10 Max SEC SEC SEC N x SECs Maximum 60 SEC SEC SEC SECs in a single trail Level 2 SASE SASE SASE SEC SEC SEC N x SECs SEC SEC SEC 29
  • Synchronisation reference chain• See ITU-T G.803 or ETS 300 462-2• The ITU-T/ETS synchronisation reference chain meets the network limits on jitter and wander: – Not more than 60 SECs in a chain – Not more than 20 SECs between two SSUs – Not more than 10 SSUs in the chain 30
  • Distribution Layer composition The SDH Synchronisation distribution layer is comprised of 3 parts: 1. Clocks 2. Equipment 3. Links 31
  • Round Up• What are the two main causes of synchronisation problems?• What equipment is normally at the top of a sync tree?• What is the maximum allowed wander under G.823? 32
  • Chapter 04Sync Distribution Layer - Clocks 1
  • Distribution Layer Clocks• The clock element of the synchronisation distribution layer is categorised in three ways: 1. Primary Reference Clock (PRC) 2. Synchronisation Supply Unit (SSU) 3. SDH Equipment Clock (SEC) 2
  • PRC Systems• The PRC System is a master clock used to synchronise the entire network with a frequency accuracy of < 1 x 10-11• This is defined by ITU-T recommendation G.811.• A complete Primary Reference Clock consists of the following: – 3 separate Primary Reference Sources – Reference Selector – Tracking Unit – Output Distribution Unit 3
  • Typical PRC SASE Unit GPS 1 Input Tracking stage & Oscillator OutputCaesium 1 reference Section Section SelectorCaesium 2 4
  • Primary Reference Source• This is a single source of G.811 Reference which is used to feed a PRC or can be used as a standalone reference• This can take two forms: 1. Caesium reference source 2. Off air source i.e. GPS, Loran, GLONASS 5
  • Caesium PRS• These elements are usually expensive items but provide the network with its own source of synchronisation – The beam can last up to 10 years before requiring a re-tube – They provide a stability of 1x10-11 over 20 years – Where two beams are compared the maximum difference between the two beams equates to 2x10-11 which will result in 1 slip every 72 days on E1 links – This is the standard set by ITU and can be found in ITU-T G.811 6
  • Off-air PRS• Off-air Primary Reference Sources provide an excellent alternative or additional reference to Caesium• This is a single source of G.811 Reference which is used to feed a PRC or can be used as a standalone reference• Off-air Primary Reference Sources include: – Global Positioning Systems (GPS) – Loran – GLONASS GPS is the most commonly used 7
  • GPS as a PRS• The raw GPS signal contains various information including UTC time and identification data for navigation purposes• The GPS satellites contain Caesium beams which are used to provide the accuracy needed for time and location information• In Telecoms it is the stability of the Satellites Caesium that is of interest. Therefore receivers used in telecoms are specific to the requirement• The signal is received by the GPS receiver and is converted into a useable source for slaving a local oscillator. The resulting output is G.811 compliant and therefore is suitable to be used within a PRC 8
  • PRS Operation• Three PRS sources are fed into an SASE (Stand Alone Synchronisation Equipment). This forms the hub of the PRC• The SASE is normally configured to be completely redundant. It will contain an input stage, a prioritising and selection mechanism to determine which source it will utilise, a tracking oscillator unit and an output stage 9
  • Which PRS is Best?• Technically both are perfectly acceptable sources. The differing factor is mainly down to cost• On the surface GPS looks like a cheap option, but beware, it is not always easy to obtain permission from landlords to fit antenna systems and the cost of installation can be more than the cost of the units• When deciding on a solution look at the cost of each of the options and consult your vendor as to what is most cost effective• Most common forms of PRC use a combination of different types of PRS 10
  • Oscillators• PLL – Phase Lock Loop – The Most common form of slaving an oscillator – This function employs a feedback mechanism which feeds the Oscillator output into a comparator where the signal is compared with the input and the difference is sent as correction voltages to the oscillator 11
  • Phase Lock LoopSimple Block Diagram of a Phase Lock Loop Phase Comparator Error Error Correction Voltage Input S1 + Pulses Low Pass Voltage Controlled Filter Output Referenc Oscillator e - S2 Frequency Divider (optional) Feedback Path 12
  • Slaved Oscillator Mechanisms• DDS – Direct Digital Synthesis – A mechanism in which the Oscillator is free running and the output signal is synthesised in software with the incoming reference signal to produce a stable output 13
  • Chapter 05 Sync DistributionLayer - Equipment 1
  • Synchronisation Elements• SASE - Stand Alone Synchronisation Equipment• SSU - Synchronisation Supply Unit• TNC - Transit Node Clock• CTO - Compact Tracking Oscillator• BITS - Building Integrated Timing Supply – All refer to the same class of equipment – Used with PRCs or standalone for regenerating timing signals – Modular by design and configured to be redundant to allow for single or multiple internal and/or external failures 2
  • The SASE• SASE stands for Stand Alone Synchronisation Equipment (Element)• The purpose of these elements is to provide filtering, regeneration and distribution of a primary reference signal• This is achieved by simple yet highly accurate equipment• The equipment is designed to be very resilient to internal and external failures therefore all components are at least duplicated 3
  • SASE Architecture Output Input Jitter/Wander InterfaceInterface Low-Pass Filter Output Input Reference InterfaceInterface Selector Output Interface Input Holdover OutputInterface Memory Interface 4
  • SASE – Input Section• Inputs – Most SASEs have multiple input capability, allowing the unit to select from a number of references – The amount and type of inputs are dependent upon the make and model. For regeneration purposes, 2 or 3 inputs are sufficient 5
  • SASE – Reference Selectors• Reference Selectors – Within each SASE will be the reference selector. Normally this is duplicated for redundancy. This section contains the priority table and selection criteria for the units inputs – Selection can be made by the following methods • Automatic • Manual • Forced • Synchronisation Status Message (SSM) 6
  • SASE - Selection ModesSelection Modes Automatic – This mode will choose the highest available priority source set within the priority table Manual – This mode will only switch to another available input by manual intervention Forced – This mode will stay fixed to its intended sync source at all times SSM – The selection is dictated by the incoming SSM information 7
  • SASE - Fltering & Holdover• Filtering & Holdover section – This section of the unit provides the filtering of the reference signal. This can be achieved using two techniques: - Phase Lock Loop - PLL - Direct Digital Synthesis - DDS – This section should be duplicated for redundancy – All SASEs employ a mechanism which prevents phase and frequency jumps when switching between channels 8
  • SASE – Output Section• Output Stages – Most SASE output arrays allow for different output frequencies to be used. 2.048Mhz is the most common for SDH but 1MHz, 10MHz, E1 Framed, etc. can all be generated by the SASE. Consult your vendor if specific frequencies are required – Again these can be configured to provide protection in the event of a hardware failure – Cards can be fitted with differing protocols. In some units the framing and bit pattern of E1 or T1 signals can be altered to generate AIS and other states. Units may also have the ability to change output protocol by means of software, e.g. 2.048Mbps to 2.048Mhz 9
  • Which SASE Configuration?• When deciding which equipment is right for your network, it is important to look at the application first• SASEs can be fitted with an array of different cards and clock types• Review the importance of the location and the equipment the SASE is to be connected to, before deciding on oscillator types and configuration• Typically, SASEs should be used within the core of the transmission network 10
  • SDU – Sync Distribution Unit• The purpose of the SDU is to expand the capacity of an SASE O/P• The SDU typically has two I/Ps and no Hold over capability• The SDU will have a large O/P capacity - consider it as an amplifier for Synchronisation signals• An SDU will typically be referenced from an SASE or SSU 11
  • SDU – Layout Output Interface Input Low Loss SplitterInterface Output Interface Input OutputInterface Interface Output Interface 12
  • SDU – Inputs• SDU Inputs – The SDU will normally have two input Interface Units, these are typically 2Mhz. Jitter can be filtered on these units – The SDU I/P reference source are often derived from an associated SASE / SSU – SDUs can be daisy-chained: however the lack of holdover and wander filtering make this undesirable – Some manufacturers have incorporated a HOU (Hold Over Unit) capability - this is normally for a single channel 13
  • SDU – Outputs• SDU Outputs – The SDU is designed as a low cost, high O/P capacity option – Most SDU output arrays allow for different output frequencies to be used. 2.048Mhz is the most common for SDH but 1MHz, 10MHz, E1 Framed, etc. can all be generated by the SASE. Consult your vendor if specific frequencies are required – Again, these can be configured to provide protection in the event of a hardware failure 14
  • SDH Elements• With the possible exception (depending on manufacturer) of the Optical Line Amplifiers, all the following equipments contain SECs (SDH Equipment Clocks) and should be counted within the trail count for SDH design: – Add Drop Multiplexers -- Microwave Systems – Cross-Connects -- Regenerators – Optical Line Amplifiers This internal SEC is normally synchronised to a traffic or external timing input signal Traffic & Traffic & timing 1 SEC timing input output External External timing n timing input output 15
  • SDH Equipment Clock (SEC) Synchronous Equipment Timing Source (SETS) STM-N input Selector C External timing output (2MHz or 1.5 Mbit/s, or SDH Equipment 2Mbit/s) PDH input Clock Synchronous Equipment NEExternal timing Timinginput Generator internal(2 MHz or timing1.5 Mbit/s or2Mbit/s) 16
  • SDH SEC features• Input synchronisation signals are: • STM-N aggregates and tributaries • 2Mbit/s tributaries • 2MHz and 2Mbit/s (non traffic) timing inputs• Input selection is determined by: • a priority table, that is user definable • Synchronisation Status Message (SSM) on the STM- N and 2Mbit/s interfaces• Output synchronisation signals are: • All STM-N aggregates and tributaries • 2MHz and 2Mbit/s (non traffic) timing outputs 17
  • SEC Timing options• Line timing: in nodes not equipped with a node clock (SSU)• External timing: in nodes equipped with a node clock• Tributary timing: only in exceptional cases, e.g. during the evolution from PDH to SDH• Internal timing: when all synchronisation reference signals are lost (= holdover mode) 18
  • SEC Line Timing• Line timing: in nodes not equipped with a node clock (SSU)• Timing is extracted from the STM-N (optical overhead)• In normal operating conditions timing is traceable to a G.811 primary reference Line timing STM-N STM- STM-N STM- 19
  • SEC External Timing• External timing: in nodes equipped with a node clock • Used for synchronisation injection points within the network • Normally either a 2 MHz or 2 Mbit/s reference signal • Node clock traceable to G.811 Primary Refence Source • Node Clock has G.812 holdover capability External timing STM-N STM- STM-N STM- 2 MHz or 2Mbit/s 20
  • SEC Internal Timing• Internal timing: when all external timing references are lost • Intended for failure conditions • SEC Clock has G.813 holdover capability Internal timing STM-N STM- STM-N STM- 21
  • SEC Timing Outputs• If a 1.5Mbit/s, 2MHz, 2Mbit/s synchronisation output is derived from the Synchronous Equipment Timing Generator (SETG), then it is called a SETG locked output• If a 1.5Mbit/s, 2MHz, 2Mbit/s synchronisation output is directly derived from the OC-N or STM-N input, then it is called a non-SETG locked output• The 2MHz timing output can be squelched when : • The SEC enters hold-over or free-run mode • The input SSM falls below the set threshold 22
  • SEC - Selection Modes• Automatic – This mode will choose the highest available priority source set within the priority table• Manual – This mode will only switch to another available input by manual intervention• Forced – This mode will stay fixed to its intended sync source at all times• SSM – The selection is dictated by the incoming SSM information 23
  • Inter-working: SDH NE & SASE SDH NE Noisy cleanedtraffic & traffic & timing timing input outputs External External timing timing output input SASE 24
  • Round Up• What are the 3 main equipment types found in the sync distribution layer?• What is a SEC?• What provides the higher clock order - PRS or SEC?• What is the difference between a SASE and an SEC? 25
  • Chapter 06Sync Distribution Layer - Links 1
  • SDH Sync Link connections - 1• Supported by an SDH multiplex section traili.e. the timing information is carried by the STM-N data rate (N x 155 Mbit/s) by a retimed PDH E1 connection• SDH regenerator timing generators are not counted as elements of the synchronisation distribution layer, they belong to the synchronisation link connection• The SDH multiplex section trail may be supported by an optical transport layer such as DWDM (dense Wavelength Division Multiplexing) or OTN (Optical Transport Network) 2
  • SDH Sync Link connections - 2 PRC SSU Synchronisation Synchronisation link connection SDH SDH SDH/SONET SDH Multiplex section trail OTN OTN OTN/DWDM Optical Trail 3
  • Types of Oscillators in Links• Oscillators are a common section of all of the three clock types described• Various types of oscillators exist and their selection is based upon the application, i.e. PRC, SASE or SEC, that they are to be utilised within• The main types of crystal oscillators are: – Caesium – High Quality Rubidium – Low Quality Rubidium – High Stability Double Oven OCXO – Single Oven OCXO – Temperature Controlled TCXO 4
  • Rubidium Oscillators• Atomic Standard Tracking Oscillators are extremely stable and thus are very suitable for using within a telecom network• Typically these oscillators are used within a Primary Reference System as Slaved units to Caesium or GPS• These are usually the most expensive tracking oscillators available• They have a life span varying from 6 to 12 years, depending on Manufacturer• The longer life span of Rubidium oscillators is achieved using DDS rather than PLL techniques within the clock element• Usually Maintenance Free• Holdover Quality dependent on Manufacturer, typically 1x10-11/mth 5
  • Single Oven OCXO• Relatively inexpensive OCXO• Provides Holdover of 1x10-9 to 1x10-10 per day depending on Manufacturer• Usually suited for Standby oscillators within SASEs or as Local Node Clock Systems• They will also be found in Large transit Switches and X- Connects 6
  • High Stab. Double Oven OCXO• Life span of 20+ years• Maintenance free• Lower cost than Rubidium• Holdover is typically 1x10-11/day• Can be used in a Primary Reference System or as a SASE Oscillator 7
  • Temperature Controlled TCXO• Inexpensive Oscillators• Maintenance free• Used in a majority of Telecom equipment such as Multiplexers and Radio Systems• Holdover of 1x10-6 per day or less 8
  • Typical Oscillator PerformanceOscillator Type Holdover Quality Slip Rate (Typical) (Worst Case)Rubidium 1x10-11/m 1 after monthLow cost 5x10-11/m 1 after weekRubidiumHigh Stability 1x10-11/d 1 after 3.5 daysDouble OvenOCXOSingle Oven 2x10-10/d 1 after 1 dayOCXOTCXO 2x10-6/d 1400 per day 9
  • Oscillator Characteristics• Oscillators are susceptible to changes in temperature and stability of rectified power• Variations in these conditions can affect the performance of the oscillator 10
  • Retimed PDH Sync Link - 1• PDH path layers supported by SDH path layers are not suitable for transporting synchronisation• Retiming is used when E1 traffic signals transported over SDH are used as synchronisation links (e.g. to synchronise distant PABXs or GSM BTSs)• Retiming is applied on E1 traffic signals affected by excessive wander (e.g. from pointer adjustments)• Retiming buffers can be integrated in the SDH network element or the SASE 11
  • Retimed PDH Sync Link - 2 SDH network element SECSTM- timing signal N PDH SEC tributary output Retiming re-timed re- Buffer PDH PDH signal tributary Retiming re-timed re- output Buffer PDH PDH signal tributary output Retiming re-timed re- Buffer PDH signal 12
  • Retiming• The retiming buffer transmits the incoming traffic at the data rate of the SEC timing signal, thus removing the excessive wander• The long-term frequency (data rate) of the E1 traffic signal must be synchronized to the network PRC• Slips will occur if the SEC has lost its synchronisation to the PRC 13
  • Round Up• What is the synchronisation link layer?• How is synchronisation transported from site to site?• How is synchronisation delivered within the node?• Name 3 Oscillator types 14
  • Chapter 07 SDHNetwork Topology 1
  • Master-Slave Principle• A designated master clock is used as a reference frequency generator• The frequency generated by the master clock is disseminated to all other clocks which are slaved to the master clock 2
  • Master-Slave Mechanism • The clock is injected into the master unit • The slave unit locks to the incoming clock rate and is synchronised to the master • No slips occur between these elements Transmission LinkData Master Master Slave Slave Data + Clock PRC 1 3
  • Master-slave principle PRC = master SEC SEC = slave SEC SEC = slave SSU SSU = slave SEC SEC SEC SEC = slave SEC SEC SEC SEC = slaveSSU SSU SSU = slave 4
  • Principle of trail redundancy• Each slave clock should get at least two reference signals from the master clock via geographically separate trails• Sometimes it is not possible to fulfil this principle for all nodes of the network (depending on connectivity) 5
  • Hierarchy of Quality Levels• There is a hierarchy of clock quality levels• The higher the clock quality level, the higher the frequency accuracy of the clock• Frequency accuracy = – either overall free-run accuracy or holdover accuracy over a limited time period 6
  • Clock Quality Levels2048 kbit/s based: 1544 kbit/s based:PRC: 1E-11 PRC: 1E-11SSU I: 2E-10/d SSU II: 1.6E-8/1yrSEC 1: 4.6E-6 SSU III/IV: 4.6E-6 SEC 2: 20E-6 7
  • Weak Hierarchical Distribution RULE • A clock of a given quality level must always (even under failure conditions) take timing (directly or indirectly) from a source clock with the same or higher quality level 8
  • Implementing the RuleQuestion:• How can we implement the Weak Hierarchical Distribution Rule? ..........Answer:• By implementing the Strong Hierarchical Distribution Rule: « A clock of a given quality level must take timing (directly) from a clock with the same or higher quality level »• Or by the use of SSM signalling 9
  • Strict Hierarchical Layering PRC SSU SSU SSU SSU SSU SEC SEC SEC SEC SEC SEC SECSEC SEC SEC 10
  • Failure Scenario PRC SEC SEC Link failure! SEC SEC SSU SSU Holdover mode! SEC SEC SEC SEC SEC SEC SEC SECSSU SSU SSU 11
  • Sync network with SSM• There is a link failure within a chain of SECs• The SSM signalling prevents the downstream SSU from following a SEC in holdover mode• Instead, the downstream SSU enters holdover mode and becomes the source clock for the cut off sub-network 12
  • The control of jitter and wander• SDH requires that jitter and wander be kept below tight network limits• This is achieved by inserting narrow-bandwidth SSUs in the synchronisation chain (SEC bandwidth is relatively wide)• Narrow-bandwidth SSUs attenuate jitter and wander components that lie outside the SSU bandwidth 13
  • Sync Distribution in SDH PRC SEC SEC SECN x SECs N = 20 Max SEC SEC SECLevel 1 SASE SASE SASE Maximum 60 SEC SEC SEC SECs in aN x SECs single trail SEC SEC SECLevel 2 SASE SASE SASE Maximum 10 SEC SEC SEC SASEs in aN x SECs single trail SEC SEC SEC 14
  • Synchronisation reference chain• See ITU-T G.803 or ETS 300 462-2• The ITU-T/ETS synchronisation reference chain meets the network limits on jitter and wander: – Not more than 60 SECs in a chain – Not more than 20 SECs between two SSUs – Not more than 10 SSUs in the chain 15
  • Summary SSU SynchronisationPRC PSTN PSTNSDH SDH SDH/SONETOTN OTN OTN 16
  • Synchronisation Signalling layerFunction:• To provide the source clock quality level from clock to clock down the synchronisation chains, in order to: – Enable clocks to select the best available reference timing signal – Enable clocks to go into holdover mode if reference timing signals are of low quality – Prevent timing loops in SDH chains and rings 17
  • SDH Sync Status Messages• The clock source quality level is indicated by the Synchronisation Status Message (SSM)• In SDH, the message set is: • QL-PRC = PRC, G.811 • QL-SSU-A = SSU, G.812 Type I or V • QL-SSU-B = SSU, G.812 Type VI • QL-SEC = SEC, G.813 Option 1 • QL-DNU = Do not use 18
  • SSM Transmission Channels• The timing quality level carried by STM-N signals (SDH) is indicated by the S1 byte in the STM-N Multiplex Section Over Head (MSOH)• The timing quality level carried over 2048 kbit/s synchronisation signals is indicated in one of the bits Sa4 to Sa8 in Time Slot Zero (TS0)• 1544 kbit/s T1 signals: see ITU-T Rec. G.704• 34 Mbit/s E3 and 140 Mbit/s E4 signals: see ITU-T Rec. G-832 19
  • SSM Algorithm• Always select the highest quality input and if a number of equal quality timing inputs are available, then select the highest priority timing input• In locked mode, the output SSMs are set to the selected input SSM e.g. G.811 in = G.811 out• The SSM in the return direction of the selected input is automatically set to Do Not Use (DNU) 20
  • If all inputs are bad ...• The SEC enters holdover mode…• The SEC memorises the phase and frequency values of the last known good input, but quickly drifts toward 4.6 x 10-6• The SEC will be in free-run mode if it has never locked to a higher level reference signal• Ext Clock Out signals should be squelched• Output SSM STM-n value is set to G.813 (unless manually set)• Unfortunately, SECs inject jitter on to the PRC signal and accumulative jitter can cause slips 21
  • SDH ring sync protection• Automatic SSM correction and automatic synchronisation distribution trail reconfiguration under failure conditions – Using the SSM algorithm• Revertive operation – SD trails returns to the original paths when the failed section or the failed network element has been repaired• No operator action is needed 22
  • Revertive/Non-Rev Switching• Revertive switching will allow previously disqualified inputs to be re-qualified and re-selected as the selected source• Non-Revertive switching will not allow previously disqualified inputs to be re-selected if they return to a useable reference• Pro’s & Con’s are associated with either option. The operator must decide which method to use as a standard for the whole network 23
  • Chapter 08 SynchronisationNetwork Architecture 1
  • Centralised or Distributed PRC• Two methods of deploying PRCs are utilised in today’s networks: – Centralised – Distributed• A combination of both methods is also a valid strategy for Synchronisation 2
  • Centralised PRCs - 1• This method was typically used by operators when PDH systems were used as the main transmission media.• This method, utilised 2 or 3 fully equipped PRC’s located separately. The clock was embedded within the E1 bearer on the Primary Multiplexers and distributed over the PDH to the Exchanges.• Each PRC system typically employed three Caesium beams for redundancy.• These systems were expensive to purchase and required maintenance to be carried out. 3
  • Centralised PRCs - 2• In today’s networks the Centralised PRC is still supported and is still valid for timing SDH.• With the onslaught of new technologies and transport mechanisms, new operators have approached the issue of network synchronisation differently.• Preferring to have multiple low cost PRS clocks situated all around the network – Distributed PRCs. 4
  • Physical ViewThe PRC distributes timing through master slaveSynchronous Equipment Clocks.All elements are traceable to the PRC SEC SEC SEC SEC SEC Equipment Clocks PRC SEC SEC SEC SEC SEC PRC = Primary Reference Clock SEC SECSEC 5
  • Distributed PRS - 1• There are many primary reference sources distributed in the network• The most common form of PRS utilised for this purpose is GPS• The GPS satellite system distributes USNO-UTC-derived time and timing to all GPS-clocks• Each GPS-clock is the master of a synchronization subnetwork• This is also referred to as decentralised PRCs 6
  • Distributed PRS - 2• This mode of clocking is favoured by the new operators. Mainly due to having isolated sites or regions which are linked by lines, leased from the incumbent carrier• In this instance, trace-ability is lost when transported over another operators network. Therefore, installing primary reference sources at all sites ensured synchronisation quality is maintained 7
  • Distributed PRS - 3 Leased Transmission LinkData Master Master Master Master Data + Clock PRS 1 PRS 2• Each element or node is timed by a separate high stability clock• These are virtually identical speeds (accuracy of 1x1011)• Will cause one slip every 72 days - perfectly acceptable 8
  • Physical View Region 1Region 2 SEC SEC SEC SEC SEC SEC PRC PRC SEC SEC Local SEC SEC Equipment Clocks SEC SEC SEC Timing Feeds Traffic Links PRC SEC SEC PRC… Primary Reference Clock Region 3 SEC…SDH Element Clock 9
  • Mixed sync distribution - 1• Mixed synchronisation network architectures offer a combination of benefits from centralised and distributed PRS solutions • Less wander due to short synchronisation chains • Simplified network design • Easy to modify the network (evolution) • Low risk of creating timing loops 10
  • Mixed sync distribution - 2 n n n n n n G G G n n n n n n M n n n n n n G G G n n n n n n central node equipmentG GPS-clock M master n clock clock Sub-network clock 11
  • Sync entirely based on GPS• It is technically feasible to deploy one GPS-clock per node• Less wander due to very short synchronization chains• Very simple network design• Easy to modify the network (evolution) • Very low risk of creating timing loops • Not robust enough, since there is only one synchronization reference signal available (dual GPS receivers do not provide protection against interference and jamming!) - no trail redundancy • Not economical for very large networks with many nodes, because of total equipment cost 12
  • Which Strategy is Best? - 1• There are benefits and drawbacks to both options. Both methods are perfectly acceptable• With distributed GPS there is a cost impact for installation and technically speaking there are multiple boundaries inside the network• Plan for a failure. If one GPS fails the network must be able to recover from a standby GPS or if possible from a GPS at an adjacent site 13
  • Which Strategy is Best? - 2• With a centralised PRC careful planning is required to prevent timing loops• Inter oscillator chain length can be large, so regenerator units such as SASE’s are required• If planned correctly this can be a more cost effective way of synchronising the network• All elements will be traceable to one Master Clock 14
  • Equipment cost model Totalequipment cost GPS-BASED SYNCHRONISATION DISTRIBUTION: (single GPS + SASE) per node WIRED (PDH- OR SDH-BASED) SYNCHRONIZATION DISTRIBUTION: one central PRC with 3 Cs clocks, and one SASE per node number of nodes or 60-80 synchronisation sub networks 15
  • Sync from a co-operating Nwk - 1 • Most common when there is no PRC in the network • All clocks in the network are slaved to synchronization signals from a co-operating network • Under normal operating conditions all slave clocks operate at the same frequency as the PRC in the co- operating network • There are normally no slip for on-net and off-net traffic to the co-operating network 16
  • Sync from a co-operating Nwk - 2 • The clock signals from the co-operating network may be received at only a few synchronisation gateway nodes • The clock signals from the co-operating network may also be received at every node, or at every sub-network 17
  • Sync from a co-op Nwk - Issues • The network’s synchronisation performance is dependent on the quality of the synchronisation signals from the co-operating network • There must be an agreement with the co-operating operator on service level • The cost to lease the synchronisation signals can be high 18
  • Agreement on sync interfaces• Physical interface specification (e.g. 2 Mbit/s, G.703)• SSM configuration• Guaranteed synchronization quality (e.g. G.823 Network Limit)• Upstream synchronisation chain length (number of clocks)• Guaranteed availability of agreed quality (e.g. 0.9999)• Mean Time to Repair in case of failure• Worst case quality degradation in case of failure (e.g. max. frequency error, max. frequency drift, max. jitter & wander)• Alarming method in case of failure (e.g. SSM)• Quality monitoring criteria 19
  • Round Up• What is a master slave clock arrangement?• What is a centralised PRC system?• What is a de-centralised PRC system?• Which system is best?• Give two examples of a PRS 20
  • Chapter 09Synchronisation Standards 1
  • Standardisation Bodies• International level : ITU Recommendations• Regional level, Europe: ETSI Legally binding standards• USA: ANSI Legally binding standards• Industry level: e.g. TIA Industry standards• Company level: e.g. Bellcore Internal standards ITU : International Telecommunication Union ETSI : European Telecommunications Standards Institute ANSI : American National Standards Institute TIA: Telecommunication Industry Association 2
  • ITU-T Recommendations 3
  • ITU-T Rec. G.810• Definitions for synchronisation networks• Includes the definitions of time error, MTIE, TDEV, etc. 4
  • ITU-T Rec. G.803• Architecture of SDH transport networks• Section 8.2: architecture of SDH-based synchronisation networks• Section 8.2.4: synchronization network reference chain 5
  • ITU-T Rec. G.823 (11/98)• The control of jitter and wander in PDH networks based on the 2048 kbit/s hierarchy: 1. Maximum network limits on jitter and wander 2. Minimum equipment tolerance to jitter and wander 6
  • G.823 - What does it specify?• Network limits for traffic interfaces• Network limits for synchronization interfaces• Jitter and wander tolerance of traffic interfaces 7
  • ITU-T Rec. G.824• The control of jitter and wander in PDH networks based on the 1544 kbit/s hierarchy• Similar to ITU-T Rec. G.823, but for the 1544 kbit/s based PDH network 8
  • ITU-T Rec. G.825• The control of jitter and wander in SDH networks based on the 2048 kbit/s hierarchy• Similar to ITU-T Rec. G.823, but for SDH networks 9
  • ITU-T Rec. G.811• Specification for Primary Reference Clocks (PRC)• It is an equipment specification• Specifies only one PRC type 10
  • G.811 - What does it specify? • Frequency accuracy • Noise generation • Phase discontinuity in case of internal protection switching 11
  • ITU-T Rec. G.812 (6/98)• Specification for Node Clocks (Node Clock is the ITU-T term for SSU)• It is an equipment specification• Specifies six SSU types 12
  • ITU-T Rec. G.812 - SSU Types SSU Type Which hierarchy? Primary Application Which case? Type I 2048 kbit/s Sync. chains as long as G.803 reference chains Type II 1544 kbit/s Distribution hubs (1) single input reference ; Type III 1544 kbit/s End offices (1) Type IV 1544 kbit/s If used in SDH: must also comply with G.813 option 2 Type V 1544 & 2048 kbit/s Existing (2)transit nodes; same as TNC G.812 - 1988 Type VI 2048 kbit/s Existing (2)local nodes; same as LNC G.812 - 1988Note (1): see Bellcore terminologyNote (2): prior to introduction of SDH 13
  • G.812 - What does it specify?• Frequency Accuracy• Pull-in, hold-in, and pull-out ranges• Noise tolerance• Noise generation• Noise transfer• Transient response in case of input reference switching• Holdover performance• Phase discontinuity in case of internal protection switching 14
  • ITU-T Rec. G.813• Specification for SDH Equipment Clocks (SEC)• It is an equipment specification• Specifies two SEC types: – SEC Option A: 2048 kbit/s hierarchy – SEC Option B: 1544 kbit/s hierarchy 15
  • G.813 - What does it specify?• Frequency Accuracy• Pull-in, hold-in, and pull-out ranges• Noise tolerance• Noise generation• Noise transfer• Transient response in case of input reference switching• Holdover performance• Phase response to input signal interruption• Phase discontinuity in case of internal protection switching 16
  • Round Up• What does ITU-T G.811 specify?• What does ITU-T G.812 specify?• What does ITU-T G.813 specify?• How many levels are defined under G.812? 17
  • Chapter 10 Sync E(Synchronous Ethernet) 1
  • What’s driving the industry?•Networks migrating to Packet but mission-critical Comms and Data need accurate timing Today: Hybrid Network•Must continue to provide the same Ethernet Base Station quality of synchronisation delivered TDM today by TDM Core•Can this be done without the need Network to retain the T1/E1 links used today Future: to transfer synchronisation? Ethernet-only Base Station 2 2 2
  • Sync-E and IEEE1588V2 compared Synchronous Ethernet delivers Frequency Only Application Frequency Time GSM 50 ppb N/A• Regular heartbeat on link signal provides frequency UMTS/ W-CDMA 50 ppb N/A synchronization. UMTS/ W-CDMA 250 ppb N/A femtocells 16 ppb, suggested GSM, UMTS, LTE to meet 50ppb RF N/A IEEE1588V2 delivers Frequency, Phase & ToD Network Interface specification • less than 100 nanosecond (target 50nS) CDMA2000 50 ppb Should +/-3µs, shall +/- time-of-day precision over Ethernet LAN. 10µs TD-SCDMA 50 ppb +/- 1.5µs • Less than 1µs time-of-day precision over LTE (FDD) 50 ppb N/A switched Ethernet WAN. +/- 1.5µs small cell, +/- LTE (TDD) 50 ppb 5µs large cell • stable frequency (1.6x10-8 or 16ppb) +/- 1-32µs, recovery (from time-of-day reference). LTE MBSFN 50 ppb implementation dependent LTE-A CoMP (Network +/- 500 ns (0.5 µs), 1588V2 CAN MEET & EXCEED MOBILE MIMO) 50 ppb pre-standard NETWORK REQUIREMENTS 2 ppm absolute, +/-1 - 8 µs, WiMAX (TDD) ~50 ppb between implementation base stations dependent 3
  • Building a Nwk with SyncE/1588v2 G.8260 (Definition) Agreed Ongoing Consent Definitions / G.8260 Dec2011 terminology (metrics) Frequency: G.826x Time/Phase:G.827x G.8261 G.8271 Basics SyncE NetwkJitter-Wander: G.8271.1 Network Included in G.8261 (NetwkPDV_time/phase requirements G.8261.1 G.8271.2 (NetwkPDV_frequency) may be needed in future G.8262 G.8272 73.1-GM Clock (SyncE) PRTC 73.2 BC G.8263 G.8273 73.3 TC G.8264 (SyncE-architecture) Methods G.8275 G.8265 (Packet-architecture-Frequency)) (Packet-architecture-time) G.8265.1 G.8275.1 Profiles (PTPprofileFrequency) (PTPprofileTime/phase) G.8265.m G.8275.n (PTP Profile frequency m) (PTPprofileTime/phase n) ITU-T Standards 4
  • Synchronous Ethernet (SyncE)– Line rate of the Ethernet Interface used to transfer timing– No impact/demand on packet layers– Defines the use of a high stability oscillator to generate line frequency – Ethernet ‘Classic’: ±100ppm – Synchronous Ethernet: ±4.6ppm– ITU-T Standards in place • G.8262: Timing Characteristics for Synchronous Ethernet Equipment • G.8261: Timing & Synchronisation in Packet Networks • G.8264: Distribution of Timing Through Packet Networks (ESMC) 5
  • Challenges• Cost: All interfaces need to be Sync-E compatible• Cannot be used with existing Ethernet equipment when transferring synchronisation ~ PRC ~ PRC 6
  • Conformance Testing - Jitter Sync-E (1GbE/10GbE) ITU-T G.8262 EEC 1G/10G SyncE 1G/10G SyncE Jitter Generation Jitter Tolerance 7
  • Conformance Testing - Wander Sync-E (100M/1GbE/10GbE) ITU-T G.8262 Frequency Accuracy Synchronisation Source Pull-in, Pull-out, Hold-inReference Wander generation Wander tolerance EEC 100M/1G/10G SyncE Wander transfer 100M/1G/10G SyncE Phase transient response Reference SyncE (Wander-free) EEC SyncE Under Test 8
  • Jitter/Wander measurement narrow-band filter (jitterless) internal wide-band filter (jittered) internal 9
  • Sync architecture for Sync-E PRC G.812 Type I (SSU) Number of G.812 type I clocks < 10 SEC SEC G.8262 isNumber of G.813 option 1 SEC EEC Compatible clocks < 20 with G.813 SEC EEC Total number of G.813 clocks in a sychronisation trail SEC SEC should not exceed 60 G.812 Type I (SSU) 10
  • White Paper & Application Note 11
  • G.8260Metrics 1588v2 Network pktfilteredMTIE Metrics – released as ratified by ITU-T Includes pktfilteredMTIE, MATIE, MAFE, etc. 12
  • G.8261 – Appendix VISlave Clock (Frequency) Test (Old) Apply G.8261 or Network Profiles, Measure E1/T1 MTIE/TDEV (now) Stress multiple slaves with G.8261 or Network Profile (H1 2012) Stress multiple slaves with multiple profiles (H2 2012) 13
  • G.8263Slave Clock (Frequency) Test (New) Apply G.8263 Profile, Measure E1/T1 MTIE/TDEV (now) Apply G.8263 Profile to multiple slaves, Measure E1/T1 MTIE/TDEV (H1 2012) Apply G.8263 Profile to multiple slaves, Measure multiple E1/T1 MTIE/TDEV (H2 2012) 14
  • Introducing ESMC• ESMC: Ethernet Synchronization Messaging Channel• ESMC has been built first and foremost as the transport channel for SSM (QL) over Synchronous Ethernet links• Key outcome: Simple and efficient• ESMC does not aim to become a complex protocol• However, in the future it may support some extensions• It is not a control plane and does not need a control plane 15
  • G.8264 – ESMC testingStimulus to EEC Response from EEC 1.ESMC = PRC1. ESMC = PRC 2.Wander locked to Synchronisation Clock Source Reference with Freq 10MHz, 2.048MHz, E1, T1 1.ESMC changes to EEC1/2 offset 2.Wander shows offset as2. ESMC = DNU EEC now locked to local clock Paragon GUI 1.ESMC changes to PRC &3. ESMC = PRC 2.Wander locked to reference TimeMonitor Change QL of •Wander Graph Port 2 ESMC shows Line EEC Clock Rate 100M/1G SyncE switching into Port 1 (Wander free) and out of Holdover ESMC with EEC •ESMC Graph defined QL shows ESMC messages changing state to reflect status 16
  • Chapter 11 IEEE 1588v2 - PTP(Precision Timing Protocol) 1
  • Packet Sync Technologies• Separate packet flow used to transfer timing – Timestamps embedded in packets to transfer timing – Two-way protocol employed to measure delay between Master and Slave devices• Able to transfer frequency (syntonisation) and phase/time- of-day (synchronisation)• Standards define devices/techniques to reduce uncertainty (Peer-to-peer & End-to-end Transparent Clocks) and to create hierarchical clocking topology (Ordinary Clocks, Boundary Clocks) 2
  • Standards• IEEE: 1588v2; Precision Timing Protocol, PTP• IETF: RFC1305; Network Time Protocol, NTPv3, RFC5905: NTPv4 (TICTOC group) Deployed by Ericsson• ITU-T: G.8264; Distribution of Timing through Packet Networks 3
  • IEEE 1588v2 (PTP)Benefits: – 1588v2 Standard ratified March 2008 – Independent of services – Suitable for layered/complex clock distribution topologies – Compatible with currently deployed packet networksDrawbacks: – Cost: Extra bandwidth required – Protocol assumes symmetrical delays in up- and down-stream paths – Sensitivity to PDV 4
  • IEEE1588 Network Sync - 1Phase 1 - Establishes the Master-Slave hierarchy via the session protocol and a local state machine 5
  • Phase 1 - Session ManagementSession Start-up Master Slave Clock Clock ce) Signalling (Re quest Announ Announce and Signaling Signalling (Ac messages configure and knowledge) maintain the clocking quest Sync) structure - they include: Signalling (Re Signalling (A cknow ledge ) • Clocking Topology • Grand Master identity p) quest Del_res and priority Signalling (Re Signalling (A cknowledge • Timestamps ) • Current UTC offset 6
  • IEEE1588 Network Sync - 2Phase 2 - Synchronises the clocks Master Slave Clock Clock 1) Mean Progation Delay Tmpd = (T2 – T1) – (T4 – T3) 2 2) Clock offset correction Offset = T2 – T1 – tmpd *simple model 3) Slave Clock Synchronisation *Calculation differs by vendor 7
  • Phase 2 – Slave Clock SyncPropagation Delay Message Exchange Master Slave Clock Clock t1 Sync t-ms Clock Output must comply with the t2 relevant ITU-T clock specification (MTIE & TDEV specification) Follow_Up t3 G.81x series of specifications t-sm Delay_Req (G.823/4 for TDM delivery) t4 Delay_Resp 8
  • Time Transfer Example Assume at an instant in time: Master clock value = 100 seconds Slave clock value = 150 secondsMaster Clock Slave Clock Data At (the slave clock error = 50 seconds) Slave Clock One way path delay = 2 seconds Sync message is sent at t = 100 seconds t1 For illustration, Delay_Req is sent 5 seconds after sync (t •2s the Sync message is received: 1) t2 t1 = 100 seconds Round Trip Delay t2 = 152 seconds RTD = (t2 - t1) + (t4 - t3) (150+2) RTD = (152 - 100) + (109 - 157) t) re q(ues t3 RTD = 4 seconds delay_ t3 = 157 seconds (152+5) Slave clock error eliminated t4 delay_ re sp(on Slave Clock Error = (t2 - t1) - (RTD ÷ 2) s e) (t4 ) = (152 - 100) - (4 ÷ 2) = 50 seconds t4 = 109 seconds (100+2+2+5) Round trip error eliminated If the slave clock is adjusted by -50 seconds, the Master & Slave will be synchronized. 9
  • Influences on 1588v2 AccuracyPacket Delay Variation Prolonged Packet(PDV) appears as a Loss (Outage) –Causes clock recovery processchange in frequency or to enter holdoverphase of the recoveredclock Slave Performance –Increases with number of Vendor A – PDV tolerance – X network elements and traffic load Vendor B – PDV tolerance – Y –Multiple causes, including queuing delays, routing changes, Packet Delay, Packet congestion, use of switches versus routers, etc. Loss, and Packet Errors are not anNetwork asymmetry issue for packet timing protocols 10
  • Today’s test challenges (G.8261)• Building a ref. network/designing algorithms is time- consuming and expensive• Not repeatable (varying behaviour) and inconsistent (many different implementations)• Does it truly represent YOUR network? 11
  • 1588v2 Slave (Ordinary Clock)• In a network with legacy routers, PDV and Asymmetry accumulation (in each direction) can be significant• Slave clock recovery is a challenge PDV Accumulation Master Router Router Router Router Slave Clock Clock 12
  • Testing 1588v2 Ordinary Clocks• Testing 1588v2 Ordinary Clocks involves applying PDV and testing the recovered Slave clock – Connect equipment as shown – Apply PDV profile – Test recovered clock to ITU-T limits 13
  • G.8261 – Appendix VISlave Clock (Frequency) Test (Old) • Apply G.8261 or Network Profiles, Measure E1/T1 MTIE/TDEV (now) • Stress multiple slaves with G.8261 or Network Profile (H1 2012) • Stress multiple slaves with multiple profiles (H2 2012) 14
  • G.8263Slave Clock (Frequency) Test (New) • Apply G.8263 Profile, Measure E1/T1 MTIE/TDEV (now) • Apply G.8263 Profile to multiple slaves, Measure E1/T1 MTIE/TDEV (H1 2012) • Apply G.8263 Profile to multiple slaves, Measure multiple E1/T1 MTIE/TDEV (H2 2012) 15
  • Chapter 12 Boundary andTransparent Clocks 1
  • Boundary Clocks Boundary Clocks reduce PDV accumulation by: • Terminating the PTP flow and recovering the reference timing • Generating a new PTP flowQ1 using the local time reference, (locked to the recovered time) Clock Q2 • There is no direct transfer of Master Slave Qn PDV from input to output A Boundary Clock is in effect a back-to-back Slave+Master 2
  • 1588v2 with Boundary Clocks• BCs recover and re-generate the 1588v2 clocking• With a network of BCs, PDV contribution (per hop) is only from BC and link• PDV experienced by Slave is minimised PDV PDV PDV PDV PDV Master BC BC BC BC Slave Clock Clock 3
  • Boundary Clocks - Specifications• The ITU-T are working on a performance specification, to appear in G.8273.2• Considered performance areas: 1) Frequency/Time Accuracy 2) Noise Generation 3) Noise Tolerance 4) Noise Transfer 5) Phase Response 6) Holdover 4
  • Boundary Clocks - G.8273.2Conformance Testing - Wander ~ ~Master ClockMaster Clock Slave Clock Master Clock Master Clock Slave Clock BC BC Master Clock Frequency Accuracy Noise generation Phase transient Noise tolerance response Holdover Noise transfer 5
  • Transparent Clocks Transparent Clocks reduce PDV by: • Calculating the time a PTP packet resides in the TC device (in nsec) and inserting the value into the CorrectionField • Using the CorrectionField, the Slave or Q1 terminating BC can effectively remove the PDV introduced by the TC Q2 Qn Packet Delay in TC Device inserted into correctionFieldat output of Transparent Clock device 6
  • 1588v2 with Transparent Clocks PDV Accumulation Master TC TC TC TC Slave Clock Clock PDV is written by each TC into CorrectionField and this accumulates, so CorrectionField = PDV End Slave removes PDV Accumulation at the End Slave Accumulation using CorrectionField 7
  • Transparent Clocks - Specifications • Performance specifications will be given in ITU-T G.8273.3 • IEEE C.37.238 specifies less than 50ns error for a TC. • The performance of a TC is essentially the accuracy of the CorrectionField • This accuracy must be tested in the presence of traffic for forward path (Sync) and return path (Del-req). • (Note 1-step and 2-step methods differ in the location of the CorrectionField) • Tests should be done with varying congestion traffic: Packet size, traffic priority and utilisation 8
  • Transparent Clock Test Plan CorrectionField Accuracy Connect as shown, and broadcast Traffic Generator traffic on all ports of the TC ~•MasterMaster •`1` Clock Slave •`1` Clock 1. Capture PDV before and after TC TC, with CorrectionField 2. Perform differential calculation Traffic Generator of PDV - Confirm CorrectionField error is <50ns 3. Repeat under multiple trafficTest Procedure to measure conditions:accuracy of CorrectionField 1. Vary traffic packet size 2. Vary traffic priority 3. Vary traffic utilisation 9
  • Packet /Traffic Generator Errors ~ e.g. GPS TC Traffic Generator Claim: Emulating Master and Slave can verify CorrectionField accuracy • TC has 50ns error limit (e.g. IEEE C.37.238) • TC test equipment must have better accuracy – Meeting the ns challenge • Even synchronised to GPS, hardware architecture of traffic generators has 10’s/100’s of ns error. So these are not fit for purpose • Paragon is accurate to 5ns and fit for purpose. 10
  • The 1µs ChallengeAn increasing number of applications requireaccurate transfer of frequency and time throughEthernet networks:•TDD base stations – need phase synchronisation to 1µs accuracy•High Frequency Trading (HFT) – needs 1µs timestamp resolution•Power Substations – specify a maximum time variation through a system of 1µs•For Mobile Backhaul – frequency accuracy must be better than 16ppb 11
  • Test Boundary/Transparent Clocks Confirming 1µs accuracy • The 1µs inaccuracy limit is for a network as a whole – but each network element plays a part • Standards bodies are creating performance specs for BCs and TCs • Errors in a BC or TC can only be a fraction of 1µs – Standards (e.g. IEEE C.37.238) propose 50ns limits • Test equipment must be accurate to ns – Traffic Generators/Packet Capture Platforms have 10’s if not 100’s of ns error 12
  • Network Conditions in the LabCapture PDV profiles from . . . then replay the real-world PDV profiles back in your lab.live or trial networks . . . •MKR-1:x=894.874691063, y=0.000360070 •x=895.477518835 •Delta: x=0.000000000, y=0.000000000 •MKR-2:x=894.874691063, y=0.000360070 •y=0.000444870 •0.000645879 •Time Interval •Erro r (TIE) TDM-o-Ethernet •vs Nominal •(seconds) Core Network Base Station •-0.000296349 •894.478017335 •894.977768110 •895.477518885 •T (a) •Offset=0.002 pp m TDM . . . additionally: Record and replay from G.8261 Reference Network (Removes repeatability issues and minimizes resource effort.) Use PDVs from a library of profiles (including G.8261, MEF-18) Generate pseudo-real world profiles (edit real-world profiles to test margins of operation and clock recovery) Generate theoretical models (Gamma or Gaussian PDV distributions) 13
  • Chapter 13Clock Measurements 1
  • Clock Performance measurements 2
  • Tie Interval Error (TIE)TIE (sec) 3
  • Maximum Time Int Error (MTIE) 4
  • Time Deviation (TDEV) 1 10 100 1000 10000 100000 5
  • Modified Allen Deviation (MDEV) 6
  • G.8271.1 Ntwk PDV – Time/Phase 1588v2 GPS Network 1588v2 Slave 1pps ToD Accuracy 1588v2 Master pktfilteredMTIE LAB NETWORK Lab – G.8271.1 profiles stress Slave, 1pps and ToD accuracy measured Network – Measure Network PDV pktfilteredMTIE to G.8271.1/G.8260 (available on ratification of G.8271.1) 7
  • G.8273.2 – Boundary Clock Test GPSRef Ref 1588v2 BC 1588v2 + PDV + Traffic BC 1pps ToD 1pps ToD 1588v2 + PDV + Traffic Frequency+Time Accuracy Pull-in, Pull-out, Hold-in Phase transient response Noise generation Noise tolerance Noise transfer 8
  • G.8273.3 – Transparent Clock Test GPS Ref TC 1588v2 + PDV + Traffic 1588v2 + PDV + Traffic Measure Latency vs Correction Field 9
  • Chapter 14CALNEX Testing 1
  • Testing E1/2.048MHzPRC Node-B E1 Clock out MTIE/TDEV against G.823 PDH Interface masks 2
  • Testing 10MHzPRC Node-B 10MHz Clock out Calnex Freq Converter MTIE/TDEV against G.823 PDH Interface masks 3
  • Testing Sync-EPRC Node B MTIE/TDEV against G.8261 Opt1 mask 4
  • Testing 1588v2 Delay Distribution 1588v2 Forward PDV 1588v2 Protocol AnalysisGPS 1588v2 Reverse PDV Node-B1588v2Master(RNC) 1588v2 pktMTIE (future) 5
  • How to measure Forward PDV Master Slave Clock Clock MKR-1:x=894.874691063, y=0.000360070 x=895.477518835 Delta: x=0.000000000, y=0.000000000 MKR-2:x=894.874691063, y=0.000360070 y=0.000444870 0.000645879 t1 Sync t-ms Time Interval Erro r (TIE) vs Nominal (seconds) t2 Follow_Up -0.000296349 894.478017335 894.977768110 895.477518885 T (a) Offset=0.002 pp m t3 t-sm Sync PDV Delay_Req t4 • Paragon uses timestamp from Sync message to calculate Sync PDV Delay_Resp • Sync PDV = variation of (arrival time at Paragon – timestamp) Propagation Delay Message Exchange Does Master > Slave PDV impact clock recovery? 6
  • How to measure Reverse PDV Master Slave Clock Clock MKR-1:x=894.874691063, y=0.000360070 x=895.477518835 Delta: x=0.000000000, y=0.000000000 MKR-2:x=894.874691063, y=0.000360070 y=0.000444870 0.000645879 t1 Sync t-ms Time Interval Erro r (TIE) vs Nominal (seconds) t2 Follow_Up -0.000296349 894.478017335 894.977768110 895.477518885 T (a) Offset=0.002 pp m t3 t-sm Delay_Req PDV Delay_Req t4 • Measure variation between the launch time of the Delay_Req message (arrival time of Delay_Resp Del_Req in Paragon) and the embedded timestamp, t4, in the corresponding Delay_Resp message Propagation Delay Message Exchange Does Slave > Master PDV impact clock recovery? 7
  • Simultaneous Measurements Delay Distribution 1588v2 Protocol Analysis 1588v2 Forward PDV 1588v2 Protocol Analysis GPS 1588v2 Reverse PDV Node-B 1588v2 Forward PDV 1588v2 Reverse PDV Delay Distribution Sync-E MTIE / TDEV E1/T1 MTIE / TDEV E1/T1 MTIE / TDEV Hybrid 1pps ToD Accuracy 1588v2Master and Sync-E MTIE / TDEVSync-E EEC 1pps ToD Accuracy ESMC Monitor / Overwrite ESMC Monitor / Overwrite ALL AT THE SAME TIME! 8
  • Calnex ProductsParagon Paragon-X Paragon-m• Lab & Field up to 1G • Lab & Field up to 10G • Field up to 1G• 1588v2, SyncE, CES, NTP, • 1588v2, SyncE, CES, NTP, • 1588v2, SyncE, CES, NTP, OAM OAM OAM • E1/T1 and 1pps • E1/T1 and 1pps Portable GPS Rubidium reference • Provides stable frequency (10MHz) and 1pps reference in the field • GPS Antenna and cables included 9