PB 1990-2009 AN 02 DWN & DWV MODELING OF ACTIVE COMPONENTSThe fast growth of signal integrity equivalents, as those utilized in theand EMC problems of digital transmission line simulators, are The modeling approach shown insystems requires very accurate not sufficient to describe the this application note is based on themodeling techniques of active unpredictable dynamic effects of primitives offered by the DWNcomponents, especially regarding real devices. simulator and allows the designer totheir dynamic behavior at highspeed. On the other hand, thegrowing complexity of systemsimposes severe goals regarding the Ctdr coaxsimulation speed. As known thetwo requirements of speed and Z0 DUTaccuracy are opposite, so that the Rtraditional approach to these Vbias vccproblems leads to unsatisfying TDR gnd ground planeresults. SPICE models, forexample, are not suitable for the Fig. 1: Measurement set-up for TDR characterization.simulation of circuits with morethan few hundred elements, A behavioral or mixed electrical- perform very accurate electricalbecause the simulation time rises behavioral approach is much more simulations with a speed at leastprohibitively with circuit effective to face real-world two orders of magnitude greatercomplexity and convergence situations, where the effects of than other commercial products1.problems could occur. active parts, lossless or lossy This modeling procedure is simpleFurthermore, the results often dont interconnections, EMC constraints, and the data can be collected fromreflect the real situations. In fact, and electrical, logical and timing several sources. In particular, it isthe parasitic effects introduced by issues must be taken possible to extract modelthe discontinuities of the package simultaneously into account. parameters from datasheet, fromand the pin bouncing (caused by analog simulations (SPICE, ELDO,simultaneous output switching) DWN MODELING etc.) or, better, directly fromcan often invalidate the results. On APPROACH TDR (Time Domainthe other hand, simple circuital Reflectometer) measurements.1.00 # Thanks to this fast experimental #RHO D approach, the model can take all the0.80 # non-linearities of the I/O cells of0.60 # the device into account, C0.40 # B0.20 # A-0.00 #-0.20 #-0.40 #-0.60 #-0.80 #-1.00 # 1DWN uses a very fast DSP engine that 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 assures high speed without convergence TIME[nS] problems. Fig. 2: TDR response for a CMOS inputHDT Copyright 1990
PB 1990-2009 behavior of the input circuitry (the STF 1 Tin Vout reactive effects of the input gates in 2 1 this particular case). The final value Z0,Td of the transient C (point D) is the 0 + Bin -R 0 5 Vin reflection coefficient determined by E1 the input ohmic resistance of the device under test in parallel with Fig. 3: Simple CMOS input model including logic level shift. the biasing resistor R. It is possible to compensate the error introduced by the resistor R with the insertionas well as its dynamic behavior. the package must be kept as short of a negative resistor -R in theThe currents flowing through the as possible. model description, as shown inmodel are simulated with accuracy The DC biasing of the input is Fig.3. Sweeping the bias voltageand can be used for ground obtained via a variable supply within the possible operation rangebouncing noise analysis and EMI (Vbias). The resistor R is chosen as (0V - 5V) there is no practicalverifications. Furthermore, these high as possible, in order to provide deviation of the behavior shown inTDR-based models are typically a high-impedance path for the Fig.2, so that a simple linear model is suitable for this situation. The .SUBCKT INCMOS 1 2 choice is a mixed TLM * TLM model of package (Transmission Line Modeling) and TIN 1 0 3 0 Z0=75 TD=200PS BTM (Behavioral Time Modeling) * input dynamic behavior approach. In particular the package BIN 3 0 S11=PWL(0 0.2 30PS -0.6 0.6NS -0.5 1.5NS 0.7 2.5NS + 0.85 5NS 1.0) Z0=50 TD=0 effect can be modeled as a short * voltage shifter ("0" -> 0V, "1"->1V) transmission line, while the E1 2 0 4 0 PWL(0V 0 2.4V 0 2.6V 1 5V 1) behavior of the active input is .ENDS INCMOS directly modeled by a PWL one- Fig. 4: Simple CMOS input model description (DWN syntax). port scattering element (Bin)3. The separation of package effectswideband2 and are suitable for reflectometer, but low enough to allows the user to simulate theEMC analysis of even slow bias the input at the desired level. behavior of internal input node socomponents. A typical TDR response is shown that it is possible to extrapolate in Fig.2 where it is possible toSIMPLE CMOS INPUT 10 VDDThis section is dedicated to the Bdvddmodeling of a CMOS input without ASvddprotection diodes. The model is ST Fbased on experimental Pvdd Voutreflectometer characterizations of 1 T in 1 2the input stage of the device. The Z0,Td 0test-fixture is shown in Fig.1. The Vin + 0 5TDR output pulse (typically a Bin Pgnd E1voltage step with 250mV amplitude Bdgndand 25ps rising edge) is fed to the ASgndinput pin of DUT package via aDC-block capacitor and a semi rigid 20 GND50 coax cable. The realization of Fig. 5: CMOS input model including protection diodes and supply pins.the test-fixture must take all high-speed issues into account, so that identify four sections: the peak device responses with otherground and Vdd supply planes must identified by the label A is the packages. If this is not required, abe provided and the interconnection parasitic effect due to the launch whole BTM model can include theof the device to the fixture must cable where it is connected to the package effects.reflect that of real operation. The device under test.connection of the launch cable to The section B is related to package 3 The PWL (PieceWise Linear) fitting of and package-die bond effects. The Bin is easily extracted from the actual2 Current TDR analysis offers band up to section C shows the dynamic behavior using the MCS (Model Capture40 GHz. System) facility of DWV.
PB 1990-20090.60 # clamping diodes for protection0.40 # against electrical discharge, so an Iclamp=0.2MA accurate model must take both their0.20 # non-linear and dynamic effects into-0.00 # account, as shown in Fig.5. In this situation it is necessary to introduce Iclamp=1MA-0.20 # the effect of power and ground pins-0.40 # because during the clamping action the diode current flows through Iclamp=5MA-0.60 # them.-0.80 # Iclamp=20MA-1.00 # 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 V (V) I(mA) TIME[nS] 0.00 0.0 a) 0.50 0.1 0.60 # 0.55 0.3 0.40 # 0.60 0.9 0.20 # 0.65 1.8 Iclamp=0.5MA 0.68 3.8-0.00 # 0.70 10.7-0.20 # Iclamp=1MA 0.72 25.4 Tab.1: Example of static charac--0.40 # teristic of clamping diode.-0.60 # Iclamp=5MA Often each diode has a specific static and dynamic behavior.-0.80 # Iclamp=20MA Sometimes the static characteristic is available from the datasheet with-1.00 # 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 a format similar to tab.1. Biasing TIME[nS] the device at 5.7V (on the DUT b) pin) it is possible to test theFig. 6: Reflectometer response of protection diodes versus clamping current: a) VDD diode, clamping effect toward the supply,b) GND diode. while a bias voltage of -0.7V tests of the ground clamping diode.In order to simulate the I/O timing By changing the current inproperties of the device it is CMOS INPUT WITH clamping conditions, it is possiblepossible to include in the model the PROTECTION DIODES. to collect a family of reflectometerinput static transfer characteristics responses for each protection diode.of the device with output values Usually, a CMOS input has two Fig.6 shows an example of theseshifted to the logical state "0" and"1". In this way the model is 0.60 #directly interfaceable to a core 0.40 #block able to model the timing logicbehavior of the component. Fig.4 0.20 #shows DWN net list of the model -0.00 #composed by the Bin block and thetransmission line that models the -0.20 #package contribution. The level -0.40 #shifter completes the model. DWNuses a SPICE-like syntax and this -0.60 #model can become a DWN sub -0.80 #circuit.Upon the model is completed, it is -1.00 #possible to validate it through a 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 TIME[nS]simulation of the measure set-up Fig. 7: PWL fitting of a clamping diode reflectometer response: the last sample isthat has been used during the extrapolated to -1000m .characterization (see App.A).
PB 1990-2009 10 VDD internal available) or directly from V-I DT F measurements and used for Pvdd Vout E1 and Pgnd (non-linear resistors) descriptions; t Pvdd - plot the TDR dynamic behavior of both protection diodes in ST F sw1 clamping condition (with a suitable Vout 2 1 value of clamping current4). The sw2 Z0,T d bottom value of the response, Bout Vin always higher than -1000m (for DT F Pgnd typical CMOS protection diodes Vout the value ranges from -700m to E2 -900m ), is the reflection t coefficient related to the ohmic 20 GND internal resistance of the diode. Because this resistance has been already Fig. 8: CMOS output behavioral (BTM) model. taken into account by the non- linear resistor Pvdd and Pgnd, it isgraphs for a CMOS EPROM in DIL - extract the package and Bin necessary to compensate this effectpackage. It is interesting to observe descriptions as already explained during the PWL extraction with thethe different behavior of the two related utility MCS of DWV, asdiodes. R( ) shown in Fig.7.The ground diode shows a very fast 1M The dynamic behavior of the VDDresponse so that low impedance sw2 sw1 and GND path through the supplylevels are reached in about a 1K pins is easily modeled in ananosecond. On the contrary, the behavioral way. This can beVdd diode shows a slow transient 1 accomplished by means of the two(several nanoseconds long) before 2.5 5 S-parameter blocks Bdvdd andit reaches low impedance levels. Vcontrol Bdgnd obtained as PWL fittings ofThis slow behavior obviously has Fig. 9: Static characteristics of the two actual TDR behaviors. The twosignificant impact in the clamp switches. series adaptors ASvdd and ASgndaction, so that, if a voltage are used to connect the blocks inovershoot due to reflections occurs, for the model of Fig.3; series to the supply paths. In factit will be effectively clamped onlyafter the delay observed in the TDR 0.60 #characterization. This kind ofsituation is very common and 0.40 #difficult to forecast. This modeling 0.20 # 1MAapproach, based on TDRmeasurement, is the best way to -0.00 #pinpoint these effects. Furthermore, 2MAduring the modeling, the user gets -0.20 #also a lot of information, not 5MA -0.40 #supplied by the manufacturer,concerning the "quality" of the -0.60 # 10MAcomponent he is going to use. 20MATo complete the model shown in -0.80 #Fig.5 the following procedure issuggested: -1.00 # 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 TIME[nS] Fig. 10: TDR responses for an ECL output versus biasing current. - determine the static input the series adaptor connects the one- characteristic of the DUT in normal and clamping conditions. The data can be extracted from datasheet (if 4 It is suggested to increase the clamping current up to its maximum limits.
PB 1990-2009 performed by two switches Pout AS Tout 2 DTF controlled by the output voltage Vout STF Vout Z0,Td itself. The two switches, 1 Eout Bout implemented by voltage controlled Vin t + resistors, have low impedance when closed in order to not affect the 20 GND output impedance value. Fig. 9 Fig. 11: ECL output behavioral model shows suggested static transfer characteristics that could be used to control the switch resistance. Theport element placed at its third port pin bouncing phenomena, as it will current flowing from VDD to thebetween the two nodes be discussed later. load during the 0->1 transition andcorresponding to its remaining from the load to GND during the 1-ports. CMOS OUTPUT. >0 transition is accurately modeled.The TDR dynamic behavior of the Because the switches transitions arediodes in clamping conditions Typically, the outputs of a CMOS not abrupt, also the current feedtakes into account the driver act as linear resistor until a through between power and groundcontributions of all the elements determined output current level is during the transitions is modeled, apresent along the signal path and, reached. Increasing the current typical effect of CMOS circuitry.in particular, the package effect of level, the output enters the The two dynamic characteristics arethe input pin, the diode saturation region, where its modeled directly fromcapacitance, the on-chip power and resistance grows. measurements of the output voltageground rails and the bonding and Other non-linear effects are transient with the driver unloaded,package effects of the power pins. introduced by the output clamp using PWL fitting. The non-linearIf the diode is a "good diode" (that diodes. The proposed model resistors represent the staticmeans that the low impedance accepts logic levels (0,1) as input characteristics of the output stage incondition is achieved in less than 1 and the first STF block (Static both normal and clampingns), its intrinsic dynamic effect is Transfer Function) shifts the conditions.negligible compared with the incoming (logic levels) signal to the The Bout block models the dynamic behavior of the output in normal operating condition. VDD AS A description of the package completes the model. Bvdd out1 in1 IN OUT ECL OUTPUT in2 IN OUT out2 Timing/logic CORE An ECL device presents a strong IN OUT (logic levels) non-linearity of the output resistance at low current levels. In fact, the ECL output is inm IN OUT outn Bgnd implemented by a bipolar emitter follower that has low output GND resistance (normally less than 10 AS at 10mA biasing) for normalFig. 12: Complete device model including logic/timing behavior and simultaneous operating current. During the 1-> 0switching noise effect. transition there are situations inpower and ground distribution desired output levels. The two which the output transistor goeseffects, so that the blocks Bdvdd dynamic transfer functions (DTF) near cut-off and its outputand Bdgnd can be obtained from model the actual behavior of the impedance greatly increases. Fig.10the measured dynamic behavior of output waveform without load. shows the reflectometer response ofthe power pins5. This model The dynamic behavior of the an ECL output with differentallows accurate simulation of the clamping diodes is taken into biasing current for both "1" and "0" account by the dynamic model of logic states. It is possible to point the power pins, as discussed in the out the sensitivity of the ohmic previous section. The switching resistance (given by the right-end5 Extracted from TDR characterizations of between the two logical states is steady-state responses) versus thethe power pins. current.
PB 1990-2009The dynamic behavior is usually output drivers affects the input times (~1 hour). The wide-the same for both "0" and "1" logic stage operation. bandwidth models are also suitablestates6 as well as the static output The core sections model the for EMC analysis and in very high-characteristics. The model structure internal logical functions of the speed applications involving theis shown in Fig.11. device which can be represented by use of new packaging andThe static transfer function logical functions (AND, OR, etc). interconnection technologies, liketranslates the signal from the logic The logic behavior can be modeled the MCMs (Multi-Chip Modules).input levels to ECL output levels. in DWN using voltage controlledThe dynamic transfer function has switches. APPENDIX Abeen represented by a PWL fitting With a correct introduction ofof the output waveform (driver delays along the input, core, or This section describes theunloaded). The non-linear resistor output sections, the macro model validation of the device model thatis described using the V-I staticcharacteristic of the output. The E1=Vcs Ctdr sw1Bout and package models are Modelextracted with the same procedure + 1 underdescribed in the previous sections. testThe pin #20 can be connected td=50ns sw2directly to GND or to other + 25mV/25pscircuitry taking pin bouncing Vtdr Cs=1pF Biaseffects into account. 55ns tPIN BOUNCING EFFECT Fig. 13: Simulation scheme for model validation.All the models proposed for input allows accurate electrical, timing has been created using theand output sections of the device and logic simulation at the same behavioral approach. The model isare suitable for simulations that time. validated through a simulation oftake the simultaneously switching the same measure set-up that hasnoise into account. The model of a CONCLUSION been used for devicecomplex I/O section of a device characterization. The model iswith package effects is shown in The effects of high-speed operation validated by direct comparison ofFig.12. of active devices are very complex the simulated waveforms with theAll the I/O models are coupled by and involve several phenomena. actual ones. A very fast step (25ps)the dynamic behavior of the power The only way to get accurate simulates the TDR pulse. Due to theand ground rails on chip, by the models is through experimental decoupling capacitor connected tobonding wires and the package characterization that can take all the the TDR, the initial transient duringitself. The Bdvdd and Bdgnd effects into account, pinpointing the simulation could be very long.elements are used once and replace unusual operation modes that often In fact, the TDR step must be onlyall the dynamic models of the occur. DWN & DWV allow direct activated after the initial transient isclamping diodes for both input and utilization of the experimental exhausted and when the device isoutput models (with the exception measures to build very accurate and biased at the proper operating point.of "slow" diodes, as previously reliable models without resorting to Fig.13 shows a scheme that can bementioned). The power and ground circuital equivalent. used for the simulation of TDRcoupling allows a good simulation In this way the user is able to build responses. At time 0 the switch sw1of the pin bouncing effect in both up his own library of DWN models is open and the switch sw2 isnormal and clamping operating of active and passive components. closed. The bias generator can be aconditions. It is interesting to point These models can be utilized for current generator with very highout that the macro model (that is fast and accurate simulation of internal impedance or a voltagedescribed as a sub circuit using the digital systems both in the pre- generator with an internal resistorSPICE-like syntax of DWN) layout and in the post-layout phase greater than 10k . The circuit iscouples the input section of the of the design. In order to automate designed in order to use a currentdevice with the output one. As a this type of analysis, DWN & generator for current greater thanconsequence, the noise due to the DWV are interfaced to the most 100µA (for example validating popular CAD/CAE environments clamping diodes) and a voltage through a specific tool (PRESTO) generator for current lower than6 In fact, a unique transistor is active for allowing accurate and exhaustive 100µA (for example testingboth the logical states. simulation of PCB boards in short
PB 1990-2009elements with very high inputimpedance). The values of thecurrent or voltage bias can bepositive or negative (source orsink). After 50ns the device isbiased at the correct operating pointand the generator E1 copies thevoltage present at the pin of themodel. At this time, the twoswitches change condition and astep of 25mV amplitude and 25psrise time is fed to the model. Theamplitude of the signal at the testpoint 1 multiplied by 80 (becauseof the 25mV step) gives thereflectometer response scaledbetween -1000m and +1000m inorder to provide a directcomparison to the TDR measure.