A simultaneous two-way digital transceiver on a single line

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This paper shows the internal structure of a bipolar Integrated circuit (RTB) developed to halve the cost of interconnects within a digital switch.
The RTB has been exploited in the LINEA UT digital switches produced by ITALTEL starting from the years 80. 27 Million lines are served worlwide by these exchanges.

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A simultaneous two-way digital transceiver on a single line

  1. 1. - 250 - ESSCIRC85 RTB: A Full-Duplex ECL Transceiver For Wideband Digital Systems. Piero Belforte Vanni Poletto Mario Sartori - - CSELT (Centro Studi e Laboratori Telecomunicazioni) 1014B Torino (Italy), via G. Reiss Romoli 274, Tel. 39-11-21691 Summary This paper deals with the design of a low cost ECL bipolar compatible I.Cperforming the function of four balanced full-duplex transceivers particularlysuitable for interconnections long up to several tens of meters in digitalsystems. One of the most interesting applications of this circuit is in the field ofwideband digital switching (up to 100 Mbit/sec) where the amount of two-wayinternal connections can be very high, [l] More precisely when bidirectionalvideo communications are concerned (as in the case of the digital switching ofvideo telephony signals) the use of this component virtually halves the wiringcost. Other applications include narrow band (up to 2 Mbit/sec) digital switchingsystems where it is possible to achieve great saving in cabling cost or to allowthe designers to implement interesting diagnosis and signalling schemes insidethe exchange.[2] Obviously his application range is not bounded to these fieldsbut covers all the situations where two-way communication implying the use ofstandard receiver/transmitter pairs is needed. The functional behaviour of RTB is shown in fig. 1: Ct is an ECL driver with a low output inpedance, Ip is a common modecurrent source, Ro is the line characteristic resistance, A1(A2) are linearamplifiers, Cr is a differential to single ended ECL translator. (.) Patents pending
  2. 2. - 251 - When two transceivers sending data through the same line, the signal at areboth end of the line is a superposition of the one transmitted from the localterminal and the one received from the remote terminal. The line signal swing isa bit larger than the standard ECL but down-shifted about .8 V. The circuitsubtracts from the line signal the contribution due to trasmitter, taking intoaccount the 6 dB attenuation caused by the line impedance matching. In idealconditions (lossless cable and negligible output impedance of the driver), it iseasy to show that, if the gain of Al is a half of the gain of A2, a completecancellation of the transmitted signal occurs. In such a way the outputtranslator Cr has the function of restoring the ECL level compatibility. As the circuit recovers the incoming signal wave, it is easy to gaininformation about an abnormal state of the link (cut or shorted). This featurealso supplies a very simple method for testing the circuit; in fact, when the lineis open, the signal decoded at the receiving side of the tranceiver is equal to thetransmitted one, while when it is shorted the complement of the transmittedsignal can be found at the output. Therefore, connecting both open and shortedthe four tranceivers line outputs, allows to check the correct behaviour of thedevice. chip four different functions are present, each one working in a fully In theindependent mode, so attention must be paid to avoid crosstalk among them.For this reason a careful design was made of the common bias circuit to obtainan efficient decoupling. The main goal of thedesign was to achieve the best trade-off between speedand power dissipation. For this reason a new low dissipation switched-load linedriver (*) suitable for ECL circuitry was developed, [fig. 2] The powerconsumption of the drivers is externally programmable according to bit-raterequirements and length of the cable interconnection; this is obtained throughan internally built voltage reference and an external programming resistor. Inthe chips architecture the bias circuit is shared by the four transceivers and a
  3. 3. - 252 -power saving is gained in it owing to the availability of complementary currentmirrors and amplifiers. (*) The I.C. designed following both traditional and new methodological wasapproaches. In particular the optimization of the circuit from the point of viewof speed was carried out using advanced characterization and simulationtechniques. The choice of the sizes and geometries of transistors making up themain circuit blocks (current switches, buffers, etc.) was the consequence oftheir time-domain reflectometer (TDR) characterization. The TDR responseshave been obtained from a set of standard kit-parts available on SGS LLVprocess. From these TDR responses very accurate macromodels of circuit blocksare obtained using fitting programs. The very close integration betweencomputerized measurements and simulation tools allows the designer to obtainvery quickly and easily the optimized parameters of macromodels. [fig. 3] Thesemacromodels and their related parameters are then used to simulate theinternal behaviour, mainly concerning critical paths, in the integrated circuit. Asimilar technique was also utilized for pin level electrical characterization ofthe whole circuit. The real world operation where two similar tranceivers are interconnectedthrough an external lossy cable was then analyzed. In this case the actual cableis directly modeled by its time-domain scattering parameters. Suitablesimulation programs [3] utilize both I.C. and cable models for the analysis ofsituations which are not covered by standard simulation aids. The results ofthese evaluations for various bit-rates and cable lengths are shown in the paper[fig. 4]. Chips photograph and sizes are shown in Fig. 5. Finally the main features of the implemented chip are given includingelectrical performances [fig. 6] and actual measurements in real operatingconditions, [fig. 7] The RTB is now inserted as standard component among telecom I.Cs byS.G.S ATES.
  4. 4. - 253 -Acknowledgments The authors wish to thank particularly Dr. Siligoni and Dr. Garue of S.G.SATES for their useful advices during the developement of the circuit.Bibliography [l] Enzo Garetti Piero Belforte Luciano Gabrieili "New switching techniques for wideband and ISDN environments" International Switching Symposium84 (ISS 84) Florence [2] Piero Belforte Enzo Garetti "A new generation of LSI switching networks" FORUM B3 Geneva. - [3] Piero Belforte Bruno Bostica Giancarlo Guaschino Time domain simulation of lossy interconnections using wave digital networks" International Symposium on Circuits and Systems (ISCAS 82) Roma, May 10-12, 1982
  5. 5. - 254 - snfeUb b -|r.o)¿ -^O-i Po §1 et.ia Fig. 2 - Switched current load f Line.driver. -TWHE J/77Ef? (X) vs. DATA RATE (L=4m-24m FULL DUPLEX)í GAMMA (my) Mp«) 400pl I fSrtflV r(oo).r(R^).-7IOmS equivalent T-2BB NO/VIV circuit response p(Mbiu<.;Fig.3 - Fitting of the emitter follower T.D.R. response Fig. 4 - Time jitter computer evaluation for different using a macromodel. interconnection lengths (100 balanced ribbon cable).
  6. 6. - 255 -- Main electrical characteristics.- Voltage supply 5V +_ lou- Power consumption 660 mW- Input and output levels ECL 10K canpatibile- Typical Input-output delay time (transmitter + receiver) 7 ns IÎ&L _7 . Receivers output Eye patterns in real operating ccnditlans. (TVo functions connected through 8 meter ribbon cable) Upper : 50 M bit/sec. Lower : 100 Kbit/sec uncorrelated. Fig. 5 - Chips photograph (device area 3.2 mm2 pad area = 25%)

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