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- 1. April 15th 2013 Copyright 2013 Piero Belforte1DWS versus Microcap 10: 10 RL-TL cellcascade comparative benchmarkINTRODUCTIONA simple 10-cell RL-TL test circuit has been simulated using twocompletely different simulators: Microcap10 (MC10, evaluationversion) and DWS. The first one is a classical Nodal Analysis Spicefamily simulator with a good model for Transmission Lines (TL).DWS (Digital Wave Simulator) is based on completely differentDSP algorithms (Digital Wave Network equivalent) (Ref.1,2).The RL-TL 10-cell circuit has been chosen because this class ofcircuits is used to model skin effect losses of physicalinterconnects with particular reference to coaxial cables. Thenumber of cascaded cells has been chosen in order to bemanageable by the evaluation version of MC10 that is limited to amaximum of 50 circuit elements.To be sure of the perfect equality of the benchmark circuit for thetwo simulators, its netlist (link model only), extracted by SpicySWAN (Ref. 2,3) has been imported in MC10 and then back to aDWS engine running locally on the same PC. This PC is equippedwith both simulators (DWS,MC10) and with a Chrome WEB
- 2. April 15th 2013 Copyright 2013 Piero Belforte2browser to run Spicy SWAN. Spicy SWAN can be used on the Ipadas well.The DWS simulations have been performed using both SpicySWAN Web browser version and a local DWS application runningon a I7 PC.Due to growing importance of multi-gigabit/s models for cables,the test circuit has been simulated in time domain over a verylarge bandwidth of stimulus signals like 1ps ramp, unit step andmulti-gigahertz frequency sources.
- 3. April 15th 2013 Copyright 2013 Piero Belforte3RL-TL CELLFigure1 shows two possible DWS models of the basic RL-TL cellused in this benchmark. In the link model the inductor is modeledas a 2-port unit-delay ( one time-step, Ref. 1) Transmission Line(TL) . Using the stub model the inductor is modeled by a shortedstub TL of delay equal to time-step/2 connected in parallel to theresistor R1 by means a series adaptor AS0 . This second modelcorresponds to the trapezoidal integration rule (Ref.1).
- 4. April 15th 2013 Copyright 2013 Piero Belforte4Figure 1: Unit RL-TL cell structures for SWAN/DWSRAMP INPUTFigure 2 shows the SWAN/DWS circuit used to evaluate thesimulation error comparing the waveforms of the two models inthe case of a chain of 10 RL-TL cells with a 1 ps ramp input. Theerror has been evaluated at different simulation time steps in therange from 50 attoseconds to 1 femtosecond in a window of200ps.Figure 2: 10-cell RLTL circuit used for evaluation of simulation errors (1ps rampinput)Figures 3 and 4 show the waveforms related to circuit of Figure 2for two different simulation time steps (10 femtoseconds and 50
- 5. April 15th 2013 Copyright 2013 Piero Belforte5attoseconds). The difference (error) between models is less than5mVpp for tstep=10 femtoseconds and less than 1.2uVpp fortstep=.05 fs. The error peak is located in correspondence of theoutput edge. As known the behavior of integration error isproportional to the square of simulation time step. In fact with atime step ratio of 10/.05=20, the max error ratio is 5mV/1.2uV=410. 410 is about the square of 20.Due to two completely different integration methods (link andstub) and to error behavior, the results of fig.3 can be taken as"golden" reference waveform with an approximation in the orderof 1uV.This consideration is very important when evaluating MC10results .Another important consideration has to be made about timestep choice criterion.Dealing with TLs, to keep the TL propagation delay quantizationerror to a minimum, simulation time step has to be an integersub-multiple of TL delays. In our circuit the cell TL delay is 10ps,so any sub-multiple of 10ps is a good choice for modeling TLs.This rule apply for both DWS and MC10. MC10 has the advantageover traditional Spice versions of "fixed time step " feature, sothat the comparison of results (accuracy and simulation times)with DWS can be performed working at the same simulation stepfor both simulators.
- 6. April 15th 2013 Copyright 2013 Piero Belforte6Figure 3: Waveforms of circuit of Fig. 2 with simulation time step= 10fs. Lower group is a detail of the output edge.Bottom waveforms are the differences between models at the input and output respectively.
- 7. April 15th 2013 Copyright 2013 Piero Belforte7Figure 4: Waveforms of circuit of Fig. 2 with simulation time step= 50 attoseconds (.05 fs). Lower group is a detail ofthe output edge. Bottom waveforms are the differences between models at the input and output respectively.In the following figures from 5 to 8 the waveforms at the input and output of thechain of RL-TL cells for a 1ps ramp input stimulus are shown. The simulations werecarried at the same time step for both simulators.In the panoramic view of Figure 5 it is possible to notice a difference on the inputvoltages in the 0-200ps time window. MC shows a peak at the input edge not visiblein the DWS (reference) waveform. Zoomed views are shown in the following figures.The distortion of the ramp behavior in the MC10 simulation is evident and it ishighlighted by the yellow area (Fig.6 and 7) . DWS simulation agrees with thetheoretical behavior because in the first 2ps the first inductance of the chain acts
- 8. April 15th 2013 Copyright 2013 Piero Belforte8like a open circuit (Time constant=Lcell/R cell= 10 pH/1 ohm=10ps) so that theincident wave sees a 1 ohm resistance in series the first tract of TL (50ohm, 10ps).Figure 7 highlights the difference in chains output edge, where the theoreticallycorrect response of DWS (1ps ramp attenuated by the 10 ohm sum of seriesresistances) is replaced by a smoothed and delayed behavior.Even reducing the MC10 time step these differences dont disappear.Figure 5: Comparison between MC10 (upper) and DWS (lower) waveforms for a 1ps ramp input at 1fs time-step ona 200ps window.
- 9. April 15th 2013 Copyright 2013 Piero Belforte9Figure 6: Comparison between MC10 and DWS: detail of input voltage edges for a 1ps ramp input at 5fs time-stepon a 2ps window. In yellow the difference is highlighted.Figure 7: : Comparison between MC10 and DWS: detail of chain output voltage edge for a 1ps ramp on a 2ps(100ps to 102ps) window. In yellow the difference is highlighted.
- 10. April 15th 2013 Copyright 2013 Piero Belforte10In Figure 8 DWS simulation shows a first "tooth" with decaying value (with the 10psRL time constant) in the first 20ps. This first tooth is not present in the MC10simulation, and is replaced by a narrow peak not explainable with circuit theory.MC10 simulation shows a total of 9 "saw-teeth" versus 10 of DWS corresponding to10 RL-TL cells.Figure 9 shows previous MC10 results with different time-steps (1-500fs). The firstsaw-tooth is missing in all waveforms.Figure 8: Comparison between MC10 and DWS: detail of chain input voltage for a 1ps ramp on a 200ps window. Yscale : Ymin=1V Ymax=1.012VFigure 9 : MC10, detail of chain input voltage for a 1ps ramp on a 50ps window. Four different time steps havebeen used (1,10,100,500fs).
- 11. April 15th 2013 Copyright 2013 Piero Belforte11STEP INPUTThe circuit of Figure 2 has been utilized for a step input comparative benchmark bysimply replacing the ramp generator with an ideal step generator. To keep thesimulation error to a minimum, femtosecond range time steps have been utilized inboth simulators over a 200ps time window.Figures 10 and 11 shows the comparisons of MC10 versus DWS responses at theinput and at the output of the RL-TL chain respectively. DWS step response (1 fstime-step) complies with theoretical behavior while MC10 shows aberrations:peaked response at the input and edge dispersion at the output. Even in this caseMC10 behavior practically doesnt change reducing the time -step.Figure 10: Comparison between MC10 (left) and DWS (right): detail of input voltage edges for a step input at 1fstime-step on a 1ps window. In yellow the difference is highlighted.Figure 11: : Comparison between MC10 and DWS: detail of chain output voltage edges for a step input at 1fs time-step on a 1ps window (100ps-101ps). In yellow the difference is highlighted.
- 12. April 15th 2013 Copyright 2013 Piero Belforte12MISMATCHED CONFIGURATIONCircuit of Fig.2 has been utilized in a mismatched case, setting the generatorsresistances R2 and R3 to 10 ohm and termination resistances R0, R1 to 10Gigaohm.Following Figures 12 and 13 show the comparison between MC10 and DWS resultsin this mismatched situation.Figure 12: Comparison between MC10 (upper) and DWS (lower) of chains I/O waveforms in the mismatched case(1ps ramp input). X axis 0-4ns, Y axis 0 4V .Figure 13: Comparison between MC10 (left ) and DWS (right) output waveform details in the mismatched case (1psramp input). X axis 500ps - 700ps , Y axis 2.97V-3.21V .
- 13. April 15th 2013 Copyright 2013 Piero Belforte13Even if the overall waveform behavior seems roughly equivalent, the zoomed viewof Fig. 13 clearly shows differences: In MC10 waveform peaks are clearly evident at"saw-tooth" reflections as well at the final falling edge. These peaks are not visiblein DWS results.SINUSOIDAL INPUTA further comparative test has been carried out using the circuit of Fig.2 replacingthe ramp generators with a 1Thz (period=1ps) sinusoidal sources of 2V amplitude. Inthe following Figures 14 and 15 the results of this test are shown.Figure 14: MC10 results at the input (blue) and output (red) of the RL-TL chain in case of 2V peak amplitude and 1Thz frequency sinusoidal input. 0-200ps time window.Figure 15: DWS results at the input (green) and output (red) of the RL-TL chain in case of 2V peak amplitude and 1Thz frequency sinusoidal input. 0-200ps time window. Here both stub model and link model results aresuperimposed. 1fs time step.
- 14. April 15th 2013 Copyright 2013 Piero Belforte14Figure 16 : MC10 (upper) and DWS (lower) zoomed view of I/O of the RL-TL chain in case of 2V peak amplitude and1 Thz frequency sinusoidal input. About 3 periods of 1ps each are shown.From previous Figures 14, 15 and 16 the differences between MC10 and DWSresults are clearly visible.MC10 (Fig. 14,16) shows a 1.4V peak amplitude at input port and a .8V peakamplitude at the output port, with an unrealistic signal attenuation. This behavior isperfectly in line with the MC10 step response of Figures 10 and 11 showing awrong peaked input and a smoothed output.DWS (Fig. 15,16) shows the correct slight increase of the signal at the input in stepsof 20ps due to backward reflections of the cells. The output amplitude is about .9Vpeak, in line with the theoretical value. In fact, the attenuation at this frequency isdue to 10 ohm total series resistance partition with 50 ohm termination resistors .From Fig. 16 even a different I/O relative phase relationship between MC10 andDWS is clearly visible. At 1Thz the inductances act like open circuits, so input and
- 15. April 15th 2013 Copyright 2013 Piero Belforte15output must be in phase because the total delay of 100ps is a multiple of thewaveform period (1ps). This can be easily verified in the SWAN/DWS result (Fig.16,lower waveform) but not in the MC10 result (Fig.16, upper waveform) where aphase shift of the output is clearly visible.FREE OSCILLATIONS TEST COMPARISONAnother comparative test has been carried out using the circuit of Fig.2 with the 1psramp input in a fully mismatched configuration, with the generator resistance set to0 ohms and RL-TL chain termination set to 10 Gigaohms. In this conditions thewaves going back and forth on the chain of cells cause 5Ghz (period=200ps)decaying oscillations. This is a good test for transmission lines (Ref.9). DWSwaveform maximum absolute error is 1uV peak as shown in Figure 18 .Figure 17 clearly shows that MC10 oscillations are less damped than DWS . Theresidual amplitude at 100ns is about 500mVpp (DWS) compared to about 650mVpp(MC10). This means that the relative amplitude error of MC10 is about +30% at100ns (fixed simulation time step of 20fs).Figure 29 shows the evolution of V-I free oscillation trajectories with Xaxis: chainoutput voltage and Y axis: chain input current. Both link and stub model trajectoriesare shown superimposed (Ref 9).Figure 17 :Free Oscillations test for a fully mismatched configuration on a 100ns time window, chains output :MC10 result on the left, DWS (stub model) on the right. TSTEP=20fs.
- 16. April 15th 2013 Copyright 2013 Piero Belforte16Figure 18: Absolute error of DWS simulation (stub model) at TSET=20fs as difference between output waveformsobtained with 20fs and 5fs time stepsFigure 19: V-I free oscillation trajectories, DWS at 20fs tstep: Xaxis: chain output voltage Y axis: chain input current.Both link model (black)trajectory and stub model (brown) are shown.
- 17. April 15th 2013 Copyright 2013 Piero Belforte17MEASURED SIMULATION TIMESA comparison between simulation elapsed time of MC10 versus DWS has beencarried out in several situations on the same machine (PC with I7 quad core CPU)using the same time step (for MC10 max and/or fixed).One typical example is that of circuit of Fig.2 for DWS (two different chains) and theextracted single-chain RL-TL circuit for MC10. In this situation, for a time window of200ps, the results are the following:MC10 (only one RL-TL chain)Only max time step set to 1 fs sim elapsed time = 125secBoth max t-step and fixed t-step set to 1fs sim elapsed time = 160secDWS (two RL-TL chains, Fig.2)DWS sim time-step= set to 1fs sim elapsed time = .5 secComparing these results DWS shows a speed up factor at equal fixed tstep (similaraccuracy) that is about 320X with respect MC10.Taking into account that circuit complexity of DWS is more than doubled (Fig.3)with respect MC10 circuit DWS/MC10 speed up factor can be evaluated to bemore than 500X.
- 18. April 15th 2013 Copyright 2013 Piero Belforte18CONCLUDING REMARKSFrom the previous comparative benchmark it is evident that MC10, despite having aTransmission Line model better than conventional Spice versions using a lumpedLC equivalent (Ref.6), shows some problems on output waveform behavior at highfrequency. In some situations, simulated waveforms seem roughly similar to thoseobtained from DWS, but several important details dont match. Even trying to uselower simulation time steps or other simulation options as choosing a differentintegration method (Gear instead of Trapezoidal rule etc.) offered by MC10, theseresults dont change appreciably. The free oscillations simulation test (Ref.9) gives aresponse that is less damped than the reference waveform.DWS results can be taken as exact reference because are obtained from twodifferent implementations (link and stub models) with sub-femtosecond simulationtime steps. These results show an absolute error in the order of micro volts and areperfectly in line with theoretical results. DWS error can be easily evaluated asdifference between two simulations performed using different time steps.The elapsed simulation times of DWS are about 500 times faster than MC10.This performance is particularly appreciable when simulating complex circuitalmodels of interconnects requiring hundreds or even thousands cells at low timesteps.Moreover DWS supports the BTM (Behavioral Time Modeling, Ref.7) techniquewhere a the model is described by its S-parameters step response behavior. Using aPWL (Piece Wise Linear) approximation of these behaviors a very fast model can beobtained. The source of these behaviors can be both experimental (e.g. TDRmeasures) or theoretical (analytical models). Simulative sources of BTM are circuitalmodels like the RL-TL chains of cells for or simulated S-parameters obtained fromother tools like EM field simulators. In case of circuital models the speed andaccuracy advantages of DWS are fully exploited because quasi-ideal step response ofcircuital models is required to extract the S-parameters from the complex circuitalmodel (Ref.5).BTM is not allowed in classical NA (Nodal Analysis) tools, while DWS has no problemdealing with this technique due to extreme stability of wave algorithms.
- 19. April 15th 2013 Copyright 2013 Piero Belforte19BTM allow the simulator to gain a further speed up factor of more than 2-3 orders ofmagnitude with respect circuital models.Using BTM, DWS can achieve a speed up factor of 4 to 6 order of magnitude (10,000to 1,000,000 time faster) with respect Spice (MC10) as exhaustively demonstratedby thousands of real design applications (Ref.7,8)For the above mentioned reasons DWS is the best simulation choice for highfrequency or multi-gigabit/sec circuit simulationWEB REFERENCES(1) http://www.slideshare.net/pierobelforte/electrical-simulation-using-digital-wave-networks-iasted-international-symposium-paris-june1985(2) http://www.slideshare.net/PieroBelforte1/spicy-swan-concepts-16663767(3) https://www.ischematics.com/webspicy/portal.py#(4) https://www.ischematics.com/(5) http://www.slideshare.net/PieroBelforte1/2013-pb-prediction-of-rise-time-errors-of-a-cascade-of-equal-behavioral-cells(6) http://www.slideshare.net/PieroBelforte1/2012-trasmission-line-approximation-using-lc-cells-pbdws(7) http://www.slideshare.net/PieroBelforte1/1993-new-modellingsimulationenvironmentpbgen1993fullslidecollection(8) http://www.slideshare.net/PieroBelforte1/swan-dws-story270113pbgoogledrive-16525591(9) http://www.slideshare.net/PieroBelforte1/2012-pb-vi-trajectory-plots-for-transmission-line-models-evaluation
- 20. April 15th 2013 Copyright 2013 Piero Belforte20NOTE : some of Spicy SWAN circuits shown in this paper areavailable in the public libraries available on line at Ischematicswebsite (https://www.ischematics.com/). All simulationsrelated to previous circuits run in few seconds (SWAN mode).

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