The chip, heart of an RFID Tag

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The chip, heart of an RFID Tag

  1. 1. A COMPANY OF THE The chip, heart of an RFID Tag Thierry Roz RFID Business Unit Manager March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 1
  2. 2. EM's Mission Design and production of integrated circuits for the watchmaking industry since 1975 Today more than 90% of its business is outside of the watch industry Microelectronics Industry Watch-making Industry March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 2
  3. 3. EM in the World Colorado Springs - USA Prague – Czech Republic Design Center Design Center Marin - Switzerland Headquarter – Design Center - Fab Bangkok - Thailand Know How centered in Marin – Switzerland Multiple design sites to collect worldwide experience at EM's and its customer's benefits Packages – Electronic Modules March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 3
  4. 4. Introduction Will economy of scale really help massive RFID deployement ? Massive RFID deployement : Nickel Tag or Penny Tag ? One significant part of an RFID tag is the chip. What influences the chip cost ? March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 4
  5. 5. EM RFID Track Record Over 2 billions RFID circuits in the field Sold more than 410 millions RFID chips in 2008 Sells RFID circuits for more than 20 years Among the top 3 RFID chip manufacturers in world March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 5
  6. 6. Market position according ABI research in 2007 With courtesy of ABI research March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 6
  7. 7. EM's RFID Background 20% Standard ICs 80% Custom Specific Product offer in ~20% 125 KHz 13.56 MHz, UHF 2.45 GHz ~80% Low cost silicon supplier with experience in mass production Cooperation with various tag and reader manufacturers March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 7
  8. 8. Item-Level Tagging in Apparel Industry MARKS & SPENCER (UK) To offer the highest possible level of product availabitity to customers Through an accurate and efficient supply chain Right Goods Right Place Right Time 120 Stores March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 8
  9. 9. RFID Label Cost Breakdown Fixed Costs Variable Costs Total Costs Automated lamination Raw material equipment Paper, adhesives, ink Label Amortization costs Logistics, personalization, 30-40% manpower Automated chip/inlay assembly Raw material equipment Substrate, conductor Inlay Amortization costs Manpower 30% Antenna design + RF test facility Production equipment (line) Raw material Amortization costs Silicon, chemicals Silicon Tooling (mask set) Manpower 30-40% Chip design + test facility March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 9
  10. 10. Silicon Cost Driving factors Wafer Cost Function Cost Feature size Standard Cost (ISO, EPC, …) Patent (IP) Costs Economy of scale March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 10
  11. 11. Wafer Costs Raw Material Cost Manufacturing Costs Programming, Testing Conditionning Backlapping Sawing Bumping Delivery Format (wafer, straps, …) March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 11
  12. 12. Function Cost Function (anticollision, command interpreter, crypto) Memory type (Read Only, WORM, R-W, Flash) Mixed signal (sensors, A/D, …) RF technology (High frequency) Higher complexity => lower features size March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 12
  13. 13. Average Wafer Cost vs. Feature Size 5.0 4.5 4.0 3.5 Cost Factor 3.0 2.5 2.0 1.5 1.0 0.5 0.0 90nm 0.13um 0.18um 0.25um 0.35um 0.50um 1.00um Feature size Source Selantec 2006 March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 13
  14. 14. Feature size : scribe line cost 75.6% usable surface 91.5% usable surface March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 14
  15. 15. Reducing feature size ok, but… Reduce die size to carry more chips per wafer, there are limits: Currently, few inlay manufacturers are able to efficiently handle chips smaller than 500 μm in size. Some functions do not scale efficiently with process Usable vs. unusable wafer surface ratio decreasing with chip size Conclusion There is a critical minimum surface under which reducing die size will increase handling and material costs again March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 15
  16. 16. Impact of Standard Benefits: Enables mass adoption for cross user deployment in open systems / environments Drawbacks: All user requirements considered with the same importance Compromises often lead to complex solutions Slow development Evolving Standards (ISO14443, ISO18000) March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 16
  17. 17. Standard Costs EM4122 EM4122 EM4223 -- ISO18000-6A EM4223 ISO18000-6A 600 gates 600 gates 3500 gates 3500 gates EM4223 twice the surface of EM4122 (same techno) EM4223 twice the surface of EM4122 (same techno) EPC C1G2 complexity = 12'000 gates EPC C1G2 complexity = 12'000 gates March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 17
  18. 18. Estimated Evolution of EPC C1G2 Die Size Chip Size Chip Size Chip Size 2007 Today 2010 Class1G2 0.18μm 0.13μm 0.5μm EM TTO EM4123 March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 18
  19. 19. Patent Costs 15000 patents are related to RFID: Patents apply to Protocol, Chip implementation, Chip attachment, Label conversion, Reader design, Usage of the RF spectrum Existing patent claims Typically 5% of chip + 5% of tag price + 7.5% of reader price Latency on patent claims Standards March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 19
  20. 20. Economy of scale : 1 Billions (109) of additional tags per year, distributed over major foundries, will lead to thousands (103) of additional wafers per months and per foundry The economy of scale brought by leveraging on quantities from 100 to 5000 wafers per month is in the range of few percents (%) not factors source Selantec 2006 March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 20
  21. 21. Impact of 1 additional billion chips on production One 8" wafer holds Annual Chip Qty Monthly Wafers 120’000 EPC chips 10 000 000 7 8" wafer equivalent capacity: TSMC 2006 : 8 M 100 000 000 70 World MOS 2006 : 100 M 1 000 000 000 700 1 billion chips => 0.1% TSMC capacity 10 000 000 000 7000 0.008% World MOS capacity March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 21
  22. 22. Conclusions Chip cost is sensitive to feature size Chip cost is affected by additional process features (Memory, Analog,RF...) Chip cost is affected by delivery format (tested, sawn, bump, shipping,…) RFID chip quantities even in billions do not weigh much on world production capacity Golden rule : keep it as simple as possible, don’t pay for features you don’t use ! March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 22
  23. 23. Thank you for your attention Questions ? Thierry Roz ( troz@emmicroelectronic.com ) March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 23

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