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High Speed Design Guideline

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High Speed Design Guideline

High Speed Design Guideline


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  • 1. Do’s and Don’t in high speed schematic design Khodifad Pankaj eInfochips Training and Research Academy Sola, Ahmedabad Abstract Designing high-speed systems requires not only fast components, but also intelligent and careful design. The analog aspect of the devices is as important as the digital. In high-speed systems, noise generation is a prime concern. The high frequencies can radiate and cause interference. The corresponding fast edge rates can result in ringing, reflections, and crosstalk. If unchecked, this noise can seriously degrade system performance. Do’s For High Speed Schematic Design Filtering Noise: To diminish the low-frequency (< 1 kHz) noise caused by the power supply, filter the noise on the power lines at the point where the power connects to the PCB and to each device. Altera recommends placing a 100-µF electrolytic capacitor adjacent to the location where the power supply lines enter the PCB. If using a voltage regulator, place the capacitor immediately after the final stage that provides the VCC signal to the device(s). Capacitors not only filter low-frequency noise from the power supply, but also supply extra current when many outputs switch simultaneously in a circuit. It is important to check the schematics against the guidelines provided for various high speed busses (Clock signals, DDR2, DDR3, PCI express etc) and to correct the errors. It is also imperative that all the pull up/pull down resistors are verified for the value and the voltages provided to the devices are checked. Schematics need to be thoroughly checked since layout is directly cascaded down from the schematics. A small error in the schematic will be harder to find in layout. Layout engineers do not check for the right values; they layout the schematic reports. Reflections on a transmission line can be avoided by using terminations to the transmission line. The most popular terminations used in the digital logic are either end termination or series termination. To diminish the low-frequency (< 1 kHz) noise caused by the power supply, filter the noise on the power lines at the point where the power connects to the PCB and to each device. Altera recommends placing a 100-µF electrolytic capacitor adjacent to the location where the power supply lines enter the PCB. If using a voltage regulator, place the capacitor immediately after the final stage that provides the VCC signal to the device(s). Capacitors not only filter low-frequency noise from the power supply, but also supply extra current when many outputs switch simultaneously in a circuit. Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the board’s ground plane Eliminate sockets whenever possible. Create a programmable ground next to switching pins Use surface mount capacitors to minimize the lead inductance Use low effective series resistance (ESR) capacitors. The ESR should be < 400 mΩ.
  • 2. Use Parallel Capacitors array Bypass capacitor Selection Filtering is standard for power lines. It can also be used on signal lines, but is recommended only as a last resort, when the source of the signal noise cannot be eliminated. EMI filters are commercially manufactured devices designed to attenuate high-frequency noise. They are used primarily to filter out noise in power lines. They act to isolate the power outside the system (referred to as the line) from the power inside the system (referred to as the load). Their effect is bi-directional: they filter out noise going into, and coming out of, the device or board When a line is long, meaning the cable length exceeds one-sixth of the electrical length of a rising edge, the cable needs terminators. Without terminators, reflections at either end of a long cable render signal transmission impossible. Use following Termination Technique: End Terminations Series Terminations Middle Terminators The rise time of an end-terminated circuit, when capacitively loaded, is half that of a series terminated line driving the same load. Most TTL or CMOS logic gates can't source enough current to drive end terminators. You can daisy-chain receivers on an end-terminated line. At low-pulse repetition rates, source terminators dissipate little power. Source terminators have a slower rise time and usually smaller residual reflections than end terminators. Use Capacitive termination at R1C>>Signal Clock Time
  • 3. Combination RC circuits can terminate DC-balanced lines with no wasted quiescent power. Specify both a resistance value tolerance and a power rating on terminating resistors. Use Following Rule For Power System Design: Power Rule 1. Use low-impedance ground connections between gates. Power Rule 2. The impedance between power pins on any two gates should be just as low as the impedance between ground pins. Power Rule 3. There must be a low-impedance path between power and ground. Differential transmission is practically immune to power supply fluctuations Aluminum electrolytics are the workhorse capacitors most often used for board-level bypass. Their characteristics are similar to those of tantalum, which has an even higher dielectric constant at a slightly higher cost. The Z5U dielectric material has a higher dielectric constant than X7R but worse temperature and aging properties. Below 10°C, Z5U is not recommended. The X7R dielectric material has a lower dielectric constant than Z5U, but better temperature and aging properties. Higher-dielectric-constant materials pack more capacitance into a smaller space but have poor temperature coefficients and aging instability. Two or more driver outputs connected in parallel make a convenient and simple high-powered driver. Use Delays Adjustment for Timing Requirement A fixed delay cannot cancel variations in board fabrication or active component delay. An adjustable delay compensates for actual delays, not just nominal delays, elsewhere in the circuit. Whatever form of delay you choose, incorporate its uncertainty in delay into your timing margin calculations. Do Perfect Power Supply Design. Take Care of Component Foot print and Size of Component. Take Care of Component Life time at Selection of component. Don’ts For High Speed Schematic Design Do not daisy-chain receivers on lines having source terminators. Do not under estimate timing analysis of circuit. Do not take any component lightly. Do not go by value of component but other specification is important.
  • 4. Reference 1. http://www.intel.in/content/dam/www/public/us/en/documents/white-papers/high-speed- digital-design-paper.pdf 2. http://www.altera.com/literature/hb/stx2/stx2_sii52012.pdf 3. High Speed Digital Design: A Handbook of Black Magic-Howard Johnson (Author), Martin Graham (Author) 4. http://www.ee.ucla.edu/~brweb/papers/Journals/R%26WDec92_2.pdf 5. http://www.freescale.com/files/32bit/doc/app_note/AN2536.pdf 6. http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=scaa082