Logic gates

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The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.
The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

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Logic gates

  1. 1. Logic Gates Digital Logic and Software Principles © University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License .
  2. 2. <ul><li>The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1 st year undergraduate programme. </li></ul><ul><li>The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments. </li></ul><ul><li>Contents </li></ul><ul><li>AND gate </li></ul><ul><li>Truth Table </li></ul><ul><li>Symbol </li></ul><ul><li>OR gate </li></ul><ul><li>NOT gate </li></ul><ul><li>Exclusive OR EXOR gate </li></ul><ul><li>Not AND NAND gate </li></ul><ul><li>Not OR NOR gate </li></ul><ul><li>Universal Gates </li></ul><ul><li>NOT using NANDs only </li></ul><ul><li>AND using NANDs only </li></ul><ul><li>OR using NANDs only </li></ul><ul><li>Logic Families </li></ul><ul><li>Transistor Transistor Logic TTL </li></ul><ul><li>TTL Gate Packages </li></ul><ul><li>Complementary Metal Oxide Semiconductor Logic CMOS </li></ul><ul><li>TTL and CMOS developments </li></ul><ul><li>Logic Problem. </li></ul><ul><li>Convert the circuit to NAND only. </li></ul><ul><li>Logic Circuits TTL and CMOS </li></ul><ul><li>Credits </li></ul><ul><li>In addition to the resource below, there are supporting documents which should be used in combination with this resource. Please see: </li></ul><ul><li>Holdsworth B, Digital Logic Design, Newnes 2002 </li></ul><ul><li>Crisp J, Introduction to Digital Systems, Newnes 2001 </li></ul>Logic Gates
  3. 3. AND gate <ul><li>e.g. I get up if it is 8-00 a.m. AND it is a weekday </li></ul><ul><li>he said if A = 8-00 a.m. B = weekday and Y = get up </li></ul><ul><li>then he said you can write: </li></ul><ul><li>where the dot represents logical AND. </li></ul><ul><li>He went on to say that if 1 represents TRUE </li></ul><ul><li>and 0 represents FALSE </li></ul><ul><li>then the function can be defined in a truth table. </li></ul>Logic Gates
  4. 4. Truth Table <ul><li>The truth table has an entry for each possible combination of inputs. </li></ul><ul><li>For n inputs there will be 2 n entries … 2 inputs = 4 entries. </li></ul>We can have more than two inputs in which case the only time we would have a 1 out is when all the inputs are true. Logic Gates A B Y 0 0 0 1 1 0 1 1 A B Y 0 0 0 0 1 0 1 0 0 1 1 1
  5. 5. Symbol <ul><li>The symbol adopted for the AND function (gate) is shown below </li></ul><ul><li>American (MIL-STD-806) British (IEC 617:12) </li></ul>Logic Gates A A B B Y Y &
  6. 6. OR gate <ul><li>e.g. I turn on my headlights if it is dark OR it is raining </li></ul><ul><li>if A = dark B = raining and Y = headlights on then: </li></ul><ul><li>where the + sign represents logical OR. </li></ul>Logic Gates
  7. 7. We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are false. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 A B Y 0 0 0 0 1 1 1 0 1 1 1 1 A A B B Y Y  1
  8. 8. NOT gate <ul><li>e.g. I turn on the heating if it is NOT hot </li></ul><ul><li>if A = hot and Y = Heating on then: </li></ul><ul><li>where the bar represents logical NOT. </li></ul>Logic Gates
  9. 9. We can only have one input and the output is always the opposite sign. American (MIL-STD-806) British (IEC 617:12) Logic Gates A Y 0 1 1 0 A A Y Y 1
  10. 10. <ul><li>Using these three gates we can design any logic circuit. </li></ul><ul><li>We will define three additional gates which aid circuit design. </li></ul>Logic Gates
  11. 11. Exclusive OR EXOR gate where the  sign represents logical EXOR. Note that the normal OR includes the case where we have both inputs true. The EXOR does not include this case. For more than two inputs the gate is defined as: The output is TRUE if we have an odd number of inputs TRUE Logic Gates A B Y 0 0 0 1 1 0 1 1 A B Y 0 0 0 0 1 1 1 0 1 1 1 0
  12. 12. <ul><li>The symbol adopted for the EXOR function (gate) is shown below </li></ul><ul><li>American (MIL-STD-806) British (IEC 617:12) </li></ul>Logic Gates A B Y =1 A B Y
  13. 13. Not AND NAND gate where the dot and bar represents logical NAND. We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are true. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 1 1 1 0 A B Y & A B Y
  14. 14. Not OR NOR gate where the + sign and bar represents logical NAND. We can have more than two inputs in which case the only time we would have a 1 out is when all the inputs are false. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 1 0 0 0 A A B B Y Y  1
  15. 15. Universal Gates <ul><li>NAND and NOR gates are referred to as universal gates as the three basic gates can be constructed using either one of the two. </li></ul><ul><li>This therefore implies that all logic circuits can be constructed using either of the gates. </li></ul><ul><li>The notes show this process for NAND only but it can be shown for NOR also. </li></ul>Logic Gates
  16. 16. NOT using NANDs only The Truth Table is for a NAND gate If we tie the inputs of a NAND together then we limit the possible input combinations to two, 1 1 and 0 0. These are shown on the table now if the input is 0 the output is 1 and vice versa – a NOT gate Logic Gates A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A Y
  17. 17. AND using NANDs only <ul><li>As a NAND is simply an AND followed by a NOT gate (inverter) we can simply use a NAND followed by NOT. </li></ul>Note – more than one NAND gate to produce the desired AND gate. Logic Gates A B Y
  18. 18. OR using NANDs only This is our desired OR gate Logic Gates 0 0 0 0 1 1 1 0 1 1 1 1
  19. 19. OR using NANDs only If we now add NOT A and NOT B into our table Logic Gates 0 0 0 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 0
  20. 20. OR using NANDs only If these are now ANDed together Logic Gates 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0
  21. 21. OR using NANDs only Finally if we invert our result we see that the 3 rd and 7 th column are identical. This means that if we invert the inputs then NAND then we will end up with the OR function. Logic Gates 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1
  22. 22. OR using NANDs only Let us examine the way in which logic gates can be used to realise logic circuits: Logic Gates A B Y
  23. 23. Example <ul><li>A drill (D) is to operate if we are in automatic (A) and the system (S) is running or if we are in manual (M) and a button (B) is pressed or if an override (O) input is not operated. </li></ul><ul><li>The boolean (logic) expression for this can be written in the following way: </li></ul>This can be constructed in the following way: A S M B O D
  24. 24. <ul><li>At this point let us examine different logic integrated circuits (I.C.s) families which can be used to construct logic circuits. </li></ul>Logic Gates
  25. 25. Logic Families <ul><li>Transistor-Transistor Logic ( TTL ) is a class of digital circuits built from bipolar junction transistors (BJT), and resistors. It is called transistor-transistor logic because both the logic gating function (e.g. AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL). </li></ul>Logic Gates
  26. 26. Transistor Transistor Logic TTL <ul><li>prefix 74 e.g. 7400 Quad 2-input NAND </li></ul><ul><li>More Specifically MM74XXX00P </li></ul><ul><li>MM Manufacturers codes </li></ul><ul><li>e.g. SN Texas Instruments </li></ul><ul><li>CD Harris Semiconductors </li></ul><ul><li>DM Fairchild Semiconductors </li></ul><ul><li>M SGS-Thomson Microelectronics </li></ul><ul><li>MC Motorola </li></ul>Logic Gates
  27. 27. Transistor Transistor Logic TTL <ul><li>XXX variants </li></ul><ul><li>e.g. L Low power </li></ul><ul><li>S Schottky high speed </li></ul><ul><li>LS Low power Schottky </li></ul><ul><li>ALS Advanced low power Schottky </li></ul>Logic Gates   Voltage range Speed Power LS +5V 5% 10nS 2mW ALS +5V 5% 7nS 1mW
  28. 28. Transistor Transistor Logic TTL <ul><li>Prefix 54 not 74 is used for higher specifications (normally military) </li></ul>Logic Gates   Temperature range Voltage supply tolerance Commercial 74 families 0 - 70ºC ±5% Military 54 families -55 - +125ºC ±10%
  29. 29. Transistor Transistor Logic TTL <ul><li>Most TTL families </li></ul><ul><li>An input is recognised as 1 if the input is >2V </li></ul><ul><li>An input is recognised as 0 if the input is < 0.8V </li></ul><ul><li>Noise immunity is the difference = 1.2V </li></ul><ul><li>A low output has a maximum output of 0.2V </li></ul><ul><li>A high output has a minimum output of 3.3V </li></ul>Logic Gates
  30. 30. Available TTL Gate Packages <ul><li>Quad 2-input gates </li></ul><ul><li>7400 quad 2-input NAND </li></ul><ul><li>7403 quad 2-input NAND with open collector outputs </li></ul><ul><li>7408 quad 2-input AND </li></ul><ul><li>7409 quad 2-input AND with open collector outputs </li></ul><ul><li>7432 quad 2-input OR </li></ul><ul><li>7486 quad 2-input EX-OR </li></ul><ul><li>74132 quad 2-input NAND with Schmitt trigger inputs </li></ul><ul><li>7402 quad 2-input NOR </li></ul>Logic Gates
  31. 31. <ul><li>Triple 3-input gates </li></ul><ul><li>7410 triple 3-input NAND </li></ul><ul><li>7411 triple 3-input AND </li></ul><ul><li>7412 triple 3-input NAND with open collector outputs </li></ul><ul><li>7427 triple 3-input NOR </li></ul><ul><li>Dual 4-input gates </li></ul><ul><li>7420 dual 4-input NAND </li></ul><ul><li>7421 dual 4-input AND </li></ul><ul><li>Others </li></ul><ul><li>7430 8-input NAND gate </li></ul><ul><li>Hex NOT gates </li></ul><ul><li>7404 hex NOT </li></ul><ul><li>7405 hex NOT with open collector outputs </li></ul><ul><li>7414 hex NOT with Schmitt trigger inputs </li></ul>Logic Gates
  32. 32. Complementary Metal Oxide Semiconductor Logic CMOS <ul><li>Number sequence originally from 4000 upwards but not the same as TTL </li></ul><ul><li>Characteristics </li></ul><ul><li>Delay 50nS Power 1  W Voltage 3-18V </li></ul><ul><li>Input </li></ul><ul><li>Logic 1 is recognised above 2/3 Supply </li></ul><ul><li>Logic 0 is recognised below 1/3 Supply </li></ul><ul><li>Output </li></ul><ul><li>The minimum for logic 1 is Supply – 0.01V </li></ul><ul><li>The maximum for logic 0 0.01V </li></ul>Logic Gates
  33. 33. Available CMOS Gate Packages <ul><li>Quad 2-input gates </li></ul><ul><li>4001 quad 2-input NOR </li></ul><ul><li>4011 quad 2-input NAND </li></ul><ul><li>4070 quad 2-input EX-OR </li></ul><ul><li>4071 quad 2-input OR </li></ul><ul><li>4077 quad 2-input EX-NOR </li></ul><ul><li>4081 quad 2-input AND </li></ul><ul><li>4093 quad 2-input NAND with Schmitt trigger inputs </li></ul>Logic Gates
  34. 34. CMOS Gate Packages <ul><li>Triple 3-input gates </li></ul><ul><li>4023 triple 3-input NAND </li></ul><ul><li>4025 triple 3-input NOR </li></ul><ul><li>4073 triple 3-input AND </li></ul><ul><li>4075 triple 3-input OR </li></ul><ul><li>Dual 4-input gates </li></ul><ul><li>4002 dual 4-input NOR </li></ul><ul><li>4012 dual 4-input NAND </li></ul><ul><li>4072 dual 4-input OR </li></ul><ul><li>4082 dual 4-input AND </li></ul><ul><li>4069 hex NOT (inverting buffer) </li></ul>Logic Gates
  35. 35. Developments in TTL and CMOS <ul><li>Often there are different pin-outs in the two family types. </li></ul><ul><li>CMOS chips are available which are the same numbers due to the popularity of TTL. </li></ul><ul><li>74HC High speed CMOS operating 2V to 6V </li></ul><ul><li>74HCT High speed CMOS with TTL compatible supplies </li></ul><ul><li>74ACT Advanced CMOS with TTL compatible levels and pin-outs </li></ul><ul><li>74AC Advanced CMOS with CMOS compatible levels and TTL pin-outs </li></ul>Logic Gates
  36. 36. Logic Problem. <ul><li>Getting back to our example, we can see that we would require: </li></ul><ul><li>2 x 2-input AND 7408 (4 x 2-input AND) </li></ul><ul><li>4081 (4 x 2-input AND) </li></ul><ul><li>1 x inverter (NOT) 7404 (6 x inverter) </li></ul><ul><li>4069 (6 x inverter) </li></ul><ul><li>1 x 3-input OR Not available? </li></ul><ul><li>4075 (3 x 3-input OR) </li></ul><ul><li>This is a total of 3 chips and we end up not using 9 gates within the packages. </li></ul>Logic Gates
  37. 37. Convert the circuit to NAND only. Note. We require: 8 x 2-input NAND 2 x 7400 1 x 3-input NAND 1 x 7410 again 3 chips . Logic Gates OR AND AND NOT 1 2 3 4 5 6 7 8 9
  38. 38. <ul><li>BUT </li></ul><ul><li>By observation we can see that NANDs 2 and 3 simply invert 1’s output then invert it again. This means that they cancel each other out and can be removed. </li></ul><ul><li>This is also true for NANDs 5 and 6 and NANDs 8 and 9, leaving us with </li></ul>Logic Gates
  39. 39. <ul><li>This requires: </li></ul><ul><li>2 x 2-input NAND 1 x 7400 </li></ul><ul><li>1 x 3-input NAND 1 x 7410 </li></ul><ul><li>With a little understanding of logic gates we can reduce the requirements to only one chip by using the fact that: </li></ul>So we need: 3 x 3-input NANDs 1 x 7410 Logic Gates
  40. 40. Note. <ul><li>Conversions from AND, OR, NOT to NAND only rarely produce a less complex circuit but normally the complexity is similar. The advantage lies in the fact that NAND chips are readily available and are inexpensive due to the number sold and that any gates left over can be used in other circuits as all circuits use the same gate types. </li></ul>Logic Gates
  41. 41. Logic Circuits TTL and CMOS <ul><li>Transistor Transistor Logic (TTL) NAND Gate. </li></ul>Logic Gates R1 R2 R3 R4 Q1 Q2 Q3 Q4 D F a b c
  42. 42. <ul><li>Complementary Metal Oxide Semiconductor CMOS NOR gate </li></ul>Logic Gates Output Input A Input B Vs+ Q1 Q2 Q3 Q4
  43. 43. * dependant on frequency Logic Gates Technology Silicon gate CMOS Metal gate CMOS Std TTL Low-power Schottky TTL Schottky TTL Advanced Low – power Schottky TTL Advanced Schottky TTL Device series SN74HC 4000 SN74 SN74LS SN74AS SN74ALS SN74AS Power diss per gate (mW) Static At 100kHz 0.0000025 0.17 0.001 0.1 10 10 2 2 19 19 1 1 8.5 8.5 Progation delay time (nS) 8 105 10 10 3 4 1.5 Maximun clock (MHz) 40 12 35 40 125 70 200 Maximum output drive (mA) 4 1.6 16 8 20 8 20 Fan out LS loads Same series 10 * 4 * 40 10 20 20 50 10 20 80 50 40 Maximum input current(mA)  0.0001 -0.0001 -1.6 -0.4 -2.0 -0.1 -0.5
  44. 44. This resource was created by the University of Wales Newport and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © 2009 University of Wales Newport This work is licensed under a Creative Commons Attribution 2.0 License . The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence.  All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher. The name and logo of University of Wales Newport is a trade mark and all rights in it are reserved. The name and logo should not be reproduced without the express authorisation of the University. Logic Gates

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