Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy.

Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our Privacy Policy and User Agreement for details.

Like this presentation? Why not share!

- Lecture 8 bjt_1 by Napex Terra 21407 views
- (Latest) topic 4 bipolar_junction_t... by Way Chin 10742 views
- 3.bipolar junction transistor (bjt) by firozamin 28672 views
- Transistors ppt by behin by Behin anben 25061 views
- Bipolar Transistor Operation by S_Degnan 8708 views
- Transistors by vicdiola 10151 views

No Downloads

Total views

4,795

On SlideShare

0

From Embeds

0

Number of Embeds

23

Shares

0

Downloads

288

Comments

0

Likes

3

No embeds

No notes for slide

- 1. Lecture : TRANSISTOR BIAS CIRCUITSCode: Semester II Apr 5, 2012 1EEE2213 2010/2011
- 2. THE DC OPERATING POINT A transistor must be properly biased with a dc voltage in order to operate as a linear amplifier. A dc operating point must be set so that signal variations at the input terminal are implified & accurately reproduced at the output terminal. Note that when we bias a transistor, the dc voltage and current values will be established. Thus, at the dc operating point, IC & VCE have specified values. Q-point: the dc operating point (quiescent point)Apr 5, 2012 2
- 3. DC Bias Bias establishes the dc operating point (Q-point) for proper linear operation of an amplifier. If an amplifier is not biased with correct dc voltages on the input and output, it can go into saturation or cutoff when an input signal is applied.Apr 5, 2012 3
- 4. FIGURE 5–1 Examples of linear and nonlinear operation of an invertingamplifier (the triangle symbol).Apr 5, 2012 4
- 5. Figure 5-1 shows the effects of proper & improper dc biasing of an inverting amplifier. Part (a): Linear operation The output signal is an amplified replica of the input signal except that it is inverted, which means that it is 180° out of phase with the input. The output signal swings equally above & below the dc bias level of the output, V DC(out).Apr 5, 2012 5
- 6. Part (b & c): Nonlinear operation Improper biasing can cause distortion in the output signal. Part (b): shows the limiting of the positive portion of the output voltage as a result of a Q-point (dc operating point) being too close to cutoff. Part (c): shows the limiting of the negative portion of the output voltage as a result of a dc operating point being too close to saturation.Apr 5, 2012 6
- 7. Graphical Analysis The transistor in Figure is biased with VCC & VBB to obtain certain values of IB, IC, IE, and VCE. The collector characteristic curves for this particular transistor are shown in Figure.Apr 5, 2012 7
- 8. Figure 5-3 Illustration of Q-point adjustment.Apr 5, 2012 8
- 9. Refer to Figure 5-3;Assign 3 values to IB & observe what happens to IC & VCE.First, VBB is adjusted to produce an IB of 200µA.Since IC=βDCIB, the collector current is 20 mA, & VCE; VCE=VCC – ICRC = 10 V – (20 mA)(220Ω) = 10 V – 4.4 V = 5.6 V (this Q-point is shown in (a) as Q1.)Next, in (b);VBB is increased to produce an IB of 300µA & an IC of 30 mA. VCE=VCC – ICRC = 10 V – (30 mA)(220Ω) = 10 V – 6.6 V = 3.4 V (this Q-point is shown in (a) as Q2.)Next, in (c);VBB is increased to produce an IB of 400µA & an IC of 40 mA. VCE=VCC – ICRC = 10 V – (40 mA)(220Ω) = 10 V – 8.8 V = 1.2 VApr 5, 2012 9
- 10. DC Load Line The dc operation of a transistor circuit can be described graphically using a dc load line. DC Load Line: a straight line drawn on the characteristic curves from the saturation value where IC=IC(sat) on the y-axis to the cutoff value where VCE = VCC on the x-axis.Apr 5, 2012 10
- 11. Load line is determined by the external circuit (VCC & RC), not determined by the transistor itself, which is described by the characteristic curve.Apr 5, 2012 11
- 12. Refer to Figure 5-3,the equation for IC is;This is the equation of a straight line with a slope of -1/RC, an x intercept ofVCE=VCC, & a y intercept of VCC/RC, which is IC(sat).The point at which the load line intersects a characteristic curve represents theQ-point for that particular value of IB.Figure 5-4(b): shows the Q-point on the load line for each value of IB in Figure5-3. 2012Apr 5, 12
- 13. Linear Operation The region along the load line including all points between saturation & cutoff is generally known as the linear region of the transistor’s operation. As long as the transistor is operated in this region, the output voltage is ideally a linear reproduction of the input.Apr 5, 2012 13
- 14. Figure shows an example of the linear operation of a transistor.AC quantities are indicated by lowercase italic subscripts.Assume a sinusoidal voltage, Vin, is superimposed on VBB, causing the basecurrent to vary sinusoidally 100 µA above and below its Q-point value of 300µA.This will causes the collector current to vary 10 mA above and below its Q-pointvalue of 30 mA.From 2012 variation in collector current, the collector-to-emitter voltage varies Apr 5, the 14
- 15. Point A on the load line: corresponds to the positive peak of the sinusoidal inputvoltage.Point B on the load line: corresponds to the negative peak.Point Q: corresponds to the zero value of the sine wave.VCEQ, ICQ, & IBQ are dc Q-point values with no input sinusoidal voltage applied. Apr 5, 2012 15
- 16. Waveform Distortion Under certain input signal conditions, the location of the Q-point on the load line can cause one peak of the VCE waveform to be limited or clipped (Figure (a) & (b).Apr 5, 2012 16
- 17. In each case, the input signal is too large for the Q-point location & is driving the transistor into cutoff or saturation during a portion of the input cycle. When both peaks are limited as in (c), the transistor is being driven into both saturation and cutoff by an excessively large input signal. When only the positive peak is limited, the transistor is being driven into cutoff but not saturation. When only the negative peak is limited, the transistor is being driven into saturation but not cutoff.Apr 5, 2012 17
- 18. Example 5-1Apr 5, 2012 18
- 19. Lecture 9-2: TRANSISTOR BIAS CIRCUITSCode: Semester II Apr 5, 2012 19EEE2213 2010/2011
- 20. VOLTAGE-DIVIDER BIAS A method of biasing a transistor for linear operation using a single-source resistive voltage divider. Earlier, a separate dc source, VBB, was used to bias the base-emitter junction because it could be varied independently of VCC, & it helped to illustrate transistor operation. More practical bias method: use VCC as the single bias source (refer next Figure).Apr 5, 2012 20
- 21. Apr 5, 2012 21
- 22. A dc bias voltage at the base of the transistor can be developed by aresistive voltage divider that consists of R1 & R2.VCC: the dc collector supply voltage2 current paths are between point A & ground;(2)through R2, and(3)through the base-emitter junction of the transistor & REGenerally, voltage-divider bias circuits are designed so that thebase current is much smaller than the current (I2) through R2.For this case, the voltage-divider circuit is very straightforward toanalyze because the loading effect of the base current can beignored.Stiff voltage divider: A voltage divider in which the base currentis small compared to the current in R2 (the base voltage is relatively Apr 5, 2012 22independent of different transistors & temperature effects).
- 23. To analyze a voltage-divider circuit in which IB is smallcompared to R2, first calculate the voltage on the base;R1 and R2 are selected to establish VB. If the divider is stiff,IB is small compared to I2. Then, +VCC R2 +15 V VB ≈ VCC R1 + R2 R1 +VCCRC 27 kΩ 1.2 kΩ Determine the base voltage for the βDC = 200 R1 RC circuit. IB R2 RE 12 kΩ 680 Ω I2 R2 VB = VCC R1 + R2 R2 RE 12 kΩ = ( +15 V ) = 4.62 V 27 kΩ + 12 kΩ
- 24. • Once we have the base voltage, we can find the voltages & currents in the circuit;• and• Then,• From the VC & VE, we can determine VCE;Apr 5, 2012 24
- 25. What is the emitter voltage, VE, and current, IE? +VCC +15 VVE is one diode drop less than VB: R1 RC 27 kΩ 1.2 kΩVE = 4.62 V – 0.7 V = 3.92 V 4.62 V βDC = 200Applying Ohm’s law: 3.92 V R2 RE 12 kΩ 680 Ω VE 3.92 VIE = = = 5.76 mA RE 680 Ω
- 26. Example 5-2Apr 5, 2012 26
- 27. Ideally, a voltage-divider circuit is stiff; where transistor doesnot appear as a significant load.To determine if the divider is stiff or not, then need to examinethe dc input resistance looking in at the base.Apr 5, 2012 27
- 28. Loading Effects of Voltage-Divider Bias (1) DC Input Resistance at the Transistor Base (2) Stability of Voltage- Divider Bias (3) Voltage-Divider Biased PNP Transistor Apr 5, 2012 28
- 29. DC Input Resistance at the Transistor Base The dc input resistance of the transistor is proportional to βDC, thus it will change for different transistors. When a transistor is operating in its linear region, the emitter current is βDC IB. When the emitter resistor is viewed from the base circuit, the resistor appears to be larger than its actual value by a factor of is βDC because of the current gain in the transistor. Thus, β DCVB RIN (BASE ) = IE This is the effective load on the voltage divider illustrated in earlier Figure.Apr 5, 2012 29
- 30. We can estimate the loading effect by comparing RIN(BASE) to the resistor R2 in the voltage divider. As long as RIN(BASE) is at least 10x larger than R2, the loading effect will be 10% or less & the voltage divider is stiff. If RIN(BASE) is less than 10x R2, it should be combined in parallel with R2.Apr 5, 2012 30
- 31. Example 5-3Apr 5, 2012 31
- 32. Stability of Voltage-Divider Bias Thevenin’s theorem is applied when analyze a voltage-divider biased transistor circuit for base current loading effects. 1st, get an equivalent base-emitter circuit for this circuit using Thevenin’s theorem.Apr 5, 2012 32
- 33. Looking out from the base terminal, the bias circuit can beredrawn as shown in this figure. Apply Thevenin’s theorem to thecircuit left of point A, with VCC replacedby a short to ground & the transistordisconnected from the circuit. The voltage at point A with respect toground is, and the resistance is, Apr 5, 2012 33
- 34. The Thevenin equivalent of the bias circuit, connected to thetransistor base, is as shown in the grey box in the figure. Applying Kirchhoff’s voltage lawaround the equivalent base-emitter loopgives, Substituting, using Ohm’s law, &solving for VTH, Substituting IE / βDC for IB, Apr 5, 2012 34
- 35. Solving for IE, If RTH / βDC is small compared to RE, theresult is the same as for unloaded voltagedivider. Reason of why a voltage-divider bias iswidely used; Reasonably good bias stability isachieved with a single supply voltage. Apr 5, 2012 35
- 36. The unloaded voltage divider approximation for VBgives reasonable results. A more exact solution is toThevenize the input circuit. + VCC +VCC +15 V +15 V VTH = VB(no load) RC R1 RC = 4.62 V 1.2 kΩ 27 kΩ 1.2 kΩ RTH = R1||R2 = +V TH 4.62 V + R TH – + βDC = 200 βDC = 200 IB VBE – = 8.31 kΩ 8.31 kΩ + R2 RE RE The Thevenin IE – 680 Ω 12 kΩ 680 Ω input circuit can be drawn
- 37. Now write KVL around the base emitter circuit andsolve for IE. VTH = I B RTH + VBE + I E RE + VCC +15 V VTH − VBE IE = R RE + TH RC β DC 1.2 kΩ Substituting and solving, +V TH R TH + – + 4.62 V − 0.7 V 4.62 V βDC = 200 IE = = 5.43 mA IB VBE – 680 Ω + 8.31 kΩ 8.31 kΩ 200 + RE IEand – 680 ΩVE = IERE = (5.43 mA)(0.68 kΩ)= 3.69 V
- 38. Voltage-Divider Biased PNP Transistor pnp transistor requires bias polarities opposite to the npn. This can be accomplished by using a negative collector supplyvoltage: (a), or with a positive emitter supply voltage (b). 3rdfigure is same as (b), only that it is drawn upside down. Apr 5, 2012 38
- 39. Analysis procedure is the same as for an npn transistor circuit. For a stiff voltage divider (ignoring loadingeffects), By Ohm’s law, Thus, Apr 5, 2012 39
- 40. Determine IE for the pnp circuit. Assume a stiff voltage divider (no loading effect). +VEE +15 V R1 VB = VEE R2 RE R1 + R2 12 kΩ 680 Ω 27 kΩ 10.4 V 11.1 V = ( +15.0 V ) = 10.4 V 27 kΩ + 12 kΩ VE = VB + VBE = 10.4 V + 0.7 V = 11.1 V R1 RC 27 kΩ 1.2 kΩ VEE − VE 15.0 V − 11.1 VIE = = = 5.74 RE 680 Ω mA
- 41. Example 5-4 & 5-5Apr 5, 2012 41
- 42. EMITTER BIAS Provides excellent bias stability in spite of changes in β or temperature. Use both a positive & a negative supply voltage. In an npn circuit, the small base current causes the base voltage to be slightly below ground. The emitter voltage is one diode drop less than this.Apr 5, 2012 42
- 43. The combination of this small drop across RB & VBE forces the emitter to be at approximately -1 V. Thus, emitter current is,Apr 5, 2012 43
- 44. Applying the approximation that to calculate the collector voltage, thusApr 5, 2012 44
- 45. Apr 5, 2012 45
- 46. Example 5-6Apr 5, 2012 46
- 47. • Approximation that & the neglect of βDC may not be accurate enough for design work or detailed analysis.• Kirchhoff’s voltage law (KVL) can be applied to develop a more detailed formula for IE.• In (a): KVL applied around the base-emitter circuit• In (b): (a) is redrawn for analysis• Thus, • Substitute & transposing VEE,• Using Ohm’s law,Apr 5, 2012 47
- 48. • Thus,• Voltages with respect to ground are indicated by a single subscript.• Thus, the emitter voltage with respect to the ground is,• The base voltage with respect to ground is,• The collector with respect to the ground is,Apr 5, 2012 48
- 49. Example 5-7Apr 5, 2012 49
- 50. BASE BIAS This method of biasing is common in switching circuits. Analysis of this circuit for the linear region shows that it isdirectly dependent on βDC. Starts with KVL around the base circuit, Substitutes IBRB for VRB,Thus,Apr 5, 2012 50
- 51. When KVL is applied around the collector circuit, we get, Thus, Substitute IC = βDCIB, we get,Apr 5, 2012 51
- 52. Base bias is used in switching circuits because ofits simplicity, but not widely used in linearapplications because the Q-point is β dependent.Base current is derived from the collectorsupply through a large base resistor. +VCC +VCC +15 V What is IB? RC 1.8 kΩ RB 560 kΩ VCC − 0.7 V 15 V − 0.7 V IB = = = 25.5 µA RB 560 kΩ
- 53. Q-Point Stability of Base Bias Equation shows that IC is dependent on βDC. Thus, a variation in βDC causesIC and, as a result, VCE to change, thus changing the Q-point of thetransistor. Therefore, the base bias circuit is extremely beta-dependent & unpredictable. βDC varies with temperature & collector current. There is a large spread of βDC values from one transistor toanother of the same type due to manufacturing variations.Apr 5, 2012 53 Therefore, base bias is rarely used in linear circuits.
- 54. Example 5-8Apr 5, 2012 54
- 55. EMITTER-FEEDBACK BIAS If an emitter resistor is added to the base-circuit, we get anemitter-feedback bias. Help make base bias more predictable withnegative feedback, which negates anyattempted change in collector current with anopposing change in base voltage. If the collector current tries to increase, theemitter voltage increases, causing an increase inbase voltage due to VB = VE + VBE This increase in base voltage reduces thevoltage across RB, thus reducing the basecurrent & keeping the collector current fromincreasing.Apr 5, 2012 55
- 56. The same scenario happens if the collectorcurrent tries to decrease. This circuit is better for linear circuits thanbase bias, but still dependent on βDC & is notpredictable as voltage-divider bias. To calculate IE, write KVL around the basecircuit.Substitute IE/βDC for IB, can see that IE is stilldependent on βDC.Apr 5, 2012 56
- 57. Example 5-9Apr 5, 2012 57
- 58. COLLECTOR-FEEDBACK BIAS The base resistor RB is connected to the collector rather than toVCC. The collector voltage provides the bias for the base-emitter junction. The negative feedback creates an “offsetting” effectthat tends to keep the Q-point stable. If IC tries to increase, it drops more voltage across RC,and thus causing VC to decrease. When VC decreases, there is a decrease in voltageacross RB, which deecreases IB. The decrease in IB produces less IC which, in turn,drops less voltage across RC & thus offsets the decreasein VC.Apr 5, 2012 58
- 59. By Ohm’s law, Assume that IC >> IB, thus the collectorvoltage, Also, Thus,Apr 5, 2012 59
- 60. Thus, Since the emitter is ground, VCE = VC, thenApr 5, 2012 60
- 61. Q-Point Stability Over Temperature Equation shows that IC is dependent to some extent on βDC and VBE . The dependency can be minimized by making RC >> RB/βDC &VCE >>VBE. The collector-feedback bias is essentially eliminates the βDC &VBE dependency even if the stated conditions are met. βDC varies directly with temperature, & VBE varies inversely withtemperature. As the temperature goes up in a collector-feedback 61 Apr 5, 2012 β DC
- 62. The increase in βDC acts to increase IC. The decrease inVBE acts to increase IB which, in turn also acts to increaseIC. As IC tries to increase, the voltage drop across RC alsotries to increase. This tends to reduce the collector voltage& therefore the voltage across RB, thus reducing IB &offsetting the attempted increase in IC & the attempteddecrease in VC. The result is that the collector-feedback circuitmaintains a relatively stable Q-point. The reverse actionoccurs when the temperature decreases.Apr 5, 2012 βDC 62
- 63. Compare IC for the case when β = 100 with the case when β = 300. +VCCWhen β = 100, + 15 V VCC − VBE 15 V − 0.7 VIC = = = 2.80 mA RC RB 1.8 kΩ + 330 kΩ RB RC + 100 1.8 kΩ β DC 330 kΩWhen β = 300, VCC − VBE 15 V − 0.7 VIC = = = 4.93 mA RB 1.8 kΩ + 330 kΩ RC + 300 β DC
- 64. Example 5-10Apr 5, 2012 64

No public clipboards found for this slide

×
### Save the most important slides with Clipping

Clipping is a handy way to collect and organize the most important slides from a presentation. You can keep your great finds in clipboards organized around topics.

Be the first to comment