Multiple Board Si Analysis And Emi Analysis

Multiple Board SI Analysis and EMI Analysis using Spectraquest for successfully reducing the EMI of the medical product Ravindra Munvar Mohit Jain Oct 16, 2008

Agenda

Terms and Terminologies - Definition

Our Objective

How we did SI simulations?

Block Diagram

Pre-layout SI Analysis

Post-layout SI Analysis

EMI Analysis

Conclusion

Q&A

Terms and terminologies - Definition

Overshoot

Propagation Delay

Noise Margin

Cross Talk

SSN (Simultaneous Switching Noise)

Objective

To meet CISPR 11 and IEC 60601-1-2 EMI/EMC regulations for medical product

For Class B product its 30 dB (at 10m)

How we did SI simulation?

Only few signals of the similar signal groups were simulated for the pre-layout reflection analysis

Batch simulations for the reflection, cross talk and SSN were performed at the post layout stage along with the EMI Analysis

Single iteration of Post layout Analysis and consequent Layout update was followed.

Block Diagram

Address and data signals are connected to the FPGA on the same board

Address and data signals are connected to SRAM and ROM on the other board through board to board connector

The frequency of operation of the signals is 12MHz

Pre-Layout SI - Setting Simulation Preferences

Pre-layout SI : Topology for Data Line MCU/ROM

Pre-layout SI : Simulation Graph for Data Line MCU/ROM MCU as driver and ROM as receiver OBSERVATIONS: Overshoots are high

Pre-layout SI : Simulation Graph for Data Line MCU/ROM ROM as driver and MCU as receiver

Pre-layout SI : Updated Topology for Data Line MCU/ROM

Corrective Action:

Added 47 ohms series termination resistor

Pre-layout SI: New Simulation Graph for Data Line MCU/ROM MCU as driver and ROM as receiver

Pre-layout SI: New Simulation Graph for Data Line MCU/ROM ROM as driver and MCU as receiver

Pre-layout SI : Topology for Data Line MCU/RAM

Pre-layout SI : Simulation Graph for Data Line MCU/RAM MCU as driver and RAM as receiver OBSERVATIONS: Ringing is more

Pre-layout SI : Simulation Graph for Data Line MCU/RAM RAM as driver and MCU as receiver

Pre-layout SI : Updated Topology for Data Line MCU/RAM

Corrective Action: Added 47 ohms series termination resistor

Pre-layout SI: New Simulation Graph for Data Line MCU/RAM MCU as driver and RAM as receiver

Pre-layout SI: New Simulation Graph for Data Line MCU/RAM RAM as driver and MCU as receiver

Post-layout SI : Topology for RW Signal MCU as driver  ROM and NOT Gate as receiver

Post-layout SI : Simulation Graph for RW Signal OBSERVATIONS: Waveform is not monotonic MCU as driver  ROM and NOT Gate as receiver

Post-layout SI : Updated Topology for RW Signal

Corrective Action: Added 47 ohms series termination resistor

Post-layout SI : New Simulation Graph for RW Signal MCU as driver  ROM and NOT Gate as receiver

Cross Talk Analysis 0ns Pulse Step Offset 0.5 Pulse Duty Cycle 12MHz Pulse Clock Frequency 100mil Minimum Coupled Length 0.1pF Min Neighbor Capacitance 30mil Geometry Window Value Variable Simulation Preferences

Cross Talk Analysis – Results 13.53 15.98 14.49 19.48 U14 18 DQ<6> U13 J1 DQ<7> 14.59 16.16 15.11 19.9 U14 16 DQ<4> U13 J1 DQ<7> 2.43 19.89 2.47 31.89 U14 18 DQ<6> U14 19 DQ<7> 3.325 21.93 3.12 32.28 U14 16 DQ<4> U14 19 DQ<7> 114.4 152.1 104.1 142.3 U13 J2 DQ<6> U13 J1 DQ<7> 118.4 155.6 101.8 147.5 U13 K2 DQ<4> U13 J1 DQ<7> 244.6 266.3 200.6 267.2 U13 J2 DQ<6> U14 19 DQ<7> 249.9 276 201.5 277.7 U13 K2 DQ<4> U14 19 DQ<7> LSEvenXtalk (mV) LSOddXtalk (mV) HSEvenXtalk (mV) HSOddXtalk (mV) Aggr Drvr Aggr XNet Victim Drvr Victim XNet

SSN Analysis – Simulation Preferences 0ns Pulse Step Offset 0.5 Pulse Duty Cycle 12MHz Pulse Clock Frequency 0GHz Cutoff Frequency 0.1pF Min Neighbor Capacitance 30mil Geometry Window Simulation Preferences – 12 MHz

SSN Analysis - Results 110.5 gndbus 461 pwrbus U16 104 A<18> 110.5 gndbus 461 pwrbus U16 105 A<17> 110.5 gndbus 461 pwrbus U16 106 A<16> 110.5 gndbus 461 pwrbus U16 110 A<15> 110.5 gndbus 461 pwrbus U16 111 A<14> 110.5 gndbus 461 pwrbus U16 112 A<13> 110.5 gndbus 461 pwrbus U16 113 A<12> 110.5 gndbus 461 pwrbus U16 115 A<11> 110.5 gndbus 461 pwrbus U16 116 A<10> SSNFall (in mV) GroundBus SSNRise (in mV) PowerBus Drvr Net

EMI Analysis

EMI Analysis – Topology for SQW Signal FPGA as driver  MCU as receiver

EMI Analysis – New Topology for SQW signal FPGA as driver  MCU as receiver Added termination resistor of 33 ohms

EMI Analysis – Simulation Graph for SQW signal

Conclusion