Design of an ultra-wideband integrated MAC and digital PHY chip Debashis Goswami and Janardhan Eerappa April 2009

Agenda INTRODUCTION DESIGN COMPLEXITY DESIGN VALIDATION TOP LEVEL DESIGN CONSIDERATIONS Design for testability challenges Physical design challenges

INTRODUCTION

DESIGN COMPLEXITY

DESIGN VALIDATION

TOP LEVEL DESIGN CONSIDERATIONS

Design for testability challenges

Physical design challenges

Introduction Ultra-wideband (UWB) is an emerging short-range wireless technology – high bit rate of 480Mbps Bandwidth of more than 500MHz or even a few GHz in the radio frequency spectrum. Compared to that of conventional wireless technologies UWB’s bandwidth is extremely large. Bluetooth, for one, has about 1MHz bandwidth UWB’s high bit rate coupled with full CMOS realization possibility makes it an excellent choice for low-power wireless personal area networks (WPAN). Two applications based on UWB technology show great potential, viz, Wireless USB, and High-speed Bluetooth. The Wireless USB promises low cost and user-friendly wireless experience with the same speed as high speed wired USB. The High-speed Bluetooth would benefit from the almost universal use of Bluetooth technology in mobile and headset applications, and would enable Bluetooth to transfer high speed audio/video. Towards the goal of achieving an all-CMOS UWB single chip, an integrated chip is planned comprising of the UWB Medium Access Control (MAC) layer and the digital Physical (PHY) layer The chip, has been successfully timing closed using 90nm low power CMOS technology.

Ultra-wideband (UWB) is an emerging short-range wireless technology –

high bit rate of 480Mbps

Bandwidth of more than 500MHz or even a few GHz in the radio frequency spectrum.

Compared to that of conventional wireless technologies

UWB’s bandwidth is extremely large.

Bluetooth, for one, has about 1MHz bandwidth

UWB’s high bit rate coupled with full CMOS realization possibility makes it an excellent choice for low-power wireless personal area networks (WPAN).

Two applications based on UWB technology show great potential, viz, Wireless USB, and High-speed Bluetooth.

The Wireless USB promises low cost and user-friendly wireless experience with the same speed as high speed wired USB.

The High-speed Bluetooth would benefit from the almost universal use of Bluetooth technology in mobile and headset applications, and would enable Bluetooth to transfer high speed audio/video.

Towards the goal of achieving an all-CMOS UWB single chip, an integrated chip is planned comprising of the UWB Medium Access Control (MAC) layer and the digital Physical (PHY) layer

DESIGN COMPLEXITY The UWB MAC and PHY operate with a maximum bit rate of 480Mbps, Puts a number of constraints on the architecture Problem with translating into an ASIC. The major functionalities of the MAC have been implemented in hardware to ensure that software related interactions do not slow it down. The MAC was architected to ensure that all buffers have optimized sizes to keep the ASIC footprint low, and pipelined architecture had been employed to ensure low latency, fast protocol response. A complete high level software model was developed to optimize the data path width of various blocks inside the PHY layer, thereby optimizing the performance while keeping the gate count low. Also, parallel architecture had been employed to ensure smooth timing closure during front-end synthesis.

The UWB MAC and PHY operate with a maximum bit rate of 480Mbps,

Puts a number of constraints on the architecture

Problem with translating into an ASIC.

The major functionalities of the MAC have been implemented in hardware to ensure that software related interactions do not slow it down.

The MAC was architected to ensure that all buffers have optimized sizes to keep the ASIC footprint low, and pipelined architecture had been employed to ensure low latency, fast protocol response.

A complete high level software model was developed to optimize the data path width of various blocks inside the PHY layer, thereby optimizing the performance while keeping the gate count low.

Also, parallel architecture had been employed to ensure smooth timing closure during front-end synthesis.

DESIGN VALIDATION Validation of the UWB MAC and PHY is done using an FPGA-based platform The platform has a host of debug features and numerous peripherals including s-video and audio connectivity. The UWB protocol over the air is validated using a protocol analyzer. In addition, a unique software-based debug feature had been internally developed to step through complex sequences of events for easy debugging.

Validation of the UWB MAC and PHY is done using an FPGA-based platform

The platform has a host of debug features and numerous peripherals including s-video and audio connectivity.

The UWB protocol over the air is validated using a protocol analyzer.

In addition, a unique software-based debug feature had been internally developed to step through complex sequences of events for easy debugging.

TOP LEVEL DESIGN CONSIDERATIONS The design is targeted to 90nm low power ASIC standard cell library. The chip has approximately 700K gates and I/O pin count of 391. Compact footprint coupled with low power implementation was the major consideration for this design. Design for testability challenges Given the smaller die-size and lower pin count of the design, the challenge was to implement DFT logic within the given area and pin count, and not compromising on the test coverage. All logic, memories and IOs in the design were covered for testability with minimal vectors and low test time. At-speed testing for logic and memories was covered for all derived clocks and clock frequencies in the design to meet the quality requirements. The DFT architecture employed ensured low power consumption and smooth timing closure of the design. Physical design challenges The major challenge was to implement the design in a smaller die-size to reduce cost. The design had multiple derived clocks operating at different frequencies and was quite difficult to close timing smoothly with DFT logic. The design with DFT logic was taken through synthesis for timing optimization, after which the design was timing closed smoothly in the Back-end. Power analysis and Dynamic simulations were run in all modes to ensure the design was meeting the low power requirements.

The design is targeted to 90nm low power ASIC standard cell library. The chip has approximately 700K gates and I/O pin count of 391. Compact footprint coupled with low power implementation was the major consideration for this design.

Design for testability challenges

Given the smaller die-size and lower pin count of the design, the challenge was to implement DFT logic within the given area and pin count, and not compromising on the test coverage.

All logic, memories and IOs in the design were covered for testability with minimal vectors and low test time.

At-speed testing for logic and memories was covered for all derived clocks and clock frequencies in the design to meet the quality requirements.

The DFT architecture employed ensured low power consumption and smooth timing closure of the design.

Physical design challenges

The major challenge was to implement the design in a smaller die-size to reduce cost.

The design had multiple derived clocks operating at different frequencies and was quite difficult to close timing smoothly with DFT logic.

The design with DFT logic was taken through synthesis for timing optimization, after which the design was timing closed smoothly in the Back-end.

Power analysis and Dynamic simulations were run in all modes to ensure the design was meeting the low power requirements.

SUMMARY An integrated UWB MAC and digital PHY chip was designed and targeted for 90nm low power technology. The chip would be used for board level validation with external analog and RF components and for development of UWB based applications. An FPGA-based prototype board had also been developed to validate the functionality at the FPGA level.

An integrated UWB MAC and digital PHY chip was designed and targeted for 90nm low power technology.

The chip would be used for board level validation with external analog and RF components and for development of UWB based applications.

An FPGA-based prototype board had also been developed to validate the functionality at the FPGA level.