UltraBGA Multi-Tier Design Guides Rev D 040102.PDF

Substrate Technologies Inc.
Ultra BGA®®
Multi-Tier Design Guidelines
Substrate Technologies, Inc. Document Number: DES 04001
Dallas, TX: (972) 484-3800 Document Revision: D
Campbell, CA: (408) 879-7310 Page 1 of 22
UUNN CCOONNTTRROOLLEEDD
DDOOCCUUMMEENNTT
D O C U M E N T R E V I S I O N S
Date Sections Description of Change Initials Rev. Letter
8/31 All Initial Release JH A
2/02 All Revsed DRAFT RS B
03/27/02 All Design rules update RS C
04/01/02 1.2.3,4, &
2.3.2
Changed bond finger flat size, added new detail drawing
and copper thickness on plane layer
RS D
Authorizing Functions
Document ID: DES 04001-M
Abram Castro ______________________________________
CTO
Michael Knight ______________________________________
President
Rick Shearer ______________________________________
Director, Customer Engineering
Aaron Castro ______________________________________
Ultra Product Director
Gary Roper _______________________________________
Director Technical Service
Title: Ultra BGA®
Multi-Tier
Design Guidelines
Caution: Unless accompanied by RED “CONTROLLED COPY” printed in the
frame at right, copies of this document may be obsolete. The latest version is
available on the network.
UNCONTROLLED
COPY

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Contents
Section 1 Cross section view
1.1 Current product offerings
1.2 Typical material stack up
1.3 Mechanical options
Section 2 Formed features
2.1 Etched features and vias
2.1.1 Assembly indicators
2.1.2 A1 corner indicator
2.1.3 Ball pad specifications
2.1.4 Power/ Ground capability
2.1.5 Multi tier bond ring configuration
2.1.6 Metal areas
2.2 Soldermask
2.2.1 Soldermask and dielectric
2.2.2 Soldermask alignment
2.2.3 Soldermask defined and non-defined rings
2.3 Bond fingers
2.3.1 Bond finger layout
2.3.2 Bond finger parameters
2.3.3 Bond finger arrays
2.3.3.1 Single row wire bond finger diagram
– External routing
2.3.3.2 Staggered bond finger diagram
– External routing only
2.3.3.3 Staggered bond finger diagram
– Inner layer routing
Section 3 Material characteristics
3.1 Photo imageable dielectric (STI proprietary)
3.2 Substrate/ heatsink ( Copper Alloy )
3.3 Soldermask (Taiyo PSR – 4000 AUS)
Section 4 Bussing network

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Section 1: Cross section view
1.1 Current Ultra BGA III Multi-Tier product offerings:
1.2 Typical material stack-up:
Note (1) 0.787 mm metal core is optimized for sub
1.00 mm substrate profile. Consult STI for alternate
metal core options.
Note (2) Measured from top of metal to base of
subsequent metal layer.
Note (3) Consult STI for details on Copper plating
thickness for Multi-tier bondshelf structures.
Plane layer copper under dielectric= .050 mm and
copper under gold plating at rings = .015 mm
Note (4) Cavity depth can be changed as needed .
Material Typical Tolerance
A Copper Heatsink Thickness (1) 0.787 mm +/- 0.024 mm
B Photo Dielectric - Cured thickness(2) 0.032 mm +/-0.008 mm
C Plated Circuit Layer – Signal layers. 0.015 mm +/-0.005 mm
D Plated Plane Layer – Internal (3) 0.050 mm +/-0.005 mm
E Soldermask Layer (over circuits) 0.023 mm +/-0.008 mm
F Cavity Depth (Top of SM) (4) 0.570 mm +/-0.050 mm
G
R
Three dielectric layer (Ultra III)
Total Substrate Thickness
Radius at Base of Cavity
0.957 mm
0.15 mm
+/-0.050 mm
+0.00/-0.15 mm

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1.2.6 Detail of Outer Edge
Detail Dielectric 1 recess
from outside edge
Dielectric 2 recess
From outside edge
Dielectric 3 recess
from outside edge
A 0.250 mm 0. 250 mm 0. 250 mm
1.3 Mechanical options
Feature Typical Value Tolerance
Cavity minimum depth Set by die thickness +/- 0.050 mm
Cavity maximum depth
Copper heatsink + (0.057 mm x # circuit
layers) - 0.280 mm die paddle thickness
+/- 0.050 mm
Cavity finish – Roughness
Ra (average)
Rmax (maximum)
1 microns
8 microns
Circuits
Dielectric Recess 1,2,3
Dielectric
Heatsink
Dielectric
Dielectric
Soldermask
Detail A

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Note (1) Die to cavity wall dimension determined by assembly process.
STI suggested gap 0.50mm
Feature Minimum Maximum Tolerance
Substrate outside dimension (X,Y) 17 X 17 mm N/A +/- .100 mm
Cavity Dimensions (X,Y) Set by die size N/A +/- .050 mm
Cavity Corner Radius * 0.79 mm N/A N/A
*Note: A 0.39 mm can be achieved for premium designs.

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Section 2: Formed features
2.1 Etched features and vias
Note (1) Connection between circuit and/or plane layers is accomplished by using micro-vias in pad and “dog
bones” when a connection is needed between non-sequential layers.
Note (2) Note removed
Note (3) Via diameters on any one layer must all be the same.
Note (4) Via in Pad to be minimum diameter per design requirement.
Note (5) Stacked Vias are not allowed
Substrate Feature Standard Advanced Tolerance
A Conductor Width 0.050 mm 0.050 mm
+0.005 mm/
-0.010 mm
B Conductor Spacing 0.050 mm 0.045 mm
+0.010 mm/
-0.005 mm
C Photo Via Diameter (3)(4) 0.100 mm 0.075 mm +/- 0.010 mm
D Photo Via Pad Diameter 0.250 mm 0.200 mm
+0.005mm/
-0.010 mm
E
Dog bone Capture Pad
(1)
0.280 mm 0.230 mm
+0.005 mm/
-0.010 mm
F Dog Bone Line Width 0.100 mm 0.075 mm
+0.005 mm/
-0.010 mm
G
Dog Bone Clearance to
Adjacent Plane 0.100 mm 0.075 mm
+0.010 mm/
-0.005 mm

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Cavity Features Guideline
Note (1) Die to cavity wall dimension determined by assembly process.
STI suggested gap 0.50mm
Description Value
Distance from Die to Cavity
1.00 mm (preferred)
0.50 mm (minimum)
Ground Ring from cavity 1.00 mm
Width of Ground Ring 0.350 mm (typ)
Width of Power Ring 0.350 mm (typ)
Gap Between Ring (No soldermask) 0.10 mm (min)

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2.1.1 Assembly indicators
Wire bond fiducials can be etched into any pattern to meet a given customer‘s character recognition
specifications. Fiducials in STI open tool Ultra BGA®
parts conform to K&S Wire Bonder recognition
software; these fiducials are defined as 0.35mm to 0.40mm square metal areas for all corners with the
exception of the A1 ball corner, where the wire bond fiducial is defined as an “L” pattern with nominal
length and width of 0.40mm and a nominal thickness of 0.10 mm. The wire bond fiducials on customer
designs follow the configuration of the die, where the “odd” fiducial is placed on the “pin 1” corner of
the die. The fiducials are Nickel/Gold plated and are free of soldermask by a minimum space of
0.15mm in all directions.
2.1.2 A1 Corner indicator
STI A1 indicators can be etched into any pattern to meet a given customer’s character recognition
specifications. The A1 indicator in STI open tool parts are designed as an etched triangle of 1.03 mm
(X and Y dimension) placed in the A1 corner of the substrate. The A1 indicator should be placed a
minimum of 0. 25 mm from the edge of the outer most dielectric layer. When a triangle is used, a
minimum of 0.05 mm from the A1 ball pad should be considered, see fig below. There is a solder
mask defined opening to allow for Gold plating of this triangle with a trace from the A1 ball pad.
Solder mask opening is 0.065mm smaller than the triangular pad. (This is the preferred method).
0.15
Fiducial Mark – 3 Fiducial Mark – A1
Photo defined dielectric
Soldermask
Soldermask
Wire-bond
0.15 mm
mm
0.150.15 mm
0.35 mm 0.075 mm
0.65 mm soldermask clearance

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3 lines between
adjacent round pads
4 lines between
adjacent oblong pads
3 lines between
adjacent round pads
4 lines between
adjacent oblong pads
2.1.3 Ball pad specifications
STI ball pad placements conform to customer design specification requirements. All STI open tool
designs conform to requirements specified in:
Jedec Document MO-163 Rectangular PBGA, 1.27mm pitch
Jedec Document MS-034A S-PXGA-X Family Registration
Jedec Document MO-192D Low Profile Ball Grid Array Family
The nominal diameters of the ball pad lands for each standard ball pitch are shown in the below chart.
The maximum number of lines than can be routed between adjacent ball pads is dependent on line
width, ball pad size, and ball pad pitch.
Fig 2.1.3 Oblong ball pad dimensions and routing capacity
Ball Pitch Pad Size TYP
Trace Width
and Space
Lines Between
Round Pads
Lines Between
Oblong Pads
1.27 mm 0.74 mm 0.050 mm 4 6
1.27 mm 0.74 mm 0.045 mm 5 7
1.00 mm 0.60 mm 0.050 mm 3 4
1.00 mm 0.60 mm 0.045 mm 3 5
Feature Solder Ball Pitch
1.27 mm 1.00 mm
Tolerance
Via Diameter–Solder ball pad 0.100 mm 0.100 mm +/-0.010 mm
Solder ball Pad Size – round 0.74 mm 0.60 mm
+0.005 mm
-0.010 mm
Solder ball Pad Size – oblong 0.82x0.54 mm 0.67 x 0.50 mm
+0.005 mm
- 0.010 mm
Soldermask clearance - round 0.565 mm 0.435 mm +/-0.015 mm
Soldermask clearance – oblong 0.655 x 0.385 0.485 x 0.365 +/-0.015 mm

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2.1.4 Power/Ground capability
STI’s Ultra BGA®
design allows for direct ground/ heatsink connection through customer specified ball
lands. The fab process allows for placement of a microvia in said specified lands that is electrically
connected to the heatsink (ground layer) through a plating process. STI specifications for grounded
ball lands can be found in section 4.3. STI Ultra BGA®
power/ground ring designs conform to
customer design specifications.
2.1.5 Multi tier bond ring configuration
STI Ultra BGA designs allow the placement of multiple bond shelves for the Power and Ground
networks. The bond rings are non-soldermask defined.
The ground ring is dielectric-defined and placed directly onto the grounded heatsink. The minimum
bondable area is 0.350 mm. A dielectric area of 0.100 mm from the edge of the cavity to the ground
ring should be considered.
The power ring is placed on the power plane layer; the minimum nominal width is 0.350 mm and
should be recessed 0.100 mm from the outer dielectric edge defining the ground ring. Fig 2.1.5a

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Fig 2.1.5a Multi tier bond ring configuration
STI Ultra BGA multi tier designs allow for multiple power nets on the substrate’s PWR ring area; this is
accomplished by dividing the ring into segments. The minimum length for any ring segment should be
5.00 mm. The minimum distance between ring segments is 0.100 mm and a distance of 0.200 mm
from the center of the wire bond to the edge of the ring segment should be considered. Fig 2.1.5b
Fig 2.1.5b PWR ring segment specifications

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2.1.6 Metal areas
STI Ultra BGA designs utilize the heatsink as a featureless ground layer. In multi layer configurations
additional planes can be added to meet a given customer’s specification. Minimum space between
metal planes and etched traces is 0.127 mm nominal. All STI Ultra BGA®
designs must have the metal
plane recessed a minimum of 0.130 mm from any dielectric edge.
Fig 2.1.6a Metal planes
2.2 Soldermask
2.2.1 Soldermask and dielectric
The soldermask on an STI Ultra SD and Ultra II BGAshall overlap (seal) the dielectric on the outside
edges of the substrate. To accomplish this the first dielectric layer shall be recessed 0. 250 mm from
the outside edge of the substrate. The second dielectric layer shall be recessed 0.250 mm from the
outside edge of the substrate. Soldermask shall then be applied so as to overcoat and seal the
dielectric to the edge of the package perimeter
The Solder ball pads on STI Ultra BGA®
substrates are defined by soldermask clearances as
described in section 2.1; tangency is not allowed, overlap at least 0.015mm.
0.15 mm minimum recess
From edge of dielectric
Copper Substrate
0.127 mm min. between
Plane and etched trace
Copper plane
Dog bone feature
Copper Substrate
0.127 mm min. between
Plane and etched trace
Copper plane
Dog bone feature

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Soldermask
Bond fingers
Soldermask
Power ring
Ground ring
Soldermask
Cavity
Soldermask
Recess from
dielectric edge
Bond fingers
Power ring
0.10 mm spacing
between rings
Ground ring.
2.2.2 Soldermask alignment
The bond finger pattern should be cleared of soldermask. When designs require partial soldermask
coverage of the bond fingers, a 50 µm positional tolerance should be considered when calculating
minimum bonding area.
The over coating of soldermask encroachment on to the bond finger from either direction should not
exceed more than 25% of the total bond finger length.
The soldermask opening shall not PARTIALLY expose a via, only fully open (in ring area) or fully
covered vias are acceptable.
Fig 2.2.2a Soldermask clearance on the wire bond fingers
The minimum width for any soldermask-
defined ring is 0.200mm, see fig. 2.2.2b;
and for non-defined rings is 0.150mm.
The rings are shorted to the internal
layers with the use of micro vias that are
placed on the corners of the rings and/or
in between wire bonds; the vias placed
in between wire bonds are 0.100mm in
diameter with a 0.250mm diameter from
the center of the micro via free of wire
bonds. The vias from external layers
short to the internal layers using “via in
capture pad” method; for rings that are
connected to other internal layers and/or
grounded heatsink, dog bones
described in section 2.1 are used.
Minimum spacing between rings and
other features are held at 0.10 mm
Fig 2.2.2b Soldermask defined rings
(minimum soldermask feature 0.150mm any direction)
Soldermask
Wire bond fingers
< 25% of total
finger length
Soldermask
Wire bond fingers
< 25% of total
finger length
Soldermask
Wire bond fingers
< 25% of total
finger length
Soldermask
Wire bond fingers
< 25% of total
finger length

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Soldermask defined rings placed around the substrate’s cavity should have a minimum nominal width
of 0.100 mm over the minimum bondable area defined by the soldermask clearances. The ring’s
nominal width requirement should be recessed from any dielectric edge a minimum of 0.100 mm to
ensure flatness of the wire bondable area.
2.3 Bond fingers
2.3.1 Bond finger layout
The bond finger array should be placed no closer than 0.100 mm to the closest dielectric edge and at
least 0.050 mm from any metal plane inside the dielectric edge. The minimum distance from any bond
ring to the closest bond finger should be 0.100 mm. Whenever possible, the finger layout should
follow a radial pattern (see fig 2.3.1)
Fig 2.3.1 Radial Pattern Bond Finger Array
Spac
Lengt
Widt
Pitc
Adjacent Bond
150µm
Cavit
Radial bond finger pattern
Space
Length
Width
Pitch
Adjacent Bond
0.1 mm
Cavity
Radial bond finger pattern

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2.3.2 Bond Finger Parameters
Fig 2.3.2 Bond finger array definitions
Bond Finger Design
Feature
Standard Advanced
Bond Finger Width 0.100 mm 0.090 mm
Bond Finger Length 0.350 mm 0.200 mm
Bond Finger Spacing 0.050 mm 0.045 mm
Minimum Finished Bond Flat 0.080 mm 0.070 mm
Bond Finger Pitch 0.150 mm 0.135 mm

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Note: Bond finger Length is determined by assembly process.
2.3.2.1 Staggered bond finger Diagram–External routing Only
FEATURE DIM. Standard Advanced
Staggered Bond Finger Pitch 1 0.1250 0.1125
Bond Finger Row Pitch 2 0.4000 0.4000
In-line Bond Finger Pitch 3 0.2500 0.2250
Bond Finger Dimensions - W 0.1000 0.0900
Designed Bond Finger Dimension - L 0.3500 0.3500
Designed Circuit Width 0.0500 0.0450
Designed Circuit Spacing 0.0500 0.0450
1
3
2
= Outer Layer Routing
= Inner Layer Routing
= Wire Bond Finger
= Via Capture Pad
= Via In Pad

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2.3.2.2 Staggered bond finger diagram – Inner layer routing
FEATURE DIM. Standard Advanced
Staggered Bond Finger Pitch 1 0.075 0.0675
Bond Finger Row Pitch 2 0.650 0.600
In-line Bond Finger Pitch 3 0.150 0.135
Via Capture Pad Diameter 4 0.250 0.200
Via Diameter 5 0.100 0.075
Bond Finger Dimensions - W 0.100 0.090
Designed Bond Finger Dimension - L 0.350 0.350
Designed Circuit Width 0.050 0.045
Designed Circuit Spacing 0.050 0.045
1
2
3
4 5
= Outer Layer Routing
= Inner Layer Routing
= Wire Bond Finger
= Via Capture Pad
= Via In Pad

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Section 3: Materials characteristics
3.1 Photo-imageable dielectric (STI proprietary)
Property Typical Value Test Method
Dielectric Constant (Dk)
@ 1 MHz
@ 100 MHz
@ 1 GHz
@ 2.5 GHz
@ 5 GHz
@ 10 GHZ
@ 30 GHz
3.700000
3.700000
3.850000
4.043333
4.183333
4.223333
4.256667
ASTM-D-2520-95
Loss Tangent
@ 1 MHz
@ 100 MHz
@ 1 GHz
@ 2.5 GHz
@ 5 GHz
@ 10 GHZ
@ 30 GHz
0.000670
0.000860
0.001180
0.001800
0.003033
0.006367
0.008867
ASTM-D-2520-95
Dielectric Strength 2200 V/mm IPC 2.5.6.2
Surface Resistance (W)
A. 96 hrs / 35°C / 90%RH
B. At elev temp/RTI value
4.45 E+11
2.25 E+13
IPC 2.5.17.1A
Volume Resistivity (W-cm)
A. 96 hrs / 35°C / 90%RH
B. At elev temp/RTI value
2.23 E+14
1.34 E+11
IPC 2.5.17.1A
Tensile Strength (Mpa) 7,700 psi IPC 2.4.18.3
Elongation % 5 % IPC 2.4.18.3
3.2 Substrate / Heatsink ( Copper Alloy )
Property Alloy
Density (Lbs/cu” @68°F) 0.322
Modulus of Elasticity (psi) 17 E+ 6
Electrical Conductivity (%IACS @68°F) 60
Thermal Conductivity (BTU/sq ft/hr/F@68°F) 150
Coefficient of Therm Expan (In/°F from 68°F to 572°F 9.7 E- 6
Tensile Strength (x1000 psi) 60 – 70
Yield Strength (x1000 psi) 60
Elongation (nom. % in 2”) 7
Nominal Composition (99% min Cu)

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3.3 Soldermask (Taiyo PSR-4000 AUS 5)
Property Requirement Result
Pencil Hardness Minimum “F” Pass – 6H
Solder Resistance –10 cycles Solder float 10 sec @ 280°C Pass
Dielectric Strength 500 VDC/mil (min) Pass - 3600 VDC/mil
Insulation Resistance
Before Soldering (ohms)
After Soldering (ohms)
5 X 10
8
Minimum
Pass (4.8 x 10
12
)
Pass (1.51 x 10
13
)
Moisture & Insulation Resistance
Before soldering – in chamber
Before soldering – out of chamber
After soldering – in chamber
After soldering – out of chamber
5 X 10
8
Minimum
Pass (1.53 x 10
10
)
Pass (1.07 x 10
12
)
Pass (1.42 x 10
10
)
Pass (1.16 x 10
12
)
Volume Resistivity (Ω-cm) JIS K6911 5.13
25 - 65°C / 90% RH / 7 days
Initial 4.5 x 10
14
Ω
Final 2.9 x 10
13
Ω
Dielectric Constant
See below for High Frequency (1)
JIS C6481 @ 1MHz
25 - 65°C / 90% RH / 7 days
Initial 4.71
Final 5.22
Dissipation Factor
See below for High Frequency (1)
JIS C6481 @ 1MHz
25 - 65°C / 90% RH / 7 days
Initial 0.0332
Final 0.0466
Water Absorption 85°C / 85% RH
% Weight Gain
1Hr: 0.65%
2 Hr: 0.73%
168 Hr: 0.84%
Coefficient Of Linear Expansion TMA Method 1. Below Tg:
2. Above Tg:
6 x 10
-5
1.6 x 10
-4
Tensile Modulus Specific Gravity:
Tensile Force:
Tensile Force Ratio:
Initial Elasticity:
1.5
2.19 kg/mm
2
1.1
3.46 x 10
3
/mm
2
Young’s Modulus JIS K7127 Tensilon TM-H-20 3,500 MPa
Thermal Conductivity (W/mk) Laser Flash (t ½) 0.26
Note: Measured data as provided by material supplier.

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Section 4: Bussing network
STI Ultra BGA®
substrates are designed to minimize cost by selectively gold plating the
critical areas such as ball pads, bond fingers, bond rings, wire bond fiducials and special
customer features. The bussing is accomplished by connecting all of the signals and PWR
networks to GND using a 0.050 mm trace width. The bussing network at any point should be
perpendicular (+/- 20 degrees) from adjacent shorting traces (Fig 4.1).
The bussing network should be placed no closer than 0.100 mm from the outer edge of the
bond finger array. The spacing requirements for the bussing network should comply with the
spacing rules indicated in Section 1.
Fig 4.1 Perpendicular bussing network
All busing shall be done on the outer most metal layer. Special cases where the design does
not allow for full outer layer bussing; internal layer bussing in conjunction with outer layer
bussing shall be implemented. This is accomplished by routing the internal layer nets on any
internal layer towards the center of the cavity, where these nets will be connected to the
grounded heatsink with the use of dog bones and micro vias. The micro vias shall be placed
no closer than 0.75 mm from the cavity edge. The disconnection of the “cavity” bussing will
occur during the cavity mill formation.
The bussing shall be placed in such a manner to allow for an opening in the soldermask layer
no closer than 0.100 mm to any other soldermask opening (Fig 4.2). Also special bussing
shall follow the guide below (Fig 4.3) and shall not be placed outside or under the Resin Dam
/ Encapsulate area (Fig 4.4).

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Fig 4.3 Feature of short ring and soldermask openings

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Fig 4.4 Features of Resin Dam & Bussing

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