Spi master core verification


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Spi master core verification

  1. 1. Serial Peripheral Interface (SPI)Serial Peripheral Interface (SPI)Master CoreVerificationMaster CoreVerificationBy: Maulik Suthar
  2. 2. IntroductionIntroductionWhat is SPI?Properties of SPISPI Master Core SpecificationVerification ApproachEnvironment DiagramTestcasesBUGS!!Conclusion
  3. 3. What is SPI?What is SPI?SPI stands for Serial Peripheral Interface.Synchronous Serial Bus protocoldeveloped by Motorola.Also known as SSI(Synchronous SerialInterface)4-wired serial bus.Simple, fast, easy to use.Accepted by wide number of devicesoffering serial data transmission.
  4. 4. Properties of SPIProperties of SPIAlways FULL DUPLEX.Devices communicate in master-slave mode, master initiates the transfer.Single master – multiple SlavesSingle slave is active at a given instance oftime.Variable transmission speed from slavesupported.
  5. 5. INTERFACEINTERFACEThe SPI bus specifies four logic signalsSCLK: serial clock (output from master)MOSI: master output, slave inputMISO: master input, slave outputSS: slave select (slave enable signal,output from master)
  6. 6. Data TransmissionData TransmissionHost configures the masterMaster initiates the transfer by selectingthe slave, and starting the SCLK.Data from master shifts out from MOSIand slave data shifts in via MISO
  7. 7. SPI Master Core ArchitectureSPI Master Core Architecture
  8. 8. FeaturesFeaturesFull duplex synchronous serial data transferVariable length of transfer word up to 128 bitsMSB or LSB first data transferRx and Tx on both rising or falling edge of serialclock independently8 slave select linesFully static synchronous design with one clockdomainTechnology independent VerilogFully synthesizable
  9. 9. Wishbone InterfaceWishbone Interface SPI Master acts as a slave to the Wishbone Interface. Wishbone communicates with the host Bus signals are as described below:
  10. 10. SPI Core registersSPI Core registersData receive registers, Data transmit register◦ Both are same registers, total four registers each of 32 bits◦ Received data is stored in Rx0, Rx1, Rx2, Rx3 after readcycle◦ Transmitted data is stored in Tx0, Tx1, Tx2, Tx3 duringwrite cycleDivider register◦ This register specifies the SCLK frequency which is derivedby dividing the Master clock
  11. 11. Registers Contd.Registers Contd.Slave Select register◦ bits [7:0] defines the current active slave out of 8slaves.◦ It employs 1-hot encoding as to enable only 1 slave ata time, it its automatically set by master if ASS bit inCTRL is set to 1.Control and status register
  12. 12. Verification approachVerification approachMaster agent is established to simulate thewishbone protocol signals from host side.Slave agent is established to simulate the SPIprotocol.Each agent has its individual sequencer, monitorand driver.The virtual sequencer and scoreboard areincluded in the environment and the top levelmodule which encapsulates the RTL along withthe Testcases.
  13. 13. Steps to drive the DUVSteps to drive the DUV To drive the DUV we need to make the signalswb_we_i = 1,wb_stb_i = 1,wb_cyc_i = 1. This will activate the SPI Master Core and indicate avalid write cycle. Supply the address of the SPI core registers to writeinto and wait for the ack to arrive from the core. After configuring the data, divider, and ss registers atlast configure the CTRL register by making GO_BUSYbit to 1 and start the slave data transfer.
  14. 14. Contd.Contd.After slave completes writing the datainto core’s data registers wb_int_o signalwill be asserted.This indicates end of a valid bus cycle andcore is ready to proceed for next cycle.
  15. 15. TestcasesTestcasesTest_1◦ LSB =1, TxNEG = 1, RxNEG = 0.Test_2LSB =1, TxNEG = 0, RxNEG = 1.Test_3LSB =0, TxNEG = 0, RxNEG = 1.Test_4LSB =0, TxNEG = 1, RxNEG = 0.
  16. 16. BUGS!!BUGS!!Able to find two BUGS!! In the design ofSPI master core.First bug is found in MISO coming fromslave side.When the SCLK starts, the data to betransferred is not arriving at triggeringedge of the SCLK as a result X istransferred into the master.
  17. 17. Screenshot of BUGScreenshot of BUG
  18. 18. Another BUG!! Is found in the MOSIcoming out of the master core.The applied data to be transmitted toslave is shifted 1-bit right, when collectedfrom slave monitor.01001001110111010101100011000100 MOSI from mastermonitor00100100111011101010110001100010 MOSI from slavemonitor
  19. 19. Design with Multiple SlavesDesign with Multiple Slaves• Design with a single master and multipleindependent slaves.• This Design supports up to 8 slaves which can beaddressed using SS signal independently.
  20. 20. ConclusionConclusionDesign was verified based on UVMmethodology.Simulation was done in Questasim usingSystemVerilog.Two critical bugs were found duringVerification.Functional coverage was implementedand achieved 92.85% of functional codecoverage for this design.
  21. 21. Pros & Cons of SPIPros & Cons of SPIFast & easy to implement.Best choice for point-to-pointconnections.Easily supported by devices.Lack of ACK mechanism.Doesnt have in-built addressing forslavesMultiple slaves increases its complexity.No data error control and flow control.Cant detect if slave present or not.