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Fpga implementation of  utmi  with usb 2.O
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Fpga implementation of utmi with usb 2.O

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THIS IS THE PROJECT PRESENTATION ON UTMI MODULE WITH USB 2.0

THIS IS THE PROJECT PRESENTATION ON UTMI MODULE WITH USB 2.0

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  • 1. FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATION 1 GUIDED BY RENEESH .C. ZACHARIAH ASSISTANT PROFESSOR ECE DEPARTMENT MLMCE PRESENTATION BY MATHEW GEORGE MTECH VLSI&ES ROLLNO.8 MLMCE KOTTAYAM
  • 2. OUTLINE  INFORMATION OF LITERATURE  INTRODUCTION  DEVICE ANATOMY  FUNCTIONAL BLOCK DIAGRAM  MACROCELL FEATURES & FUNCTIONS  INTERFACE FEATURES & OPTIONS  TRANSMITTER & RECEIVER MODULE  SCHEMATIC VIEW  SIMULATOIN RESULT  SYNTHESIS REPORT  CONCLUSION  FUTURE SCOPE  APPLICATIONS  REFERENCES 2
  • 3. INFORMATION OF LITERATURE  “FPGA Implementation of USB Transceiver Macro cell Interface with USB 2.0 specification. ”  K. Babulu , K Soundara Rajan  First International Conference on Emerging Trends in Engineering and Technology IEEE 2008 3
  • 4. INTRODUCTION  The Universal Serial Bus (USB) Transceiver Macroc ell Interface (UTMI) is a two wire, bidirectional serial bus interface between USB devices through D+ and D- lines.  There are three functional blocks present in USB controller, they are  Serial Interface Engine (SIE), UTMI and Device Specific Logic (DSL). 4
  • 5. BASIC BLOCK DIAGRAM 5 Figure 1: Block diagram of UTMI.
  • 6. CONT…  The parallel data from SIE is taken into the transmit hold register .  This data is sent to transmit shift register .  This serial data is bit stuffed to perform data transitions for clock recovery and NRZI(1) encoding  Then the encoded data is sent on to the serial bus. 6
  • 7. CONT…  When the data is received on the serial bus, it is decoded, bit unstuffed  And is sent to receive shift register.  After the shift register is full, the data is sent to receive hold register 7
  • 8. Device Anatomy  USB Transceiver Macro cell (UTM)  Serial Interface Engine  Device Specific Logic 8 ASIC Serial Interface Engine Device Specific Logic Endpoint Logic Endpoint Logic … SIE Control Logic Endpoint Logic Device Hardware USB 2.0 Transceiver UTM Interface USB 2.0
  • 9. Serial Interface Engine  SIE Control Logic • USB Transaction State Machine • PID, Address, and EP match logic • Checks receive completion status • Chains packets into transactions  Endpoint Logic • FIFOs and FIFO control 9 Serial Interface Engine Endpoint Logic Endpoint Logic … SIE Control Logic Endpoint Logic Control Data In Data Out To Device Specific Logic To Transceiver
  • 10. Transceiver Macro cell  Converts USB signaling into a parallel interface • USB 2.0 compliant serial interface • Multiple Parallel Data Interface Options • Multiple Speed Options – HS/FS, FS Only, LS Only 10 USB 2.0USB 2.0 Transceiver Control Data In Data Out To SIE To Bus
  • 11. FUNCTIONAL BLOCK DIAGRAM 11Figure 2. UTMI Functional Block Diagram.
  • 12. MACROCELL FEATURES  UTMI is one of the most important blocks of USB Controller.  This block handles the low level USB protocol and signaling.  This includes features such as data serialization, deserialization, bit stuffing, bit de stuffing, Non Return to Zero Invert on ‘1’(NRZI) encoding, decoding, clock recovery and synchronization 12
  • 13. Macrocell Functions  HS and FS signaling and termination  HS receiver squelch  USB clock recovery  Bit stuffing and unstuffing  NRZI encoding and decoding  Serializing and deserializing  Data-rate tolerance  Data buffering  Single interface for HS/FS, FS or LS operation 13
  • 14. Interface Features  Packet Engine • Automatically handles SYNC Pattern and EOP  Flow Control • Compensates for Bit Stuffing and Data Rate Toler ance  Complete Primitives for Full Protocol Support  Speed Switching  Clock Generation  Power Control 14
  • 15. Interface Options  Integrated Macro cell • 8-Bit Uni-directional • 16-Bit Uni-directional  Discrete Transceiver • 8-Bit Bi-directional • 16-Bit Bi-directional / 8-Bit Uni-directional 15
  • 16. CLOCK MULTIPLIER  This module generates the appropriate internal clocks for the UTMI and the CLK output signal  All data transfer signals are synchronized with the CLK signal.  HS/FS OPERATION  Supports 480 Mbit/s High Speed (HS)/ 12 Mbit/s  Full Speed(FS), serial data transmission rates.  In HS mode there is one CLK cycle per bit time  In FS mode there are 5 CLK cycles per FS bit time 16
  • 17. TRANSMITTER MODULE SYNC GENERATOR  The TX valid signal is asserted by the SIE  Transmit state machine enters into send Sync state where a signal called sync enable is asserted.  This signal is checked at every rising edge of the clock out side the state machine.  When this signal is enabled, a sync pattern is send to the NRZI encoder 17
  • 18. TX SHIFT /HOLD REGISTER  This module is responsible for reading parallel data from the parallel application bus interface  This module consists of an 8-bit primary shift register for parallel/serial conversion  An 8-bit Hold register used to buffer the next data to serialize. 18 Figure 3: Transmit shift/Hold register
  • 19. NRZI ENCODER  Non Return to Zero Invert on ‘1’ Encoder.  This is a standard USB 1.X compliant serial NRZI encoder module,  It can operate at full-speed or high-speed USB data rates.  Whenever a bit ‘1’ is encountered in the data stream, it is negated.  A bit ‘0’ is transmitted as it is depend on the Operational Mode. 19
  • 20. BITSTUFF LOGIC  To ensure adequate signal transitions, bit stuffing is employed when sending data on USB.  A zero is inserted after every six consecutive ones in the data stream before the data is NRZI encoded,  Bit stuffing is enabled beginning with the SYNC Pattern and through the entire transmission.  In FS mode bit stuffing by the transmitter is always enforced, without exception.  During Bit Stuffing, the transmit state machine is in Data wait state. 20
  • 21. EOP GENERATOR  When TX valid signal is negated by the SIE, the transmit state machine enters into send EOP state .  This signal is checked out side the state machine for every clock.  If this signal is high then the EOP pattern: two single ended zeroes (i.e, DP, DM lines contain zeroes)  And a ‘J’ (i.e, a ‘1’ on DP line and a ‘0’ on DM line) is transmitted on to DP, DM lines. 21
  • 22. TRANSMITTER STATE DIAGRAM 22 Figure 4: Transmit state machine
  • 23. TRANSMIT STATE DIAGRAM  Transmit must be asserted to enable any transmissions.  The SIE asserts TXValid to begin a transmission  The SIE negates TXValid to end a transmission.  After the SIE asserts TXValid it can assume that the transmission has started when it detects TXReady asserted. 23
  • 24. CONT..  The SIE assumes that the UTMI has consumed a data byte if TXReady and TXValid are asserted.  TXValid and TXReady are sampled on the rising edge of CLK.  The SIE must use Line State to verify a bus Idle condition before asserting TXValid in the wait state. 24
  • 25. RECEIVER MODULE SYNC DETECTOR  To detect the SYNC pattern a state machine is developed  It checks every bit for every rising edge of the clock.  If the pattern is detected, a signal called sync detected is enabled.  This signal is checked by the Receive state machine.  If the signal is high,the Receive state machine will enter into strip sync state .  Where RX active signal is asserted and the state machine will enter into RX data state. 25
  • 26. RX SHIFT/HOLD REGISTERS  This module is responsible for converting serial data received from the USB to parallel data.  It consists of an 8-bit primary RX Shift Register for serial to parallel conversion  And an 8-bit RX Hold Register used to buffer received data bytes and present them to the Data Out bus. 26 Figure 5: Rx Shift/Hold Register
  • 27. NRZI DECODER  This is a standard USB 1.X compliant serial NRZI decoder module.  It can operate at FS or HS USB data rates.  The data received on DP, DM lines is NRZI(1) decoded and it is sent to the bit unstuff module.  The NRZI Decoder simply XOR the present bit with the provisionally received bit.  During NRZI decoding, the receive state machine is in RX wait state. 27
  • 28. BIT UNSTUFF LOGIC  The Bit Unstuffer examines each bit of the stream.  If a zero is detected after six consecutive ‘1’s the zero bit is deleted.  A state machine is designed which is invoked at every rising edge of the clock.  The state of the machine will change to the next state until six consecutive ‘1’ and a bit ‘0’ or detected 28
  • 29. CONT…  During bit Unstuffing, the receive state machine is in RX data wait state  If a zero is not detected after six consecutive ‘1’ the state machine asserts a signal called rx_error  This signal is checked by the receive state machine for every clock. 29
  • 30. EOP DETECTOR  A state machine is developed for EOP detection, which is invoked at every rising edge of the clock.  When this signal is high, the receive state machine will enter in to Strip eop state  Where the EOP pattern is stripped off and RX active, RX valid signals are negated. 30
  • 31. RECEIVER STATE DIAGRAM 31 Figure 6: Receive state machine
  • 32. CONT..  RXActive and RXValid are sampled on the rising edge of CLK.  In the RX Wait state the receiver is always looking for SYNC.  The Macrocell asserts RXActive when SYNC is detected (Strip SYNC state).  The Macrocell negates RXActive when an EOP is detected (Strip EOP state). 32
  • 33. CONT…  When RxActive is asserted, RXValid will be asserted if the RX Holding Register is full.  RXValid will be negated if the RX Holding Register was not loaded during the previous byte time.  This will occur if 8 stuffed bits have been accumulated  The SIE must be ready to consume a data byte if RXActive and RXValid are asserted (RX Data state).  33
  • 34. CONT…  In FS mode, if a bit stuff error is detected then the Receive State Machine will negate RXActive and RXValid and return to the RXWait state. 34
  • 35. UTMI SIGNAL DESCRIPTION 35 Table 1: System Interface Signals
  • 36. 36 SCHEMATIC VIEW
  • 37. RTL SCHEMATIC-TRANSMITTER 37
  • 38. RTL SCHEMATIC-TRANSMITTER 38
  • 39. TECHNOLOGY SCHEMATIC 39
  • 40. RTL SCHEMATIC -RECEIVER 40
  • 41. RTL SCHEMATIC -RECEIVER 41
  • 42. TECHNOLOGY SCHEMATIC 42
  • 43. RTL SCHEMATIC -UTMI 43
  • 44. RTL SCHEMATIC -UTMI 44
  • 45. TECHNOLOGY SCHEMATIC 45
  • 46. 46 SIMULATION RESULTS
  • 47. TRANSMITTER MODULE 47
  • 48. RECEIVER MODULE 48
  • 49. UTMI 49
  • 50. UTMI
  • 51. UTMI
  • 52. 52 SYNTHESIS REPORT
  • 53. PLACE AND ROUTE SYNTHESIS 53
  • 54. TIMING SYNTHESIS 54
  • 55. POWER ANALYSIS FS CLK 55
  • 56. POWER ANALYSIS HS CLK
  • 57. TOOLS USED  The individual modules of the UTMI are designed using VHDL .  Simulated using Model Sim ALTERA STARTER EDITION 10.0d environment.  Synthesis design using XILINX ISE 13.2 57
  • 58. CONCLUSION  The individual modules of UTMI have been designed, verified functionally using VHDL simulator.  The UTMI Transmitter is capable of converting parallel data into serial bits, performing bit stuffing and NRZI encoding.  The UTMI Receiver is capable of performing NRZI decoding bit unstuffing and converting serial bits into parallel data. 58
  • 59. CONT…  The functional simulation has been successfully carried out.  The design has been synthesized using FPGA technology from Xilinx 59
  • 60. FUTURE SCOPE  The UTMI has been implemented is 8-bit one, it can also be extended to 16- bit UTMI.  It can also be designed to generate CRCs for control and data packets.  Similar implementation can be done for UTMI with USB 3.0 specification 60
  • 61. APPLICATION  The UTMI has been developed into a common code (Generalized USB Transceiver) which can be used for developing the complete USB device stack.  Some of the Low speed and High speed USB devices, which are presently in the market, are:  Optical Mouse, Key Board, Printer, Scanner ,Joy Stick Memory Stick, Flash Memory, Mobiles,Video camera s etc. 61
  • 62. REFERENCE 1.USB 2.0 Specification, April 27, 2000 . 2.USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, version 1.05, March 29, 2001 3.On-The-Go Supplement to the USB 2.0 Specification , revision 1.0, Dec 18, 2001 4.UTMI+ Specification, revision 0.9, February 21,2001 5.VHDL With Example Douglas .L .Perry 6. Data and Computer Communications by William Stallings 7.Computer Networks by Andrew S.Tannenbaum 62
  • 63. 63