Array multiplier
Upcoming SlideShare
Loading in...5
×

Like this? Share it with your network

Share

Array multiplier

  • 8,845 views
Uploaded on

 

  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Be the first to comment
No Downloads

Views

Total Views
8,845
On Slideshare
8,845
From Embeds
0
Number of Embeds
0

Actions

Shares
Downloads
191
Comments
0
Likes
1

Embeds 0

No embeds

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
    No notes for slide

Transcript

  • 1. Array Multiplier Haibin Wang Qiong Wu
  • 2. Outlines Background & Motivation Principles Implementation & Simulation Advantages & Disadvantages Conclusions
  • 3. Background & Motivation One of the most critical functions carried out by ALU Digital multiplication is the most extensively used operation (especially in signal processing), people who design digital signal processors sacrifice a lot of chip area in order to make the multiply as fast as possible Innumerable schemes have been proposed for realization of the operation
  • 4. Multiplication Schemes Serial Multiplication (Shift-Add)  Computing a set of partial products, and then summing the partial products together.  The implementations are primitive with simple architectures (used when there is a lack of a dedicated hardware multiplier) Parallel Multiplication  Partial products are generated simultaneously  Parallel implementations are used for high performance machines, where computation latency needs to be minimized
  • 5. Principles of Array Multiplier 4*4 bit multiplication a3 a2 a1 a0 × b3 b2 b1 b0 a3b0 a2b0 a1b0 a0b0 a3b1 a2b1 a1b1 a0b1 a3b2 a2b2 a1b2 a0b2 a3b3 a3b2 a3b1 a3b0 p7 p6 p5 p4 p3 p2 p1 p0
  • 6. For 4*4 Array Multiplier, it needs16 AND gates, 4 HAs, 8FAs (total12 Adders)For m*n Array Multiplier, it needsm*n AND gates, n HAs, (m-2)*nFAs, (total (m-1)*n Adders)
  • 7. Principles of Array Multiplier(Cont.)
  • 8. Principles of Array Multiplier(Cont.)
  • 9. Implementation & Simulation Verilog (ISE 10.1) Multiplier Design  Cell: MulCell  Multiplier: ArrayMult Testbench  Stimulus  Verification & Timing
  • 10. Cell
  • 11. Multiplier
  • 12. Simulation Result & Timing
  • 13. Advantages & Disadvantages Advantages:  Minimum complexity  Easily scalable  Easily pipelined  Regular shape, easy to place & route Disadvantages:  High power consumption  More digital gates resulting in large chip area
  • 14. Conclusions Array multiplier is implemented and verified in Verilog Although it utilizes more gates, the performance can easily be increased using pipeline technique As a parallel multiplication method, array multiplier outperforms serial multiplication schemes in terms of speed.
  • 15. Reference [1]. http://www.trivology.com/articles/534/what-is-an- array-multiplier.html [2]. http://ece.gmu.edu ece645_lecture7.ppt
  • 16. Questions?