Background & Motivation One of the most critical functions carried out by ALU Digital multiplication is the most extensively used operation (especially in signal processing), people who design digital signal processors sacrifice a lot of chip area in order to make the multiply as fast as possible Innumerable schemes have been proposed for realization of the operation
Multiplication Schemes Serial Multiplication (Shift-Add) Computing a set of partial products, and then summing the partial products together. The implementations are primitive with simple architectures (used when there is a lack of a dedicated hardware multiplier) Parallel Multiplication Partial products are generated simultaneously Parallel implementations are used for high performance machines, where computation latency needs to be minimized
Advantages & Disadvantages Advantages: Minimum complexity Easily scalable Easily pipelined Regular shape, easy to place & route Disadvantages: High power consumption More digital gates resulting in large chip area
Conclusions Array multiplier is implemented and verified in Verilog Although it utilizes more gates, the performance can easily be increased using pipeline technique As a parallel multiplication method, array multiplier outperforms serial multiplication schemes in terms of speed.