949 Lake Rd. C: 802-488-4955
Milton, VT 05468 H: 802-893-7262
Seeking a technical position with opportunities for collaboration in a variety of science,
engineering and business disciplines.
IBM Microelectronics: Advisory Engineer. ASICs and EDA groups. 1998-2013
Synopsys DesignWare Developer
Designed and implemented standard-cell based components in Verilog and VHDL to facilitate
datapath/bitstacking layout. IP was delivered to ASICs customers as Synopsys DesignWare libraries
in 250nm, 180nm , 130nm and 90nm technologies.
Synthesis/Physical Synthesis Methodology Developer
Responsible for the development, support and documentation of synthesis, physical synthesis and
design planning methodologies for Synopsys, Cadence and Magma tool offerings. Integrated multiple
software tools into seamless design flows based on the IBM ASICs Methodology. Documented and
provided customer support for these tools and methodologies.
Methodology Test Developer
Developed testcase designs using Verilog HDL and SDC assertions for exercise of IBM ASICs design
methodology. Gathered testing requirements from all tool and methodology teams and developed
testcase designs suitable to exercise all tools and features. Successfully pushed for a “flow based”
approach to model, software and methodology development and test starting with 65nm technology,
vastly improving development quality.
Led a major and successful development effort for incorporating 3rd party memory IP in 65 nm and 45
nm ASIC designs. Scheduled and coordinated development for all stages of design methodology
including, but not limited to RTL synthesis, scan insertion, physical design and test generation.
Developed PERL and TCL software for creation and checking of IP models for IBM memory BIST
and repair system used on all 45 nm and 65 nm ASIC chips. Coordinated customer support and IBM
Design Center support for this system.
Primary development, support and test engineer for TCL-based software used for IBM ASICs power
estimation and signoff. Correlated .lib and IBM NDR based power estimates between IBM tools and
Synopsys PrimeTime PX. Developed scriptware for fine tuning switching activity numbers for
accurate power estimation. Co-developed a models-based methodology for calculating detailed
memory switching activity from high level design parameters.
Synthesis and physical synthesis methodology development and support with Synopsys, Cadence and
IBM design automation software. Strong background with Synopsys Design Compiler. Experience
with Cadence RTL Compiler, Magma tools and multiple IBM-developed electronic design tools for
timing, floorplanning, layout and power estimation.
Experience with Verilog HDL, VHDL, PERL and TCL.
Familiar with .lib, LEF, DEF, PDEF, SDF, SAIF, SDC and other semiconductor industry standard
design and data formats.
Solid background with low-power design methodologies including design synthesis and optimization
with multiple voltage threshold devices, voltage islands and voltage binning.
Strong Unix/Linux skills.
Excellent communication, public speaking, writing and presentation skills.
University of Maine at Orono 1995-1998
Bachelor of Science in Electrical Engineering, summa-cum-laude: 1998
Bates College: 1990-1994
Bachelor of Science in Economics: 1994
Height: 6'1” Weight 200 lbs
Blood Pressure 126/80
Total Cholesterol Level: 118 mg/dL
Triglycerides Level: 54 mg/dL
1 patent pending
Toastmasters International Certified Advanced Communicator & Advanced Leader.
Four time Synopsys Users Group (SNUG) author.
Sue Bentlage, Functional EDA Development Manager 802-324-3063, firstname.lastname@example.org
Christopher Kiegle, Advisory Engineer 802-769-7618, email@example.com