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MELJUN CORTES - IC & Number System

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- 1. Year 1 LESSON 5INTERGRATED CIRCUITCS113/0401/v1 Lesson 5 - 1
- 2. Year 1 NOT P NOT P T F F T Truth Table P NOT P 1 0 0 1 INPUT P NOT P OR P OUTPUT NOT-GATECS113/0401/v1 Lesson 5 - 2
- 3. Year 1 OR (WITH 2 INPUTS) p q p OR q 0 0 0 0 1 1 1 0 1 1 1 1 Truth Tablep p or q OUTPUT INPUTSq OR-GATE CS113/0401/v1 Lesson 5 - 3
- 4. Year 1 OR (WITH 3 INPUTS) p q r p OR q OR r 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1INPUTS p OUTPUT q r p or q or r Truth Table OR-GATE with 3 Inputs CS113/0401/v1 Lesson 5 - 4
- 5. Year 1 AND (With 2 Inputs) p q p AND q 0 0 0 0 1 0 1 0 0 1 1 1 Truth TableINPUTSp OUTPUT p AND qq OR-GATE CS113/0401/v1 Lesson 5 - 5
- 6. Year 1 AND (WITH 3 INPUTS) p q r p AND q AND r 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Truth TableINPUTS p OUTPUT q r p AND q AND r AND-GATE with 3 Inputs CS113/0401/v1 Lesson 5 - 6
- 7. Year 1 EXAMPLE WITH 3 GATES A B C B A.B D 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 Truth TableA A.B BB A.B+C DC 3 Gates D = (A and not B) or C or D = (A.B) + C CS113/0401/v1 Lesson 5 - 7
- 8. Year 1 NAND-GATE A B A NAND B 0 0 1 0 1 1 1 0 1 1 1 0 Truth Table p A NAND B q pSymbo A NAND B ql Circuit Diagram CS113/0401/v1 Lesson 5 - 8
- 9. Year 1 NOR-GATE A B A NOR B 0 0 1 0 1 0 1 0 0 1 1 0 Truth TableA A NOR BBA A NOR BB Circuit Diagram CS113/0401/v1 Lesson 5 - 9
- 10. Year 1 NAND GATE (UNIVERSAL GATE)♦ NAND gate can be modified to function as NOR gate, OR gate♦ NOR function B XA CNB: B, C inputs follow from A A B C X 0 0 0 1 1 1 1 0 CS113/0401/v1 Lesson 5 - 10
- 11. Year 1 NAND GATE (UNIVERSAL GATE) OR function X =A=B = A + B ( Double negation ) = A • B ( DeMorgan’s Law )A A XB B CS113/0401/v1 Lesson 5 - 11
- 12. Year 1 COMBINING LOGIC GATES ♦ Many everyday digital logic problems use several logic gates. The most common pattern of gates is shown below. This pattern is called the AND-OR pattern. The outputs of the AND gates ( 1 and 2 ) are used as inputs to the OR gate ( 3 ). You inputs ( A,B and C ). The output of the entire circuit is labeled as Z. A B (1) (3) Z (2) C( a) AND-OR logic circuit CS113/0401/v1 Lesson 5 - 12
- 13. Year 1COMBINING LOGIC GATES A (1) B (3) Z (2) C ( b ) Same circuit with Boolean expressions at the outputs of the AND gatesA (1)B (3) Z=A.B+B.C (2)C( c ) Same circuit with Boolean expressions at the outputs of the OR gates CS113/0401/v1 Lesson 5 - 13
- 14. Year 1COMBINING LOGIC GATES♦ Let us first determine the Boolean expression that will describe this logic circuit. Begin the examination at gate (1). This is a 2-input AND gate. The output of this gate is A . B ( A AND B ) . This expression is written at the output of gate (1) in figure (b) above.♦ Gate (2) is also a 2-input AND gate. The output of this gate is B . C ( B AND C ). This expression is written at the output of gate (2). Next the output of gate (1) and (2) are OR-ed together by gate (3). Figure (c) shows A. B being OR-ed with B.C.♦ The resulting Boolean expression is Z = A . B + B . C. It is read as ( A AND B ) OR ( B AND C ). You will notice that the AND is done first, followed by the OR- ing. CS113/0401/v1 Lesson 5 - 14
- 15. Year 1Example: A logic circuit is given as follows: A A A+B B (3) Z C D C+DThe Boolean expression is Z = ( A+B ) . (C+D) C B A♦ Example: A logic circuit is given as follows: B A (2) (1) A.B A.B (3) The Boolean expression is Z = A . B + A . B CS113/0401/v1 Lesson 5 - 15 Z
- 16. Year 1 ANALYSING CIRCUITS AA B A.B.CB CC A B X C A.B.C A B A.B X = A . B .C + A . BC + A . B ♦ From the diagram, we see that each of the outputs from the 3 AND gates will be a ‘1’ or a ‘0’ and they serve as the inputs to the ‘OR’ gate which is represented by the ‘+’ sign. CS113/0401/v1 Lesson 5 - 16
- 17. Year 1 ANALYSING CIRCUITS♦ Switching circuits are often over- complicated because they duplicate or even triplicate or quadruplicate functions. The B C A results of rigorous simplification can, however, be quite startling. B A A.C A.C (3) X=A.B+A.C Simplified circuit Lesson 5 - 17 X CS113/0401/v1

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