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### MELJUN CORTES Logic Design

1. 1. Digital Logic DesignMELJUN CORTES,BSCS,ACSDepartment of ICTFaculty of Information Technology
2. 2. 1. Introduction1.1. Review of Number Systems1.2. Switching Algebra and Logic CircuitsPage  2
3. 3. Chapter 1. IntroductionPage  3
4. 4. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  4
5. 5. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  5
6. 6. 1.1.1. Number Representation  Numbers are normally written using a positional number system: N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m – Base/radix: b (the number of digits) – Digits: 0..(b-1) • 0 ≤ ai ≤ (b-1) – Binary: b=2, digits:0,1 – Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9 – Octal: b=8, digits: 0,1,2,3,4,5,6,7 – Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,FPage  6
7. 7. 1.1.1. Number Representation N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m n N (10 ) = ∑ a .b i =− m i i11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2= 29.75(10) Page  7
8. 8. 1.1.1. Number Representation  Decimal: – b=10 – Digits: 0,1,2,3,4,5,6,7,8,9 N (10 ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a−m ai = 0..9 – Eg: 539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2Page  8
9. 9. 1.1.1. Number Representation Binary: – b=2 – Digits: 0,1 bit – binary digit N ( 2 ) = an an −1an −2 ...a1a0 .a−1a− 2 ...a−m ai = 0,1 n – Eg: N (10 ) = ∑ a .2 i =− m i i 1011.011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.25 + 0.125 = 11.375(10)Page  9
10. 10. 1.1.1. Number Representation  Binary (cnt’) – n-bit binary number can represent which range? • an-1...a1a0 from 0 to 2n-1 – MSB – Most Significant Bit – LSB – Least Significant Bit 0001 = 1 1001 = 9 0010 = 2 1010 = 10 0011 = 3 1011 = 11 0100 = 4 1100 = 12 0101 = 5 1101 = 13 0110 = 6 1110 = 14 0111 = 7 1111 = 15 1000 = 8Page  10
11. 11. 1.1.1. Number Representation Octal: – b=8 N (8) = an an −1...a1a0 .a−1a− 2 ...a− m – Digits: 0,1,2,3,4,5,6,7 – Eg: ai = 0..7 503.071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3  Hexadecimal: N (16 ) = an an −1...a1a0 .a−1a− 2 ...a− m – b=16 ai = 0..F – Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F – Eg: 1010 0011(2)= A3(16)Page  11 503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3
12. 12. Convert from base b to base 10 Base b to base 10 conversion N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m Eg:0 – 1010.11(2)= 10.75 – 1010.11(8)= 0*80+1*81+0*82+1*83 + 1*8- 1 +1*8-2 = 0+8+0+512+0.125+0.015625 – A12(16)= 10572 = 2*160 + 1*161 + 10*162 =Page  12
13. 13. 110.011(2)=?(10) 6.375110.011(8)=?(10) 72.0175110.011(16)=?(10) 272.039...Page  13
14. 14. Convert from base 10 to base b Base 10 to base b conversion – For integer part: • Divide integer part by b until the result is 0 • Write remainders in reverse order to get the converted result. – For the odd part after “.” • Multiply by b until the result is 0Page  14
15. 15. Convert from base 10 to base 2  Eg1: 6.625(10) = ?(2) – The integer part – The odd part after “.” • 0.625 x 2 = 1.25 6 2 • 0.25 x 2 = 0.5 0 3 2 • 0.5 x 2 = 1.0 1 1 2 1 0 6.625(10) = 110.101(2)  Eg2: 20.75(10) = ?(2)Page  15
16. 16.  20.75(10) = ?(2) 10100.11(2) 20 2 0.75 * 2 = 1.5 0 10 2 0.5 * 2 = 1.0 0 5 2 1 2 2 0 1 2 1 0Page  16
17. 17.  20.75(10)=?(8) =10100.11(2) = 24.6(8) 20 8 0.75 * 8 = 6.04 2 8 2 0Page  17
18. 18. Convert from base 2 to base 2n Group from right to left n-bit groups and replace the equivalent values in base 2n Eg: 101011(2) = ?(8) 1010.110(2)=12.6(8) 101011(2) = ?(16) 1010.110(2)=A.C(16)Page  18
19. 19. Convert from base 2n to base 2 Each digit in base 2n is replaced by n bit in base 2. Eg: 37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)Page  19
20. 20. Convert from base i to base j If both i and j are powers of 2, use base 2 as an intermediate base: – Eg: base 8 → base 2 → base 16 – 735.37(8)= 000111011101.01111100(2) = 1DD.7C ?(16) Else, use base 10 as an intermediate base: – Eg: base 5 → base 10 → base 2Page  20
21. 21. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  21
22. 22. 1.1.2 Binary Addition  Binary long addition similar to decimal long addition. decimal binary carry 110 11110 A 2565 10110 B 6754 11011 sum 9319 110001 Eg: 10101(2) + 11011(2) = 110000 ? (2)Page  22
23. 23. 1.1.2 Binary Addition  Overflow: – Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits) – In 8-bit computer, the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflowPage  23
24. 24. 1.1.2 Binary Addition n-bit adder in computer: A = an-1an-2...a1a0 B = bn-1bn-2...b1b0Page  24
25. 25. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  25
26. 26. 1.1.3 Signed Numbers Represent sign and amplitude Use the most-left-bit to represent sign: – 0: positive, 1: negative Eg: represent signed numbers using 4 bit: – +5 = 0101, -5 = 1101, -3 = 1011 – Using 3 right bits to represent amplitude, we can represent from -7 to +7. – Drawbacks: • +0 = 0000, -0 = 1000 => complex when calculatingPage  26 => need an other representation
27. 27. 2’s complement representation  Most left bit is still sign bit  Positive and 0 numbers are expressed in usual binary format. – The largest number can be represented is 2n-1-1 – n=8 => largest signed number: 28-1-1 = 127  Negative number a is stored as the binary equivalent of 2n- a in a n-bit system. – -3 is stored as 28-3=11111101 in a 8-bit system – The most negative number can be stored is -2n-1Page  27
28. 28. 2’s complement representation +10 = 0000 1010 - 10 = 28-10 = 1 0000 0000 – 0000 1010 1111 0110 - 10 = 1111 0110 +10 + (-10) = ? 0000 1010 1111 0110 1 0000 0000Page  28
29. 29. 2’s complement representation  Procedure to find binary representation of negative number in 2’s complement: – Find the binary equivalent of the magnitude – Complement each bit (0=>1, 1=>0) – Add 1  Eg: find representation of -13 in 8-bit signed number system using 2’s complement: • Magnitude: 13 = 0000 1101 • Complement: 1111 0010 • Add 1: 1 + • -13 = 1111 0011Page  29
30. 30. 2’s complement representation Range of representation: – Use n bit to represent 2’s complement numbers – Range: -2n-1 => 2n-1-1Page  30
31. 31. 4 bit representation of unsigned and signed (2’s complement) Binary format Unsigned Signed 0000 0 0 0001 1 +1 0010 2 +2 0011 3 +3 0100 4 +4 0101 5 +5 0110 6 +6 0111 7 +7 1000 8 -8 1001 9 -7 1010 10 -6 1011 11 -5 1100 12 -4 1101 13 -3 1110 14 -2 1111 15 -1Page  31
32. 32. 2’s complement representation To find the magnitude of a negative number: – Complement each bit – Add 1 Eg: 1001 0110(2) = -106? 0110 1001 + 1 01101010 = 106Page  32
33. 33. Addition of signed numbers The reason that 2’s complement is so popular is the simplicity of addition. To add any two numbers, no matter what the sign of each is, we just do binary addition on their representation. -5 1011 -5 1011 -5 1011 +7 0111 +5 0101 +3 0011 +2 0010 0 0000 -2 1110Page  33
34. 34. Addition of signed numbers Overflow – Occur when? – Add two numbers of the opposite sign? – Add two positive numbers? – Add two negative numbers? maybe ⇒Overflow occurs when adding two numbers with the same sign and the result is in different sign 0110 0101 = 101 + 0101 0010 = 82Page  34 1011 0111
35. 35. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  35
36. 36. 1.1.4 Binary Subtraction Find the 2’s complement of the second operand, then add. a – b = a + (-b) Eg: 7 – 5 = ? 5 0101 7 0111 1010 -5 +1011 + 1 2 0010 -5 1011Page  36
37. 37. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  37
38. 38. Binary-Coded Decimal - BCD BCD: Decimal Binary BCD – Use four bits (a nibble) to represent 0 0000 0000 each of the decimal digits 0 through 1 0001 0001 9. 2 0010 0010 – Eg: 3 0011 0011 4 0100 0100 375 = 0011 0111 0101(BCD) 5 0101 0101 6 0110 0110 7 0111 0111 8 1000 1000 9 1001 1001 10 1010 0001 0000 11 1011 0001 0001 12 1100 0001 0010 13 1101 0001 0011 14 1110 0001 0100 15 1111 0001 0101Page  38
39. 39. 1.1. Review of Number Systems 1.1.1 Number Representation 1.1.2 Binary Addition 1.1.3 Signed Numbers 1.1.4 Binary Subtraction 1.1.5 Binary Coded Decimal (BCD) 1.1.6 Other CodesPage  39
40. 40. ASCII American Standard Code for Information Interchange - ASCII Use seven bits to represent various characters on the standard keyboard as well as a number of control signalPage  40
41. 41. Page  41
42. 42. Problems1. Convert the following unsigned numbers: a. 98.625(10)=?(2) b. 11011.011(2)=?(10) c. 6A1.1E(16)=?(8)2. Represent the following signed numbers: a. -74 in 8-bit signed 2’s complement. b. -74 in 16-bit signed 2’s complement.Page  42
43. 43. 1. Introduction1.1. Review of Number Systems1.2. Switching Algebra and Logic CircuitsPage  43
44. 44. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.4 Representations of Algebraic Functions1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  44
45. 45. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.3 Representations of Algebraic Functions1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  45
46. 46. 1.2.1 Definition of Switching Algebra Switching algebra is binary: – All variables and constant take on 0 or 1. • Light on/off, switch: up/down, voltage: low/high... – Quantities which are not naturally binary must be coded into binary format. – Three operators: • OR: a+b • AND: a.b • NOT: a’Page  46
47. 47. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.3 Representations of Algebraic Functions1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  47
48. 48. Basic Properties of Switching Algebra P1: Commutative: • a+b=b+a a.b = b.a P2: Associative: • a + (b + c) = (a + b) + c a.(b.c) = (a.b).c P3: • a+0=a a.1=a P4: • a+1=1 a.0=0Page  48
49. 49. Basic Properties of Switching Algebra  P5: • a + a’ = 1 a . a’ = 0  P6: no coefficient and no exponent • a+a=a a.a=a • n.a=a (a)n=a  P7: complement • (a’)’ = a  P8: distributive: • a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)Page  49
50. 50. Basic Properties of Switching AlgebraBasic Properties of Switching Algebra  P9: adjacency • ab + ab’ = a (a+b)(a+b’)=a  P10: • a + a’b = a +b a(a’+b) = ab  P11: De Morgan • (a + b)’ = a’b’ (ab)’ = a’ + b’  P12: absorption • a + ab = a a(a+b) = a Page  50
51. 51. Basic Properties of Switching Algebra P13: redundant • ab+b’c+ac = ab+b’cPage  51
52. 52. Problems1. Prove the following equalities: a. xy’+y=x+y b. xy+xz’+yz=xy+x’z => prove it incorrect c. x’y’z+yz+xz=z d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1Page  52
53. 53. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.4 Representations of Algebraic Functions1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  53
54. 54. Manipulation of Algebraic Functions A literal: – Is the appearance of a variable or its complement – Eg: x and x’ are two different literals – Expression ab’+bc’d+a’d+e’ has 8 literals A product term: – Is one or more literal connected by AND operators – Expression ab’+bc’d+a’d+e’has 4 product terms – Note: A single literal is also a product termPage  54
55. 55. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A standard product term - minterm: – Is a product term which includes every variable of the function, either uncomplemented or complemented. – Eg: for a function of four variables a,b,c,d: • the product term a’bc’d is a standard product term • the product term a’bd’ is not Page  55
56. 56. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A sum of product - SOP: – Is one or more product terms connected by OR operators – Eg: ab’c+abc’+a’c+a’ »d  A canonical sum – sum of standard product term – Is a sum of products expression where all terms are standard product terms. – Eg: A function of three variables a,b,c: • ab’c + abc’ + abc is a canonical sum • ab’c + abc’ + a is not Page  56
57. 57. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A minimum sum of products: – Is one of those SOP expression for a function that has the fewest number of product terms. – If there is more than one expression with fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals. – Eg: • F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz • F2(x,y,z) = x’y+xy’+xyz • F3(x,y,z) = x’y+xy’+xz • F4(x,y,z) = x’y+xy’+yz F3,F4 are minimum SOP of F1 Page  57
58. 58. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A sum term: – Is one or more literals connected by OR operators – Eg: • a + b’ + c’ • b’  A standard sum term - maxterm: – Is a sum term that includes each variable of the problem, either uncomplemented or complemented – Eg: For a function of four variables x,y,z,t • x+y+z’+t’ is a maxterm • x+y+t’ is not Page  58
59. 59. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A product of sum – POS: – Is one or more sum terms connected by AND – Eg: • (w+x’+y’)(w+y+z’)(w+x+z) •w  A canonical product – product of standard sum terms: – Is a product of sum term where all sum terms are standard Page  59
60. 60. Manipulation of Algebraic FunctionsManipulation of Algebraic Functions  A minimum POS is defined the same way as SOP: – fewest number of terms – the same number of terms => fewest number of literals Page  60
61. 61. Canonical forms Three-variable minterm and Maxterm Decimal x y z minterm Maxterm 0 0 0 0 x’y’z’ (m0) x+y+z (M0) 1 0 0 1 x’y’z (m1) x+y+z’ (M1) 2 0 1 0 xyz’ (m2) x+y’+z (M2) 3 0 1 1 xyz (m3) x+y’+z’ (M3) 4 1 0 0 xy’z’ (m4) x’+y+z (M4) 5 1 0 1 xyz (m5) x+y+z’ (M5) 6 1 1 0 xyz (m6) x+y’+z (M6) 7 1 1 1 xyz (m7) x+y’+z’ (M7)Page  61
62. 62. Canonical forms Properties of minterm/Maxterm: – mimj=0 if i≠j =mi if i=j – Mi+Mj=1 if i≠j = Mi if i=j – mi=Mi’ and Mi=mi’ for every iPage  62
63. 63. Canonical forms An algebraic expression of a Boolean function can be derived from a given truth table in two ways: – By summing (ORing) those minterm for which the function takes a value 1. – By multiplying (ANDing) those maxterm for which the function takes a value 0.Page  63
64. 64. Canonical formsDecimal x2 x1 x0 f 0 0 0 0 0 f(x2,x1,x0)=m1+m4+m5+m6+m7 1 0 0 1 1 =Σ(1,4,5,6,7) 2 0 1 0 0 Canonical sum-of-products (SOP) 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 f(x2,x1,x0)=M0M2M3 7 1 1 1 1 = Π(0,2,3) Canonical product-of-sums (POS)Page  64
65. 65. F(a,b,c)= abc’+a’b’Decimal a b c f 0 0 0 0 1 1 0 0 1 1 F(a,b,c)=m0+m1+m6 2 0 1 0 0 3 0 1 1 0 – ∑(0,1,6) 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0Page  65
66. 66. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.4 Representations of Algebraic Functions1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  66
67. 67. 1.2.4 Representations of Algebraic Functions Truth table Venn diagram Karnaugh mapPage  67
68. 68. Truth table List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables.Page  68
69. 69. Truth table n independent variables and m dependant functions: 2n rows n+m columns 3 independent 2 dependent variables functions 23 rowsPage  69
70. 70. Venn diagram Venn diagram using ‘space’ to present logic F(A,B)=A.B F(A,B,C)=C.not(B)Page  70
71. 71. Venn diagram A A A+B A.B A+B A.BPage  71
72. 72. Karnaugh map A Karnaugh map is a graphical method for representing the true table of a Boolean function. K-map may be used for any variables number, but often at most six. C BC AB A 0 1 00 01 11 10 00 0 1 0 0 1 3 2 01 2 3 1 4 5 7 6 11 6 7Page  72 10 4 5
73. 73. Karnaugh map (K-map) If variables number is n => 2n cells in K-map. 2n cells are arranged in logical pattern for minimization purpose. BC A 00 01 11 10 0 0 1 3 2 1 4 5 7 6Page  73
74. 74. Two-variable K-map F(A,B) B 0 1 A 0 1 A B 0 0 1 0 0 2 1 2 3 1 1 3Page  74
75. 75. Two-variable K-map F(A,B) = AB B 0 1 A 0 0 0 1 0 1Page  75
76. 76. Three-variable K-map F(A,B,C) C AB BC 0 1 A 00 0 1 00 01 11 10 01 0 0 1 3 2 2 3 11 6 7 1 4 5 7 6 10 4 5Page  76
77. 77. Three-variable K-map F(x,y,z) = xyz + yz’ + x zx y z F0 0 0 0 yz xy 0 10 0 1 0 x 0 00 1 0 1 00 01 11 10 000 1 1 0 0 0 0 1 1 0 0 011 0 0 11 0 1 1 1 1 1 1 1 1 111 1 0 1 1 1 11 1 1 1 10Page  77
78. 78. Four-variable K-map  F(A,B,C,D) CD AB 00 01 11 10 00 01 11 10Page  78
79. 79. Four-variable K-map F(A,B,C,D) = AB + CD’ + BCD CD AB 00 01 11 10 0 0 0 1 00 0 0 1 1 01 1 1 1 1 11 0 0 0 1 10Page  79
80. 80. Five-variable K-map E 0 1 CD 00 01 11 10 CD 00 01 11 10 AB AB 00 00 01 01 11 11 10 10 5 variables Karnaugh Map consists of two 4 variables Karnaugh Map connected up/down.Page  80
81. 81. Six-variable K-map F 0 1 E CD 00 01 11 10 CD 00 01 11 10 AB AB 00 1 1 00 1 1 0 01 1 1 01 11 1 1 11 1 1 10 10 1 1 CD 00 01 11 10 CD 00 01 11 10 AB AB 00 1 1 00 1 1 1 01 1 1 01 11 1 1 11 1 1 10 10 1 1Page  81
82. 82. Karnaugh map with don’t care don’t care ~ input conditions that not occurPage  82
83. 83. 1.2. Switching Algebra and Logic Circuits1.2.1 Definition of Switching Algebra1.2.2 Basic Properties of Switching Algebra1.2.3 Manipulation of Algebraic Functions1.2.4 Representations of Algebraic Functions1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR GatesPage  83
84. 84. Basic logic gates  AND OR NOT A B out A B out A out 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1Page  84
85. 85. Basic logic gates NAND NOR XOR A B out A B out A B out 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 0Page  85
86. 86. Implementation of Functions with AND, OR Assume all inputs are available in uncomplemented and complementedF2 = x’y+xy’+xzPage  86 F1 = x’yz’+x’yz+xy’z’+xy’z+xyz
87. 87. Implementation of Functions with AND, OR, NOT Complemented inputs can be produced using inverters NOT: X Y F ZPage  87
88. 88. Multilevel circuits A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output two-level circuit three-level circuitPage  88
89. 89. Implementation of Functions with NAND Using equivalent change steps, every expression can be represented using only NAND gates. OR A NOTA B A.B (A’.B’)’ =A+BB ANDPage  89
90. 90. Implementation of Functions with NAND Represent the following expression using only NAND: – F(a,b,c) = ab + bc’ + b’ = ab + bc + b = ab + bc + b = ab.bc.bPage  90
91. 91. Implementation of Functions with NOR Using equivalent change steps, every expression can be represented using only NOR gates. U8A A U7A A 7402N (A+B)=A.B U9A 7402N B B 7402N U3A A 7402N (A+A)=A U10A U11APage  91 7402N 7402N
92. 92. Implementation of Functions with NOR Represent the following expression using only NOR: – F(a,b,c) = ab + bc’ + b’Page  92
93. 93. Chapter 2.Logic Function Minimization MethodsPage  93
94. 94. 2. Function Minimization Methods2.1 Algebraic Method2.2 The Karnaugh Map Method2.3 Quine-McCluskey MethodPage  94
95. 95. 2. Function Minimization Methods What is minimization? – Number of operands is minimal and number of literal in each operand is minimal Why minimization needed? – Minimize electronic components used to construct the circuit to implement that expressionPage  95
96. 96. 2. Function Minimization Methods 2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method Page  96
97. 97. 2.1. Algebraic Method Use algebraic properties to minimize expressions Drawback: – Heuristic, depending on experience – no formal method/procedure – Manually – Not sure whether the last expression is minimal or notPage  97
98. 98. 2.1. Algebraic Method Eg: Minimize these expressions using algebraic method: – F0(x,y,z)=xyz+x’yz+xy’z+xyz’ – F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’ – F2(A,B,C,D)= ( A + BC ) + A.( B + C )( AD + C ) – F3(x,y,z)=(x+y)(x+y+z’)+y’ – F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)Page  98
99. 99. 2. Function Minimization Methods 2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method Page  99
100. 100. 2.2 The Karnaugh Map Method1. Minimum Sum of Product Expressions Using the Karnaugh Map2. Don’t Cares3. Product of Sums4. Minimum Cost Gate Implementation5. Five- and Six-Variable Maps6. Multiple Output ProblemsPage  100
101. 101. Implicant, Prime Implicant An implicant of a function is a product term that can be used in a SOP CDAB 00 01 11 10 Implicants of F 00 1 1 Minterm Groups of 2 Groups of 4 A’B’C’D’ A’CD AB A’B’CD BCD 01 1 A’BCD ABC’ ABC’D’ ABD 11 1 1 1 1 ABCD’ ABC ABC’D ABD’ ABCD 10Page  101
102. 102. Implicant, Prime Implicant A prime Implicant is an implicant which can not be contained in any other implicants. CD CD BC AB * 00 01 11 10 B D 00 1 1 1 01 1 1 B D* 11 1 1 AD AB 10 1 1 1 1Page  102
103. 103. Essential Prime Implicant  Essential PI is a PI which contains at least one minterm which is not contained in other PI. CD CD BC AB * 00 01 11 10 B Dminterm 0 is only contained in PI B’D’ 00 1 1 1minterm 5 is only contained in PI BD=> BD & B’D’ are two Essential PI 01 1 1 B D* 11 1 1 AD AB 10 1 1 1 1 Page  103
104. 104. 2.2.1 Minimum Sum of Product Expressions Rules to minimize using K-map: – Rule 1: Fill K-map cells with corresponding values – Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n. – Rule 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.Page  104
105. 105. 2.2.1 Minimum Sum of Product Expressions  Step 2: Group adjacent cells whose values are 1. Number of cells is 2n. CD CD AB AB 00 01 11 10 00 01 11 10 00 00 1 1 01 1 1 01 1 1 11 1 1 11 1 1 10 1 1 10 1 1Page  105
106. 106. 2.2.1 Minimum Sum of Product Expressions Step 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables. CD AB 00 01 11 10 21 cells => eliminate 1 variable 00 01 1 1 F(A,B,C,D) = A’BC’ + AC 11 1 1 22 cells => eliminate 2 variables 10 1 1Page  106
107. 107. 2.2.1 Minimum Sum of Product Expressions Example 1: Minimize these functions using K-map: – a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14) – b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15) – c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13) – d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15) – e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)Page  107
108. 108. – a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14) = BC’D + AB’D + BCD’ + A’B’D’ CD AB 00 01 11 10 00 1 1 01 1 1 1 11 1 10 1 1Page  108
109. 109. – b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14) = B’D + BD’ CD AB 00 01 11 10 1 1 00 1 01 1 1 11 1 10 1 1Page  109
110. 110. 2.2 The Karnaugh Map1. Minimum Sum of Product Expressions Using the Karnaugh Map2. Don’t Cares3. Product of Sums4. Minimum Cost Gate Implementation5. Five- and Six-Variable Maps6. Multiple Output ProblemsPage  110
111. 111. 2.2.2 Don’t care If the function has don’t care values in cells: – Cells with don’t care values can be grouped with ‘1’ cells – Do not group only don’t care cells in one group. F ( A, B, C , D) = BC + BCPage  111
112. 112. Examples: F(a,b,c,d)=R(1,3,5,7,12,13) don’t care (0,4,10,15) CD AB 00 01 11 10 00 - 1 1 01 - 1 1 11 1 1 - 10 -Page  112
113. 113. 2. Function Minimization Methods 2.1 Algebraic Method 2.2 The Karnaugh Map Method 2.3 Quine-McCluskey Method Page  113
114. 114. 2.3 Quine-McCluskey Method1. Quine-McCluskey Method for One Output2. Iterated Consensus for One Output3. Prime Implicant Tables for One Output4. Quine-McCluskey for Multiple Output Problems5. Iterated Consensus for Multiple Output Problems6. Prime Implicant Tables for Multiple Output ProblemsPage  114
115. 115. 2.3. Quine-Mcluskey method Karnaugh map cannot handle more than 6 variables. Quine-McCluskey method has no limitation with number of variables, and is suitable for computer algorithm. ABC+ABC+ABC+ABC+ABC C 010 110 111 100 101 AB 0 1 00 01 1 *10 11* 1*0 1*1 10* 11 1 1 10 1 1 1**Page  115 find a pair of numbers of 1 bit difference
116. 116. Quine-Mcluskey Procedure 1: Represent minterms in binary numbers 2: Group each minterm by the number of ‘1’ appearance 3: Make set of 1 bit different numbers between neighboring group • write the difference within parenthesis • mark * to the number which is not included in a set 4: Make set of 1 bit different sets with the same number in a parenthesis • append the difference to parenthesis • mark + to the set which is not included in a set 5: Iterate these step until all the generated set is marked * 6: Select prime implicants 7:116Page  Convert to logic variable
117. 117. S1. Represent minterms in binary numbers f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10) f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010Page  117
118. 118. S2. Grouping f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 group each term by the appearance of 1 group 0 group 1 group 2 group 3 group 4 no times once twice three times four times 000000 000010 000110 000111 001111 001000 001100 001110 001010 101001Page  118
119. 119. S3 & S4. Making set (1)group 0 000000 0 0,2 (2) 0,8 (8) find a pair of 1 bit differencegroup 1 000010 2 between neighboring group 001000 8 2,6(4) write difference within ( ) 2,10(8)group 2 000110 6 8,10(2) 001010 10 001100 12 8,12(4) mark to the number 6,7(1) 000111 7 not included in any setgroup 3 6,14(8) 001110 14 10,14(4) 101001 41 12,14(2)group 4 001111 15 7,15(8)Page  119 14,15(1)
120. 120. S3 & S4. Making set (2) find a pair of 1 bit different sets 0,2 (2) 0,2,8,10(2,8) with the same value in ( ) 0,8 (8) between neighboring group append difference within ( ) 2,6(4) 2,10(8) 2,6,10,14(4,8) Each pair appears in duplicate 8,10(2) 8,10,12,14(2,4) 8,12(4) mark to the set 6,7(1) not involved 6,14(8) in the next level set 10,14(4) 12,14(2) 6,7,14,15(1,8) when all the set is marked finish 7,15(8) 14,15(1)Page  120
121. 121. S6. Selecting Prime Implicants (1) minterms (given at first) Prime implicant 0 2 6 7 8 10 12 14 15 41 41 x 0,2,8,10(2,8) x x x x 2,6,10,14(4,8) x x x x 8,10,12,14(2,4) x x x x 6,7,14,15(1,8) x x x x （ 　 marked write x into the position where minterm is included inevitable in the prime implicant implicant ） If only one x in a column, then the row is inevitable implicantPage  121
122. 122. S6. Selecting Prime Implicants (2) mini term 0 2 6 7 8 10 12 14 15 41 x prime implicants 41 0,2,8,10(2,8) x x x x 2,6,10,14(4,8) x x x x 8,10,12,14(2,4) x x x x 6,7,14,15(1,8) x x x x mark minterms involved in the inevitable implicants inevitable implicantsPage  122
123. 123. S7. Conversion to logic variables 41 101001 ABCDEF 000000 000010 ABDF 0,2,8,10(2,8) 001000 001010 F=ABCDEF 001000 +ABDF 8,10,12,14(2,4) 001010 +ABCF ABCF 001100 +ABDE 001110 000110 6,7,14,15(1,8) 000111 ABDEPage  123 001110 001111
124. 124. Examples: Minimize the following functions using Quine- Mcluskey method: – a. F(a, b, c, d, e, f) = ab def + abce f + bcd f + ab d e f – b. F(a,b,c,d,e,f) = ∑(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)Page  124
125. 125. Quine-Mcluskey method with don’t care 1: Represent logic function in sum of mini terms ==>A 2: Represent don’t care in sum of mini terms ==>B 3: If there exist duplication in A and B, remove from A 4: Apply Quine-McCluskey method for A and B 5: Be careful not to include B in selecting prime implicantsPage  125
126. 126. Quine-Mcluskey method with don’t care f=ABCD+BCD+ACD+ABCD+ABCD don’t care AD mini term decimal first comparison second comparison ABCD 0,1(1) 0000 0 0,2(2) 0,1,2,3(1,2) 0001 1 1,3(2) 0010 2 1,5(4) 0011 3 2,3(1) 1,3,5,7(2,4) 0101 5 3,7(4) 0111 7 3,11(8) 1011 11 5,7(2) 3,7,11,15(4,8) 1101 13 5,13(8) 5,7,13,15(2,8) 1111 15 7,15(8) 11,15(4)Page  126 13,15(2)
127. 127. Quine-Mcluskey method with don’t care 0 2 11 13 15 ABCD 0,1,2,3(1,2) x x 00** 1,3,5,7(2,4) 0**1 3,7,11,15(4,8) x x **11 5,7,13,15(2,8) x x *1*1 f=AB+CD+BDPage  127
128. 128. Chapter 3.Larger Combinational SystemsPage  128
129. 129. Introduction Logic circuits are divided into two classes: – Combinational logic circuits • Output signals only depend on current input signals • Memoryless circuits – Sequential logic circuits • Output signals not only depend on current input signals, but also depend on those input signals in the past • Memory circuitsPage  129
130. 130. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  130
131. 131. 3.1 Delay in Combinational Logic Circuits  Delay through logic gates – When the input to a gate changes, the output of that gate doesn’t change immediately; but there is a small delay Δ. – The output is stable after the longest delay pathA XB FC Page  131
132. 132. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  132
133. 133. Half Adder a b Σ r 0 0 0 0 Σ=a ⊕ b a HA Σ (Result) 0 1 1 0 b r (Carry-out) 1 0 1 0 r = ab 1 1 0 1 a =1 Σ Half Adder b & rPage  133
134. 134. Addition of two n-bit numbers r3 r2 r1 r0 A= a3 a2 a1 a0 +B = b3 b2 b1 b0 r4 Σ3 r3 Σ2 r2 Σ1 r1 Σ 0Summation Σ4 Σ3 Σ2 Σ1 Σ0Page  134
135. 135. Full Adder Σ ai Σi aibi 00 01 i 11 10 FA ri ri bi ri+1 0 1 1 1 1 1 ai bi ri Σi ri+1 0 0 0 0 0 aibi 00 01ri+1 11 10 0 0 1 1 0 ri 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 0 1 Σ i = a i ⊕ b i ⊕ ri 1 1 1 1 1 ri+1 = ai bi + ri (ai ⊕ bi)Page  135
136. 136. Combinational logic circuit design procedure Problems: design a combinational logic circuit to do smth. Design procedure: – S1: Find inputs, outputs and relations. – S2: Construct truth table – S3: For each output, using K-map to minimize from truth table. – S4: Draw the circuit.Page  136
137. 137. Example 1 Problem: Design a combinational logic circuit to implement this operation: M=N+3, N is 3-bit binary number, the number of bit of M is selected properly. Solution: – S1: three inputs: n2n1n0 four outputs: m3m2m1m0Page  137
138. 138. Example 1 S1: three inputs: n2n1n0 four outputs: m3m2m1m0 n2 m3 S2: truth table n1 m2 n0 m1 m0 n2 n1 n0 m3 m2 m1 m0 0 0 0 0 0 1 1  S3: 0 0 1 0 1 0 0 0 1 0 0 1 0 1 m3 = n2n0 + n2n1 0 1 1 0 1 1 0 n1n0 00 01 11 10 1 0 0 0 1 1 1 n2 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 0Page  138
139. 139. Example 2 Problem: design a combinational logic circuit to calculate square of a 2-bit binary number. Solution: – Step1: find inputs, outputs • Inputs: a1,a0 • Outputs: b3,b2,b1,b0 Ex2Page  139
140. 140. Example 2 – Step 2: truth table a1 a0 b3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 – Step3: using K-map to minimize outputs • b3 = a1.a0 b1 = 0 • b2 = a1.a0’ b0 = a0Page  140
141. 141. Example 2 – Step 4: Draw circuit • b3 = a1.a0 b1 = 0 • b2 = a1.a0’ b0 = a0 X1 2.5 V b3 X2 U1A 2.5 V J1 b2 X3 a1 7408N V1Key = A R1 U1B 2.5 V 5V b1 X4 100Ω a0 7408N 2.5 V b0 U2A J2 7404N V2Key = B R2 12 V 100ΩPage  141
142. 142. Full Adder ri =1 =1 ai Σi bi & & ≥1 ri+1Page  142
143. 143. Full Adder ri =1 =1 ai Σi bi HA HA & & ≥1 ri+1Page  143
144. 144. n-bit Adder  Serial n-bit adder A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0 an-1 bn-1 an-2 bn-2 a1 b1 a0 b0 rn-1 rn-2 r1 r 0= 0 FA FA FA FA rn r2 Σn Σ n-1 Σ n-2 Σ1 Σ0Page  144 Delay = n x Δ?
145. 145. n-bit Adder  Parallel n-bit adder: ri+1 = aibi + ri(ai ⊕ bi) Pi = ai ⊕ bi and Gi = aibi → ri+1 = Gi + ri Pi G0 ≥ 1 r1 r1 = G0 + r0P0 G1 ≥ 1 r2 P0 & r0 G0 & τ1 τ2 P1 & r2 = G1 + G0P1 + r0P0P1 P0 r0Page  145 τ1 τ2
146. 146. Parallel 4-bit addition a3 b 3 a2 b2 a1 b1 a0 b0 r0 Calculate Pi and Gi P3 G3 P2 G2 P1 G1 P0 G0 Carry calculation r4 r3 r2 r1 r0 a3 b3 a2 b2 a1 b1 a0 b0 Sum calculation r4 = Σ 4 Σ3 Σ2 Σ1 Σ0Page  146
147. 147. Subtractor To subtract a-b, simply add a to 2’s complement of b. Second choice:Half Subtractor => Full Subtractor => n-bit SubtractorPage  147
148. 148. Subtractor Subtractor by using 2’s complement B3 B2 B1 B0 A3 A2 A1 A0 A B A B A B A B C4 C+ FA C C+ FA C C+ FA C C+ FA C 1 S C3 S C2 S C1 S S3 S2 S1 S0Page  148
149. 149. Adder and Subtractor A3 B3 A2 B2 A1 B1 A0 B0 MPX MPX MPX MPX sel A B A B A B A B C4 C+ FA C C+ FA C C+ FA C C+ FA C S C3 S C2 S C1 S S3 S2 S1 S0Page  149
150. 150. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  150
151. 151. Decoder An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines, where m≤2n. – m = 2n => complete decoder Fundamental property: only one output is 1 for any given input combination.Page  151
152. 152. Decoder Complete decoders: m=2n Eg: + 3 bit inputs x1,x2,x3. + 8 bit outputs Y0,Y1…Y7Page  152
153. 153. Design 3x8 decoder En if (En=0) Disable or D0...D7=0 else if (En=1) Function as a 3x8 decoderPage  153
154. 154. BCD-to-decimal decoder N A B C D Y0 Y1 . Y9 . 0 0 0 0 0 1 0 . 0 . 1 0 0 0 1 0 1 . 0 Y0 . 2 0 0 1 0 0 0 . 0 A BCD Y1 . B to : 3 0 0 1 1 0 0 . 0 C . decimal Yi 4 0 1 0 0 0 0 . 0 D Decoder : . 5 0 1 0 1 0 0 . 0 Y9 . 6 0 1 1 0 0 0 . 0 . 7 0 1 1 1 0 0 . 0 . 8 1 0 0 0 0 0 . 0 . 9 1 0 0 1 0 0 . 1Page  154
155. 155. BCD-to-decimal decoder Y0 = A B C D Y1 = A B C D CD AB 00 01 11 10 Y2 = BCD 00 1 Y3 = BCD 01 Y4 = BC D Y5 = BC D 11 − − − − Y6 = BC D 10 − − Y7 = BCD Y8 = AD Y9 = ADPage  155
156. 156. Decoder 4x16 decoder using two 3x8 decodersPage  156
157. 157. Decoder implementation of arbitrary functions F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)Page  157
158. 158. BCD-to-7segment decoder a f g b N A B C D a b c d e f g e c 0 0 0 0 0 1 1 1 1 1 1 0 d 1 0 0 0 1 0 1 1 0 0 0 0 Each segment is a Light 2 0 0 1 0 1 1 0 1 1 0 1 Emitting Diode (LED) 3 0 0 1 1 1 1 1 1 0 0 1 4 0 1 0 0 0 1 1 0 0 1 1 5 0 1 0 1 1 0 1 1 0 1 1 A K 6 0 1 1 0 1 0 1 1 1 1 1 7 0 1 1 1 1 1 1 0 0 0 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 1 0 1 1Page  158
159. 159. BCD-to-7segment decoder CD AB 00 01 11 10 & B 00 1 0 1 1 D 01 0 1 1 1 11 − − − − & ≥1 10 1 1 − − A C a = A + C +BD +B DPage  159
160. 160. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  160
161. 161. Encoder An encoder is a circuit that performs the function of a decoder in reverse. An mxn encoder has m inputs, n outputs where m≤2n. The outputs generate the binary codes corresponding to m inputs. For example: encoder for PC’s keyboard Key <=> Character <=> Key code 102 keys, 8 bit ASCIIPage  161
162. 162. Keyboard encoder ‘1’ P1 1 P2 A 2 B Pi N=i i Encoder C P9 D 9 9 keys 4-bit key code.Page  162
163. 163. Keyboard encoder N ABCD 1 0001 2 0010 A = 1 if (N=8) or (N=9) 3 0011 B = 1 if (N=4) or (N=5) or (N=6) or (N=7) 4 0100 C = 1 if (N=2) or (N=3) or (N=6) 5 0101 or (N=7) 6 0110 D = 1 if (N=1) or (N=3) or (N=5) 7 0111 or (N=7) or (N=9) 8 1000 9 1001Page  163
164. 164. Keyboard encoder N=1 ≥ 1 D N=2 N=3 ≥ 1 N=4 C N=5 N=6 ≥ 1 B N=7 N=8 ≥ 1 A N=9Page  164
165. 165. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders 3.5 Multiplexors 3.6 Demultiplexors 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  165
166. 166. Multiplexor  Multiplexor has one output and more than one input.  Function: select one of input for output MUX 2-1 MUX 4-1 X0 X0 X1 Y Y X2 X1 X3 C0 C0 C1 control inputs C1 C0 Y C0 Y 0 0 X0 0 X0 0 1 X1 1 0 X2Page  166 1 X1 1 1 X3
167. 167. 2-to-1 Multiplexor MUX 2-1 C0 X1 X0 Y X0 Y C0 Y 0 0 0 0 X1 0 X0 0 0 1 1 0 1 0 0 1 X1 C0 0 1 1 1 1 0 0 0 C0 X1X0 00 01 11 10 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 Y = X 0C0 + X1C0Page  167
168. 168. 2-to-1 MultiplexorPage  168
169. 169. 4-to-1 Multiplexor Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3Page  169
170. 170. Application of multiplexor  Select source Source 1 Source 2A = a3 a2 a1 a0 B = b3 b2 b1 b0 C0 Receiver Y3 Y2 Y1 Y0 Page  170
171. 171. Application of multiplexor Convert parallel-serial A C0a0 1a1 Y 0a2 C1 ta3 1 0 tC0 YC1 a0 a1 a2 a3 tPage  171
172. 172. Application of multiplexor Implementation of arbitrary functions: f(A,B) = A Bf(0,0) + A Bf(0,1) + A Bf(1,0) + A Bf(1,1) Y = C1C 0 X 0 + C1C 0 X1 + C1C 0 X 2 + C1C 0 X 3 f(0,0) x0 f(0,1) x1 Y = f(A,B) Inputs to select f(1,0) function x2 f(1,1) x3 C1 C0 APage  172 Variables B
173. 173. Example 0 x0 1 x1 Y = f(A,B) Inputs to select 1 function x2 0 x3 C1 C0 A Variables B F(A,B) = A’B + AB’Page  173
174. 174. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders and Priority Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  174
175. 175. Demultiplexor  Demultiplexor has one input and more than one output  Function: select one of outputs for input DeMUX 1-2 S0 E S1 C0 S 0 = C0 E S1 = C0 EPage  175
176. 176. Demultiplexor 1-4 S0 S1 E S2 S3 C1 C0Page  176
177. 177. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders and Priority Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  177
178. 178. 3.7 Three-State Gates (Tristate) Three state gates exhibit three states instead of two states. The three states are: – High : 1 – Low : 0 – High impedance : z • In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant. We can have AND or NAND three-state gates but the most common is three- state buffer gatePage  178
179. 179. 3.7 Three-State Gates (Tristate) We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate. Note that buffer produces transfer function and can be used for power amplification. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide)Page  179
180. 180. Three-State buffer Three-state buffer C A Y ---------------------- 0 0 z 0 1 z 1 0 0 1 1 1Page  180
181. 181. Application of three-state buffer Three-state buffers can be used to implement multiplexer Page  181
182. 182. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders and Priority Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays - ROMs, PLAs and PALs 3.9 Larger ExamplesPage  182
183. 183. 3.8 Gate Arrays - ROM, PLA and PAL PLA - Programmable Logic Arrays PAL - Programmable Array Logic ROMPage  183
184. 184. PLA - Programmable logic arrays  Pre-fabricated building block of many AND/OR gates – actually NOR or NAND – "personalized" by making or breaking connections among the gates – programmable array block diagram for sum of products form A B C Z1 Z2 • • •m0 0 0 0 0 1 inputsm1 0 0 1 0 0m2 0 1 0 1 1m3 0 1 1 0 0 ORm4 1 0 0 0 1 AND product arraym5 1 0 1 1 0 array termsm6 1 1 0 1 1m7 1 1 1 1 0 outputs Page  184 • • •
185. 185. Before programming All possible connections are available before "programming" – in reality, all AND and OR gates are NANDsPage  185
186. 186. After programming Unwanted connections are "blown" – fuse (normally connected, break unwanted ones) – anti-fuse (normally disconnected, make wanted connections) A B C AB BC AC BC APage  186 F0 F1 F2 F3
187. 187. PLA example Multiple functions of A, B, C – F1 = A B C full decoder as for memory address – F2 = A + B + C bits stored in memory A B C – F3 = A B C ABC – F4 = A + B + C ABC – F5 = A xor B xor C ABC – F6 = A xnor B xnor C ABC ABC A B C F1F2F3F4 F5F6 ABC 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 ABC 0 1 0 0 1 0 1 1 1 ABC 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 F1 F2 F3 F4 F5Page  187 1 1 0 0 1 0 1 0 0 F6
188. 188. PALs and PLAs Programmable logic array (PLA) – what weve seen so far – unconstrained fully-general AND and OR arrays Programmable array logic (PAL) – constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product termsPage  188
189. 189. ROM – Read Only Memories Two dimensional array of 1s and 0s – entry (row) is called a "word" word lines (only one is active – decoder is – width of row = word-size just right for this) – index is called an "address" 1 1 1 1 – address is input n – selected word is output 2 -1Example: i word[i] = 001110 address x 8 data ROM decoder210 words x 8 ROM j word[j] = 10101024 words x 8 ROM1k x 8 ROM 0 internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)Page  189
190. 190. ROM – Read Only Memories  Combinational logic implementation (two-level canonical form) using a ROM F0 = A B C + A B C + A B C F1 = A B C + A B C + A B C F2 = A B C + A B C + A B C F3 = A B C + A B C + A B C A B C F0 F1 F2 F3 0 0 0 0 0 1 0 ROM 0 0 1 1 1 1 0 8 words x 4 bits/word 0 1 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 A B C F0 F1 F2 F3 1 1 0 0 0 0 1 address outputs 1 1 1 0 table0 truth 1 0 block diagramPage  190
191. 191. ROM structure Similar to a PLA structure but with a fully decoded AND array – completely flexible OR array (unlike PAL) n address lines • • • inputs memory decoder 2n word array n (2 words lines by m bits) outputs • • • m data linesPage  191
192. 192. 3. Larger Combinational Systems 3.1 Delay in Combinational Logic Circuits 3.2 Adders and Other Arithmetic Circuits 3.3 Decoders 3.4 Encoders and Priority Encoders 3.5 Multiplexers 3.6 Demultiplexers 3.7 Three-State Gates 3.8 Gate Arrays-ROMs, PLAs and PALs 3.9 Larger ExamplesPage  192
193. 193. 3.9 Larger Examples 1. Seven-segment displays 2. ComparatorPage  193
194. 194. Comparator  1-bit full comparator: ai > bi Gi=1 Gi = ai .bi ai < bi Li=1 Li = ai .bi ai = bi Ei=1 Ei = ai ⊕ biPage  194
195. 195. Comparator N-bit parallel comparator:Page  195
196. 196. Midterm examination (90’) 1. Represent the following function in the canonical form SOP: F(A,B,C)=(A+B’)C 2. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15) 3. Design 4x16 decoder using only 2x4 decoders. 4. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).Page  196
197. 197. Midterm examination 2 (90’) 1. Represent the following function in the canonical form SOP and POS: F(A,B,C)=C 2. Use the Quine-McCluskey method to obtain the minimal sum for the following function: F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15) 3. Using 3x8 decoder to implement the following function: F(A,B,C) = AB + B’C 4. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).Page  197
198. 198. Chapter 4.Sequential SystemsPage  198
199. 199. 4. Sequential Systems 4.1 Definitions 4.2 State Tables and Diagrams 4.3 Latches and Flip Flops 4.4 Analysis of Sequential Systems 4.5 Design of Sequential Systems 4.6 Solving Larger Sequential ProblemsPage  199
200. 200. 4.1 Definitions Combinatorial circuit is memoryless. In a circuit with memory, an output value at tn+1 must be a function not only of the inputs at tn+1 but also of the outputs at tn . To achieve this, the circuit must have some feedback connections from its outputs to its inputs. A circuit with memory is a combinatorial circuitPage  200 incorporating some feedback connections.
201. 201. Feedback and memory devices To implement feedback, signals are fed back from outputs to inputs using memory devices. A memory device stores an output value at time t n so that it can be input to the circuit at tn+1. But then, output at tn depends on input at tn-1, which in turn depends on tn-2… The circuit maps input sequences to output sequencesPage  201
202. 202. Sequential circuit model  Circuits with memory are called sequential circuits. Circuit inputs Circuit outputs Present state Next statePage  202
203. 203. Sequential circuit model Mealy model: • X : finite inputs. m inputs: x1,x2...,xm • S : finite states. n states: s1,s2...,sn • Y: finite outputs.l outputs: y1,y2...,yl • Fs: state function. s = Fs(X,S) • Fy : output function. y = Fy(X,S) Moore: ~Mealy • Difference: Fy = Fy(S)Page  203
204. 204. Asynchronous/Synchronous sequential circuits The timing of the signal in the circuit determine two types of sequential circuits: – Synchronous – Asynchronous.Page  204
205. 205. Synchronous sequential circuits In a synchronous sequential circuit, the state can change only at discrete instants of time. To achieve that, the circuit uses a timing device, called a clock generator, that produce trains of periodic or aperiodic clock pulses. The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence. The operation of the circuit is synchronized with the clock pulse input.Page  205
206. 206. Asynchronous sequential circuits The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time. There is no timing device in asynchronous sequential circuit (unclocked memory).Page  206
207. 207. 4. Sequential Systems 4.1 Definitions 4.2 State Tables and Diagrams 4.3 Latches and Flip Flops 4.4 Analysis of Sequential Systems 4.5 Design of Sequential Systems 4.6 Solving Larger Sequential ProblemsPage  207
208. 208. State diagram Depict graphically the operation of a sequential circuit. – Mealy state diagramPage  208
209. 209. Example of state diagram Example: a sequential circuit is used to detect the string “0101” from one input. 1 /0 0 /0 0 /0 0 /0 1 /0 0 /0 A B C D 1 /0 1 /1Page  209
210. 210. State diagram Depict graphically the operation of a sequential circuit. – Moore state diagramPage  210
211. 211. State table State table presents in a tabular form the same information contained in the state diagram. – Mealy state table – Moore state tablePage  211
212. 212. Mealy state table PS: Present State NS: Next State PS NS Output (z) x=0 x=1 x=0 x=1 PS NS/Output (z) a b a 0 0 x=0 x=1 b b c 0 0 a b/0 a/0 b b/0 c/0 c d a 0 0 c d/0 a/0 d b c 0 1 d b/0 c/1 k memory devices => 2k rows n circuit inputs => NS portion contains 2n columnsPage  212 Output portion also contains 2n columns
213. 213. Moore state table PS NS Output x=0 x=1 z a b a 0 b b c 0 c d c 0 d d e 0 e f e 1 f f a 1 The output portion always contains a single column. The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row.Page  213
214. 214. Incompletely specified Mealy state table Two inputs: x1,x2 A single output: z PS NS/Output (z) 00 01 11 10 a -/- c/1 b/- e/1 b e/0 -/- -/- -/- c f/0 f/1 -/- -/- d a/- -/- e/- b/1 e -/- f/0 d/1 a/0 f c/0 -/- c/1 b/0Page  214
215. 215. 4. Sequential Systems 4.1 Definitions 4.2 State Tables and Diagrams 4.3 Latches and Flip Flops 4.4 Analysis of Sequential Systems 4.5 Design of Sequential Systems 4.6 Solving Larger Sequential ProblemsPage  215
216. 216. 4.3. Latches and Flip-Flops Simplest memory devices: Delay element Yi yi ΔT Yi yi yi(t+ΔT) = Yi(t) ΔT In practice, we don’t have to actually insert delay elements because propagation time delays between the inputs and the outputs of the combinatorial part of the circuit providePage  216 sufficient delay across the feedback loops.
217. 217. 4.3. Latches and Flip-Flops Bistable devices: – Two stable states: • Q=0 : the device is reset (reset state) • Q=1: the device is set (set state) – A bistable device remains in one of two states indefinitely until directed by an input signal to change state. – Two types: • Latch • Flip-flopPage  217
218. 218. 4.3. Latches and Flip-Flops Latch: transparency property: – Change state when the input values change – The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch. – Used to implement the memory part of asynchronous circuits. Flip-flop: no transparency property – Has a control (triggering) input, called clock. – The state change only in response to a transition of a clock pulse at clock input. – Used to implement memory part of synchronous circuitsPage  218
219. 219. SR Latch Two inputs: S (set), R (reset) Two complementary outputs: Q, Q’ S Q Current state S R Q Q+ R Q’ Next state 0 0 0 0 S 0 0 1 1 Q 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 Q R 1 1 0 - 1 1 1 - Indeterminate Q = (R+Q’)’Page  219 Q’= (S+Q)’
220. 220. SR Latch S Q R Q’ S Q S R Q+ 0 0 Q 0 1 0 • 0 1 Q 1 1 Indeterminate R Equivalent characteristic table SR=’00’ => Output no change A logic ‘1’ at inputs can change outputs’ states => active-HIGH latchPage  220
221. 221. SR Latch S Q S Q R Q’ R Q’ S Q Q S Q R R Q active-HIGH SR Latch active-LOW SR LatchPage  221
222. 222. SR Latch  Timing chart (NOR implementation)S S Q RR Q Q Q set reset set reset Page  222