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Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
Ee660 ex 25_second_order_effects_schwappach
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Ee660 ex 25_second_order_effects_schwappach

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  • 1. MOSFET SECOND ORDER EFFECTS GATE OXIDE THICKNESS REDUCTION Loren K. Schwappach EE660 Modern Electronic Design 2 November 20111
  • 2. Why Shrink MOSFETS2  70% Reduction of Line Width Results in 50% Reduction in Area (i.e. 0.7x0.7=0.49):  Significantly Reduces Cost per Circuit  Other Parameters Reduced as a Result:  Power Supply Voltage  Gate Oxide Thickness  Changes Together Allow:  Reduced Circuit Delays  Historically Circuit Speed Has Increased 30% At Each Tech Node
  • 3. Factors Affecting Scaling3  Requires Threshold Voltage Reduction  Improves Propagation Delays  Low Threshold Affects Noise Margins and Sub- Threshold Conduction  Gate Oxide Thickness Reduction Increases Gate Leakage Due to Electron Tunneling and Hot Carrier Injection from Substrate to Gate
  • 4. Scaling Parameters4
  • 5. Reducing the Gate Insulator Thickness5  SiO2:  Preferred Gate Insulator from the Beginning  TOX=300nm for 10um technology to 1.2nm for 65nm technology  Thinner Oxides Result in Faster Circuits!  Oxide Thickness has been Scaled Roughly in Proportion to Line Width
  • 6. Problems Resulting From Reduced TOX6  Oxide Breakdown Caused By Electric Field  Loss of Inversion Charge Due to Polysilicon Gate Depletion and Inversion Layer Quantization Effects  Long Term Operation at High Field and High Temperatures Breaks Weaker Atomic Bonds:  Creating Oxide Charge and VT Shifts  SiO2 thinner than 1.5nm suffers from Extreme Tunneling Leakage  Would Drain Battery of a Cell Phone in Minutes!
  • 7. Transistor Leakage7  Increases in Leakage Power with Technology Scaling
  • 8. How Are Defects Injected in Oxide8  Pinch-off Region Near Drain-Substrate Junction of n- channel MOSFET
  • 9. PhotoInjection of Hot-Carriers9
  • 10. Gate Leakage10  Reduction in Oxide Thickness Results in Higher Electric Field  Electrons can Tunnel Through Oxide, Causing Leakage  Occurs when VOX < the Tunneling Barrier Height
  • 11. Solutions to Shrinking TOX11  High-k dielectrics to replace SiO2  Example: HfO2 has Dielectric Constant (k) of 24 (Six Times That of SiO2)  Other Candidates Include ZrO2 and Al2O3  Often Requires Inserting Thin SiO2 Interfacial layer Between Silicon Substrate and High-k Dielectric to Reduce Unwanted Chemical Reactions
  • 12. Modifying the SPICE Model12  Note: PSPICE Levels 2-4 are only Accurate for Models >1um  Recommended PSPICE Level 5 Model (Used for Short Channel Effects Correction) and Accounting for COX  Scaling Factor from Ex 23 was .36 Going from 5V to 1.8V Circuit (Adjusted VTO Accordingly)  Original COX Set to 7E-4 (Default)  COX = EOX/TOX  Results to Analyze:  How COX*2 Changes Effect Circuit Power Usage  How COX*2 Changes Effect Circuit Speed
  • 13. Schematic13 GND_0 GND_0 GND_0 VDD1 VDD2 1.8Vdc 1.8Vdc 0 PMOS1 PMOS2 Mbreakp1 Mbreakp2 W = 30u W = 30u VGate L = .36u L = .36u GND_0 Vout1 Vout2 1.8Vdc NMOS1 NMOS2 C1 C2 40p 40p Mbreakn1 Mbreakn2 W = 14.4u W = 14.4u L = .36u L = .36u GND_0 GND_0 GND_0 GND_0
  • 14. NMOS1 and PMOS1 Models14
  • 15. NMOS2 and PMOS2 Models15
  • 16. Results16
  • 17. Results17
  • 18. Results18
  • 19. Results19
  • 20. Conclusions20  PSPICE Proved Useful For Analyzing Second Order Oxide Thickness Effects  Lowering the Gate Oxide Thickness Reduced Power Usage (By 1mV During Switching)  Lowering the Gate Oxide Thickness Also Decreased the Max Switching Frequency (6.3MHz to 6MHz)  Scaling Parameters and Model Level Played a Huge Impact for Obtaining Usable PSPICE Results  Gate Oxide Thickness Has a Tremendous Impact On the Power and Frequency of a Circuit
  • 21. Questions?21
  • 22. References22  http://etd.library.vanderbilt.edu/available/etd- 12032003-100902/unrestricted/Thesis.pdf  http://www.smdp.iitkgp.ernet.in/PDF/TCAD/AK M.pdf

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